SU1589366A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and can be used in communication technology, in radar and measurement systems for generating frequencies. The purpose of the invention is to expand the range of synthesized frequencies. The synthesizer contains a clock pulse generator 1, a frequency divider 2, a frequency code generation unit 3, a control code generator 4, a phase accumulator 5 and 6, a code multiplier 7, a summation unit 8, a pulse distributor 9, registers 10,12 and 14 memories, block of permanent memory (BPP) 11, switchboard 5 PHASES - CODE OF THE CURRENT PHASE A OF THE SYNTHESIZED VIBRATION, ISKRETNO change in increments ΔA = M .N. The multiplier 7 codes forms codes 2M, 3M, ... (N-1) M, and in block 8 of summation the code of the current phase A is added to the output codes of the multiplier 7 codes. The control unit 11 consists of N memory blocks, the outputs of which through the switch 13 are fed to the input of the DAC 15. REGISTERS 10 AND 12 A SERVICE FOR ALIGNMENT DELAYS. SWITCH 13 CONTROL BY OUTPUT CODE DISTRIBUTOR 9 PULSES. QUICKLY DETERMINED DAC 15, register 14 and the switch 13. 1 Il.

Description

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Phases 5 and 6, a multiplier of 7 codes, a summation block 8, a distributor of 9 pulses, registers 10, 12 and 14 of memory, a block of permanent memory (BPP) 11, switch 13, CLP 15 and a low-pass filter (LPF ) 16. Synthesis of phase samples is produced in successively connected accumulators of phases 5 and 6, operating at a clock frequency that is n times less than the frequency of generator 1. The output signal of phase accumulator 5 is; Lebani discretely varying with step

The invention relates to radio engineering and can be used in communication technology in radar and measurement systems for shaping; frequencies.

The purpose of the invention is to expand the range of synthesized frequencies.

The drawing shows a structural electrical circuit of a digital frequency synthesizer.

The digital frequency synthesizer contains a 1 such oscillator. pulses (GTI), frequency divider 2, frequency code generation unit 3, control code generator 4, first 5 and second

a swarm 6 phase pins, a multiplier 7 Cod, a summation block 8, a pulse distributor 9, a second register 10 of memory, a block of 11 permanent memory, a third register 12 of memory, a switch 13, a first register of memory 14, a digital-analog converter ( DAC) 15 and a 16 low pass filter.

The digital frequency synthesizer works as follows

From block 3, the binary code of the number t, which determines the output frequency fj ,, yy f ,,,. m / 2 where m - takes the value

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VIA from 1 to 2; frrn the reference frequency of the GTI 1), is fed to the input of the imaging unit 4 and the input of the multiplier codes 7. In the imaging unit 4, the source code of the frequency w is multiplied by the number n, when this n is usually chosen as a multiple module

2 (item 2, 4. 8, ...). In the multiplier of codes 7, codes of numbers t, 2t, 3t, are formed, .., (n - 1) t, Codes of these numbers are formed on the basis of typical

hPi mn The multiplier 7 codes forms codes m. 2m, 3m, ..., (n - 1) mt, and in block 8 of summation, the code of the current phase A is added with the output codes of the multiplier 7 codes. The control unit 11 consists of n memory blocks, the outputs of which through the switch 13 are fed to the input of the DAC 15. Registers 10 and 12 serve to equalize the delays. Switch 1 3 is controlled by the output code of the distributor 9 pulses. The speed is determined by DAL 15, register 14 and switch 13. 1 sludge.

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multiply, or using additional adders. So codes 2m, 4m, 8m ,, .. are obtained by simply shifting the source code m by 1, 2, 3,.,. bit up, and the codes Ssh, 5t, 6t, .7t, ... receive. by summation (2b + t), (4t + t), (4t + 2t), (8t + t.), .. on several additional adders (not shown in the drawing).

The code of the most significant bits of the number Ш П from the first output of the formier 4 is fed to the information input of the first accumulator of phase 5, the code of the least significant bits. - to the information input of the second phase accumulator. The first and second drives 5 and 6 of the phase operate at a clock frequency that is n times smaller than the reference clock (fp f (), removed from divider 2 on p. The transfer signal from the output of the second accumulator of phase 6, tied to the clock frequency, is fed to the input. the transfer of the first drive 5 phase.

In this way, the accumulators 5 and 6 phases form a single accumulator with a digit N. The separation of the phase accumulator into two allows reducing the volume of each of them, i.e. provides the ability to work with a higher clock frequency. f.

Since the code of the number that determines the overflow frequency of the first accumulator of phase 5 is n times higher than the initial m and is mn, and the clock frequency of the accumulator operation is n times lower than the reference one and is equal to fr-r / n, the average overflow frequency of the first accumulator 5 phases

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---- --- Gt. paBiia at a given output frequency Since the accumulation code is n times higher than the original, the number of samples of the current phase A in the synthesized oscillation period is also n times smaller, which can lead to a significant deterioration of the output signal spectrum. The summation block 8 is used to form intermediate (n -1) samples of the current phase code A + sh, A - r2t,.,., A + (n - From the first cycle of operation of accumulators 5 and 6 of the phase, the current phase code 2A + t , ..., 2A + (p - Dm on the second cycle, etc. For this, in block 8 of summation, the code of the current phase A is output from the output of the first phase accumulator 5 with t, 2in, ..., (nl) ni formed in the multiplier 7 codes.

In the –block of the permanent 11 memory, the conversion is performed linearly, changing the pulse – phase of the phase code to the amplitude of the sinusoidal, oscillations sinA, sin (AH-in), sin (A + 2m),. .., (n-1) nij, sin2A, sin (2A -im), etc. To align and eliminate delays in the elements of the summation block 8 and the permanent memory block 11, memory registers 10 and 12 are used, clock inputs of which pulses are taken from the first and second outputs of the distributor 9 pulses. In the pulse distributor 9, a pulse sequence is generated from the output signals of the divider 2 using a coincidence circuit with a duty cycle n with a repetition rate of -1-gti / which is fed to an n-bit cd, a vigo register clocked at a repetition rate f Signals taken from each bit register, shifted relative to each other by the value of t 1 / f p- ,. The bit number of the shift register corresponding to the first and second outputs is determined by the delays in the corresponding elements of the frequency synthesizer. Switch 13 in series n times during the period of the clock frequency connects to

The codes of sinA, sin (A + m), sin (A + 2m),, .., (nr) m3, then sin2A SLn (2A + m), sin (2A + 2m), ..., sin .. :

2A + Sp-1) t for the second period of the clock frequency, etc. The first register 14 of the memory. Serves to align the delay „t f ,,“ / n output bus input

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switch 13. As the information on the inputs of the first register 14 of memory is changed n times in a period of 5 clocks f fgti / n, the synchronization frequency of register 14 of memory is equal to fp.

D / A converter 15 digital samples of the amplitude of a sinusoidal output oscillation 10 converts amplitude samples of a rinus. The filter 16 serves to filter the first harmonic of the output synthesized oscillation. .

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From the description of the operation of the synthesizer, it is clear that the fastest elements are the D / A converter 15, the first memory register 14 and the switch

The proposed frequency synthesizer allows expanding (increasing) the range of synthesized frequencies by n times while maintaining the frequency sampling step.

Claims (1)

Invention Formula thirty 35 40 A digital frequency synthesizer containing a serially connected clock pulse generator, the first memory register, a digital-to-analog converter and a low-pass filter, a frequency code generation unit, a first phase accumulator, a code multiplier, a summation unit, a fixed memory unit, the second memory register ty, about t t l. and in order to expand the range of synthesized frequencies, a frequency divider, a pulse distributor — a commutator, a third memory register, a second phase accumulator, and a control code driver, the first and second outputs of which are entered. connected to the information inputs of the first and second phase accumulators, respectively; the output of the clock pulse generator is connected to the clock inputs of the frequency divider and the pulse distributor, .by -... the course of the frequency divider is connected to the clock inputs of the first and wto th phase accumulators and the input of the frequency code forming unit whose output 5 is connected to an input of yn:. equal to the code and multiplier of codes, the output of the second phase accumulator is connected to the transfer input of the first phase accumulator, the output of the first accumulator five WITH the phases and outputs of the multiplier codes are connected to the corresponding inputs of the summation unit, the outputs of the summation unit are connected to the corresponding inputs of the second memory register, the outputs of which are connected to the corresponding inputs of the constant memory unit, the outputs of which are connected to the corresponding direct inputs of the third memory register , the clock inputs of the second and third memory registers are connected respectively to the first and second outputs of the pulse distributor, the output of which is connected, to the control input of the switch, the output of which horn connected to inlet; The first memory register, the bit output of the frequency divider is connected to the input of the pulse distributor, the outputs of the third memory register are connected to the corresponding inputs of the switch.