SU1578833A1 - Device for shaping signals modulated in amplitude and phase - Google Patents

Abstract

The invention relates to telecommunications technology. The purpose of the invention is to improve the noise immunity of the generated signals. The device contains a random number generator 1, a drive 2, a synchronization block 3, a shift register 4, an adder 5, a code converter 6, consisting of a square root extractor 7 and a digital divider 8, an information block 9, a multiplier 10, a master oscillator 11, a digital-analog converter 12, a balanced modulator 13, a driver of 14 radio pulses. The clock pulses of block 3 synchronize the entire operation of the device. In the code converter 6, a number is obtained corresponding to the square root of the normalized random number generated by generator 1. The signal at the output of the radio pulse generator 14 is the output signal. 1 hp f-ly, 1 ill.

Description

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The invention relates to a telecommunication cache and can be used in phase modulation signal transmission devices.

The purpose of the invention is to improve the noise immunity of the generated signals.

The drawing shows a structural electrical circuit of the proposed device.

The device for generating amplitude and phase modulated signals contains 1 random number generator 1, accumulator 2, synchronization unit 3, shift register 4, adder 5, code converter b, consisting of a square root extraction unit 7 and a digital divider 8, information unit 9 , multiplier 10, master oscillator 11, digital-to-analog converter (D / A converter) 12, balanced modulator I3, and driver 14 radio pulses.

The device works as follows.

Random number generator 1 is designed to output random numbers in the interval, lj, when clock pulses are received from the synchronization unit.

The drive 2 serves to accumulate n numbers from the generator 1, where n is the number of sub-elements of the generated signal, and output them in parallel code to the adder 5.

The synchronization unit 3 is provided for generating clock pulses ensuring synchronous operation of all units of the proposed device.

The shift register 4 provides for the storage and output to the digital divider of the code converter 6 numbers from the generator 1.

 Adder 5 is intended to sum the η numbers coming from accumulator 2.

Code converter 6 serves to convert numbers from the shift register 4, in accordance with a certain rule. The rule is to normalize the incoming number and extract the square root from it. The code converter 6 consists of a serially connected digital splitter 8 and a square root extraction unit 7.

The digital divider 8 provides the rationing of numbers from the shift register 4. He performs de

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The calculation of each of the n numbers for the sum of all the n numbers obtained by the adder 5.

The square root extraction unit 7 is designed to extract the square root from the number provided by the digital divider 8. (The information unit 9 provides for the issuance of an information sequence, which is to be transmitted over a communication channel.

The multiplier 10 serves to multiply the information sequence and the numbers coming from the code converter 6. The multiplication consists of inverting the sequence coming from block 7 when a pulse corresponding to logical zero arrives from information block 9 When a pulse of information logical block 9 arrives from the output of the multiplier 10 passes a sequence of numbers coming from block 7.

The purpose and principles of implementation of the DAC 12, the master oscillator 1 and the driver 14 radio pulses do not differ from the known device

The balance modulator 13 is designed to modulate the carrier oscillation of the oscillator 11 with a signal from the output of the DAC 12.

Upon receipt of the clock pulses from block 3, the random number generator 1 generates random numbers (from the interval /),), which arrive at the inputs of the accumulator 2 and the shift register 4. The drive 2 accumulates n numbers (n is the number of sub-elements of the generated signal and outputs them in parallel code to the input of the adder 5.

The numbers from generator 1 to shift register 4 are accumulated and output in serial code to the first input of the digital divider 8, the second input of which receives the sum of n numbers produced by generator 1. Digital divider 8 normalizes all n numbers, i.e. . each of the n numbers from the shift register 4 is divided by the sum of these n numbers. The resulting number in the serial code is fed to the input of block 7, which performs its conversion. At the output of block 7, an m-bit number is obtained corresponding to the square root of the normalization factor.

a random number generated by the generator 1.

The sequence of numbers from the output of block 7 is fed to the first input of multiplier 10, to the second input of which information sequence from information block 9 is fed. The duration of the element of the information sequence is equal to, where se is the duration of the element (one pulse) of the number Lormalized by generator 1, Multiplier 10 inverting the sequence from block 7 when a pulse corresponding to a logical zero arrives from information block 9.

The DAC 12 converts the generated digital sequence into an analog signal, the amplitude of which corresponds to the module of the number fed to the DAC 12, and the sign is determined by the sign of the incoming number.

The balance modulator 13 modulates the carrier oscillation of the master oscillator II according to the law of the signal coming from the D / A converter 12. This signal is fed to the Shaper 14 radio pulses, which filter out the unnecessary components of the spectrum. The signal at the output of the radio pulse shaper 14 is the output signal of the proposed device and is a signal with amplitude and Laze modulated subunits, the phase modulation being carried out by the information sequence, and the additional amplitude manipulation of the signal subelements along p- dimensional - tara. Thus, the phase of the output signal has two values (O /), and the amplitude has a countable number of values determined by the circuit design of the generator I.

Signals with subelements modulated in amplitude and phase can be received by correlation processing.

5788336

Claims (2)

1. An apparatus for generating amplitude and phase modulated signals, comprising an information unit, an adder, serially connected shift register and code converter, a digital-to-analog converter, a master oscillator, a radio pulse shaper and a synchronization unit, the first and second outputs of which are connected respectively to the clock inputs of the shift register Radio pulse puller, characterized in that, in order to improve the noise immunity of the generated signals, a multiplier is introduced, a ns modulator and serially connected gene-random numbers, to the synchronization input of which the first output of the synchronization unit is connected, and a storage device, a synchronization input and five 0 five 0 five 0 five 0 the outputs of which are connected respectively to the third output of the synchronization unit and the inputs of the adder, the output of which is connected to the second input of the code converter, the output of which is connected to the first input of the multiplier, the second input and output of which are connected respectively to the output of the information block, to the input of which the second output of the block is connected synchronization, and with the input of a digital-to-analog converter, the output of which is connected to the signal input of a balanced modulator, the control input and output of which are connected With the output of the master oscillator and with the signal input of the pulse generator, while the output of the random number generator is connected to the signal input of the shifter. 2. A device according to claim 1, wherein the code converter comprises serially connected digital divider, the inputs of which are the first and second inputs of the code converter, and the square root extractor unit, the output of which is the code converter output.