JP2956910B2 - Timing measurement device with calibration function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing measuring device for measuring an incoming timing of a signal under measurement.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional timing measuring device. In the figure, DL ₀ , DL ₁ , DL ₂ ... DL _n-1 indicate delay elements each having a different delay time by a predetermined time. One end of each of the delay elements DL _{0 to} DL _n−1 is commonly connected and connected to the input terminal 1, and the other end is connected to the input terminals D _{0 to} D _n−1 of the latch circuit 2. Latch circuit 2 is D
When the clock CP is input to the clock input terminal CK, the logic input to the input terminals D _{0 to} D _n−1 is read at the rising timing. The read logical data is output from the output terminals Q ₀ to
Output to Q _n-1 . 4 is a reset signal generator,
A signal RES for resetting the latch circuit 2 is generated at the falling edge of the output DM of the delay element DL _n-1 having the longest delay time.

The delay time τ of each of the delay elements DL _{0 to} DL _n-1
0 , τ ₁ , τ _2, ..., Τ _n−1 , when one cycle of the clock CP is t, τ ₀ = 0, τ ₁ = t / n, τ ₂ = 2t /
n, τ ₃ = 3t / n... τ _n-1 = (n-1) · t / n That is, each delay time of each of the delay elements DL _{0 to} DL _n−1 is t
/ n is different from each set, to divide the one cycle t of the clock CP, as shown in FIG. 4 equally at t / n.

[0004] The output terminal Q ₀ ~Q _n-1 of the latch circuit 2 is connected to the input terminal _{I 0, I 1, I 2} ... I n-1 of the encoder 3. At the supply timing of the clock CP, the encoder 3 counts the number of output terminals of the latch circuit that has read the logic of the signal under test X output from the latch circuit 2,
The timing at which the signal under test X is input is calculated from the supply timing of the clock CP based on the number of latch outputs from which the logic of the signal under test X has been read.

That is, as shown in FIG.
In the measured signal X is input, then, at the timing when the clock CP is input, the five output terminals Q ₀ to Q ₄ of the latch circuit 2 and outputs a logic H, the rise of the signal to be measured X timing T _x it can be seen that input to the input terminal 1 before 5 × t / n times from the rising of the clock CP. After all, the signal under measurement X from the latch circuit 2
By counting the number of output terminals Q _{0 to} Q _n−1 that output the logic of the above, the time from the timing when the clock CP is input to the rising timing Tx of the signal under test X is represented by t /.
It can be measured with a resolution of n.

[0006]

In the timing measuring apparatus described above, the measuring accuracy is determined by each of the delay elements DL _{0 to} DL _n−.
1 delay time τ ₀ , τ ₁ , τ ₂ ... Τ _n-1 . Therefore, the delay time of each of the delay elements DL _{0 to} DL _n−1 is always t / n
Must have a time difference. The delay time of the delay element fluctuates due to aging or temperature change. For this reason, generally, in this type of device, the delay elements DL _{0 to} DL ₀
The delay time of _n-1 must be calibrated.

Conventional inputs a pulse to the input terminal 1, the pulse signal is observed with an oscilloscope at a point passing through the respective delay elements DL ₀ through DL _n-1, the time interval of pulses each delay is a predetermined t / n, the delay elements DL _{0 to} DL
Adjust _n-1 . However, this adjustment has the disadvantage that it takes time and effort. SUMMARY OF THE INVENTION An object of the present invention is to provide a timing measuring apparatus of this kind, which can easily adjust the delay time of a delay element.

[0008]

According to the present invention, a signal to be measured is supplied to a plurality of delay elements having different delay times by a predetermined time, and a plurality of latches are synchronized with a delay output of each delay element in synchronization with a clock. In a timing measurement device that measures the rising timing of a signal under test with a resolution finer than the clock cycle by the number of latch circuits that read the logic of the signal under test into the circuit, a cascade consisting of each delay element and each latch circuit is used. A selection switch for selecting and taking out one circuit at a time, a cascaded circuit selected by the selection switch and a variable delay element for calibration constituting a closed loop, and a variable delay element for calibration connected independently to a closed loop for calibration. A changeover switch that oscillates at a cycle determined by the delay time of the variable delay element, and the calibration variable delay element connected to a closed loop by itself Timing with a calibration function by adding a period measuring device that measures the period of the oscillating signal to be oscillated and the period of the closed-loop oscillating signal composed by cascading the cascaded circuit selected by the selection switch and the variable delay element for calibration This constitutes a measuring device.

According to the configuration of the present invention, the latch circuit that repeats the latch operation by a clock having a constant cycle, and the oscillation cycle determined by the delay time of the calibration variable delay element and the delay time of each delay element are determined by the oscillation cycle and the clock. Suddenly changes at the point where the periods coincide with each other, and in the state of non-coincidence, the oscillation period maintains a constant value. Therefore, the delay time can be accurately set by using the point at which the oscillation cycle changes abruptly.

[0010]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals. According to the present invention, the delay elements DL _{0 to} DL _n-1 having different delay times at predetermined time intervals, and the delay elements DL
_{In a} timing measuring device including an encoder 3 and a latch circuit 2 in which input signals delayed by _{0 to} DL _n-1 are supplied to input terminals D _{0 to} D _n-1 ,
It is characterized in that a calibration device 10 for calibrating the delay times of the delay elements DL _{0 to} DL _n−1 is provided.

The calibration device 10 has changeover switches SW1, SW
3, a SW4, a selection switch SW2, a waveform shaping circuit 11 for outputting a pulse having a constant pulse width by a monostable multivibrator, a calibration variable delay element 12, and a period measuring device 13. Changeover switch SW1, SW
3, SW4 and the delay element DL ₀ through DL beat to the contact a side
A cascade circuit of any _one of _n-1 and the latch circuit 2 and a cascade circuit of the calibration variable delay element 12 and the waveform shaping circuit 11 are switched to a state in which a closed loop is formed. This loop is hereinafter referred to as a large loop.

Connect the changeover switches SW1, SW3, SW4
When tilted to the point b, the variable delay element 12 for calibration and the waveform shaping circuit
11 form a closed loop. This le
In the following, the loop will be referred to as a small loop. Selection switch
Switch SW2 is in a closed loop when a large loop is formed.
Delay element DL ₀~ DL_n-1Choose which to insert
Switch.

When operating as a timing measuring device
Switches the changeover switch SW1 to the contact a, and sets the changeover switch
SW3 and SW4 may be moved to the contact b side. This switching state
Now the calibration device 10 is disconnected from the timing measurement device
You. Therefore, in this state, the signal under measurement is input to the input terminal 1.
If you press it, it will be given immediately after that input timing.
The time until the clock is set to the delay element DL₀~ DL _n-1
Can be measured with a resolution of each time difference t / n.

The operation in the calibration mode will now be described. First, defeat the selection switch SW2 to the contact S _0, while selecting the delay element DL ₀ of the delay time is the smallest tau _a1, all changeover switches SW1 and SW3, SW4 contact a
When turned to the side, a large loop is formed. At this time, when the delay time of the calibration variable delay element 12 is gradually increased from 0, the oscillation cycle of the large loop changes stepwise as shown in FIG. One step of the stairs corresponds to one cycle t of the clock CP, and the delay time of the calibration variable delay element 12 is 0 to
While changing from τ ₁ , τ ₁ to τ ₂ , τ ₂ to τ ₃ , the oscillation cycle is maintained at T1, T2, T3. That is, this phenomenon is a phenomenon caused by the latch operation of the latch circuit 2, and it can be seen that the periods T1, T2, T3,... Have an integer multiple of the period of the clock CP. Since it changes sharply from step to step, the intermediate values are T _c1 , T _c2 , T _c3 ...
Delay time tau ₁ defining a, τ _2, τ ₃ ... it can be set reproducibly, i.e. accurately.

The calibration of each of the delay elements DL _{0 to} DL _n-1 is performed as follows. Sets the selection switch SW2 to the contact S _0, it switches the changeover switch SW1, SW3, SW4 to the contact a in a state that selects the delay element DL ₀ (fixed delay time 0). In this state, the delay time of the calibration variable delay element 12 is adjusted, and the oscillation cycle of the large loop is set to T _c1 . Next, the changeover switches SW3 and SW4 are switched to the contact b to form a small loop constituted by the cascade circuit of the waveform shaping circuit 11 and the calibration variable delay element 12. The oscillation cycle of the small loop is measured by the cycle measuring device 13 without changing the delay time of the calibration variable delay element 12, and the measured cycle is taken in as the reference cycle T _Ref .

While the oscillation state of the small loop is maintained, the oscillation cycle is t / n
The delay time of the calibration variable delay element 12 is adjusted so that the delay time becomes smaller. Since the small loop does not include the latch circuit 2, the oscillation cycle of the loop changes linearly with the change in the delay time of the calibration variable delay element 12. t is the clock CP
And n is the number of delay elements DL _{1 to} DL _n−1 , so that t / n is given as a known value.

Next, the changeover switches SW3 and SW4 are set to the contact b.
The return, switches the selection switch SW2 to the contact S _1, switches the state of the large loops. The delay element DL ₁ in the closed loop in this state is inserted, the delay time of the calibration variable delay element 12 because changed to a smaller value just ahead t / n, the delay time of the delay element DL ₁ is DL ₀ T / more accurately than the delay time
If the calibration is performed for a long time by n, the oscillation period of the large loop should match T _c1 .

[0018] When the oscillation period does not match the T _c1, since it means that the value of the delay element DL ₁ is shifted from the normal value, to adjust the value of the delay element DL _1, large loops The oscillation cycle is matched with T _c1 . When match the oscillation period T _c1, the calibration of the delay element DL ₁ is completed. Next, the changeover switches SW3 and SW4 are switched to the contact b to switch to the small loop. The delay time of the calibration variable delay element 12 is adjusted so that the oscillation cycle of the small loop is further reduced by t / n, and the switching state of the large loop is returned again. At this time the selection switch SW2 is switched to the contact S _2, now connects the delay element DL ₂ in the large loop.

[0019] In this case the delay element DL ₂ is higher than DL ₁ t /
If the delay time is calibrated to be long by n, the oscillation cycle of the large loop should match T _c1 . If the T _c1 does not match to adjust the delay time of the delay element DL ₂ such that the oscillation period of the large loop matches the T _c1. While correcting the delay time following Similarly calibration variable delay element 12 to a small value by t / n, to calibrate the delay time of each delay element DL ₃ ~DL _n-1.

A register for storing digital data as each of the delay elements DL _{0 to} DL _n-1 and the variable delay element for calibration, and a digital value stored in this register is used as a DA.
Each of the delay elements DL is constituted by a D / A converter for conversion and a variable delay element having a delay time defined by an analog voltage obtained by the D / A conversion by the D / A converter.
It is possible to electrically control the change of the delay time of _{0 to} DL _n−1 and the variable delay element 12 for calibration. Therefore, for example, by using a microcomputer as a controller, a timing measuring apparatus with a calibration function that automatically performs a calibration operation can be configured.

[0021]

As described above, according to the present invention, the changeover switches SW1, SW3, SW4 and the selection switch S
W2 and waveform shaping circuit 11, calibration variable delay element 12
A timing measuring device having a calibration function can be provided only by adding the calibration device 10 comprising.

In addition, the calibration can be performed with the accuracy of the cycle t of the clock CP using the cycle t of the clock CP as a reference for the calibration. Therefore, accurate calibration can be performed.

[Brief description of the drawings]

FIG. 1 is a connection diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a connection diagram for explaining a conventional technique.

FIG. 4 is a waveform chart for explaining the operation of the conventional technique.

[Explanation of symbols]

1 input terminal 2 latch circuit 3 encoder 10 calibration device 11 the waveform shaping circuit 12 for calibration variable delay element 13 period measuring device DL ₀ through DL _n-1 delay elements SW1, SW3, SW4 switching switch SW2 selectively switches

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 H03K 5/13 G01R 13/00-13/42

Claims (1)

(57) [Claims] 1. A signal to be measured is supplied to a plurality of delay elements having different delay times by a predetermined time, and a delay output of each of the delay elements is read into a plurality of latch circuits in synchronization with a clock, and a delay time of the signal to be measured is measured. In a timing measuring device for measuring the rising timing of a signal under measurement with a resolution finer than the clock cycle based on the number of latch circuits from which logic has been read, one cascaded circuit composed of each of the delay elements and each latch circuit is selected. Selection switch, a calibration variable delay element that forms a closed loop with the cascade circuit selected by the selection switch, and the calibration variable delay element that is independently connected to the closed loop, and the delay time of the calibration variable delay element. A switch that oscillates at the cycle determined by, and an oscillation signal that oscillates with the calibration variable delay element connected to a closed loop by itself And a period measuring device for measuring the period of the cascaded circuit selected by the selection switch and the period of the closed-loop oscillation signal formed by cascading the variable delay element for calibration. apparatus.