RU2303803C2 - Time-code transformer - Google Patents

Abstract

FIELD: measuring equipment engineering, namely, equipment for digital measurement of time intervals.

SUBSTANCE: device contains a digital delay line, synchronized with supporting generator. In accordance to invention, controllable delay element, phase interpolation block, second registers block, first and second encoders, impulse counter and subtraction block are introduced to device. Inputs of subtraction block, creating the result of transformation, are connected to appropriate outputs of impulse counter and both encoders, inputs of which are connected to appropriate outputs of first and second register blocks. Appropriate information inputs of both register blocks are combined, while divided clock inputs of registers of both register blocks are connected to appropriate outputs of phase interpolation block. First input of phase interpolation block together with the input of controlled delay element and controlling input of impulse counter through a buffer element is connected to input clamp of device, and its second input - to the output of controlled delay element. Controlling input of controlled delay element is combined with controlling input output digital delay line, which is connected by its main output to counting input of impulse counter.

EFFECT: simplification of device while maintaining high precision of measurements.

3 cl, 6 dwg

Description

FIELD OF THE INVENTION

The present invention relates to techniques for the precision measurement of time intervals.

State of the art

To measure time intervals, time-code converters are widely used, the action of which is based on counting the number of pulses of the reference period that fit into the measured time interval. To improve the accuracy of the conversion by reducing the time quantization step, various methods of interpolation of the reference period are used.

Known digital time interval meter [1], which contains a reference pulse generator, the output of which is connected through the first element And to the input of the pulse counter, while the remaining input of the first element And is connected to the output of the trigger, the inputs of which serve as inputs of the start and stop signals of the device. In addition, there is a series circuit of a plurality of delay elements connected to the output of the reference generator, the output of each of which is connected to the reset input of the corresponding additional trigger, the number of which is equal to the number of delay elements. The outputs of all additional triggers are connected to the inputs of the encoder. The measurement process begins after resetting the pulse counter and triggers by a start pulse, and ends with a stop pulse. The leading bits of the measurement result are generated at the outputs of the pulse counter and display an integer number of reference periods that fit into the measured interval, and the least significant bits of the result are generated at the encoder outputs and display the fractional part of the reference period - the remainder of dividing the interval by the reference period in units of the delay time of the delay element. The disadvantage of this analogue is the low accuracy of the measurement, the error of which cannot be less than the delay time of one delay element.

Analogs of the present invention are also schemes of digital time-code converters in which a nonius method for evaluating the fractional part of a time interval measured by a reference generator is used, for example, the circuit described in [2]. This device includes a primary and secondary pulse generators, the periods of which differ by a small amount, which is the value of the resolution in time. The known device also includes two triggers and two And elements that control the vernier sweep process, as well as two pulse counters that display the measurement result. With high accuracy of measurement of this device, it has low productivity, since the vernier sweep process takes many reference periods, the greater, the higher the measurement accuracy.

Another analogue of the present invention is a time interpolator [3] containing a pulse counter and a partitioned delay line, the inputs of which are connected to a common terminal of the reference signals. The device includes a register in the form of a plurality of triggers with common information and fault inputs, the trigger synchronizing inputs being connected to the corresponding intermediate taps of the delay line. In addition, the scheme includes read-only memory (ROM), which serves as a converter of the thermometric code of the register into binary code. The total delay time of the partitioned delay line is one reference period. The device is started by a start pulse synchronized with the reference signal, which allows the pulse counter to work. At the same time, reference signals propagate along the delay line. At the moment of arrival of the stop pulse, the pulse counter records the number of complete reference periods that fit into the measured interval, and the register indicates the number of taps of the partitioned delay line to which the reference signal has propagated. As a result, the counter reflects the high bits of the measurement result, and the ROM reflects the low bits. The measurement error is determined in analogue by the delay time of one section of the delay line, which is significantly less than the reference period. At the same time, such a resolution of the time-code converter in many applications is insufficient, in addition, there is an additional source of conversion error due to the possible uneven delay of individual sections of the delay line.

A device is also known for measuring the time interval [4] with a reference generator in the form of a multiphase pulse generator (MGI), the set of outputs of which forms a subscale of the time reference. The MGI outputs are connected to the corresponding information inputs of two registers, the clock inputs of which are connected to the input terminals of the signals for the beginning and end of the time interval, and the outputs are connected through the corresponding encoders to the lower inputs of the corresponding operands of the subtraction unit. In this case, the senior inputs of the first operand of the subtraction unit are connected via the third register to the outputs of the pulse counter, which determines the integer number of reference periods in the measured time interval. There is also a fourth register for recording the measurement result at the end of the time interval. In this analogue, there is no need to synchronize the origin of the interval with the reference pulse, and the unevenness of the time slices at the MGI outputs can be obtained arbitrarily small. This provides improved measurement accuracy of the time interval. However, the measurement accuracy is still limited by the value of the named MGI time quantum.

Of the known analogues, the closest in technical essence to the present invention is a time interpolator [5]. This device contains an MHI made in the form of a main delay line on serially connected controlled delay elements; the input of the main delay line is connected to the output of the reference generator. Each delay element is equipped with a control input for electronic control of the delay time, these inputs of the delay elements are combined and are used as a single control input of the main delay line. This control input is used to automatically adjust the total delay time of the delay line, which is carried out using the phase comparison unit installed in the feedback circuit of the delay line. The phase comparison unit, by adjusting the total delay time of the delay line, maintains it exactly equal to the reference period. The device also has many registers, the same information inputs of which are combined and connected to the corresponding outputs of the MGI - intermediate taps of the main delay line. The device also contains an additional precision delay line with a distributed RC structure, to the set of intermediate taps of which the clock inputs of the corresponding registers are connected. The total delay time of the additional delay line is equal to the delay time of one link in the main delay line. The device provides means for automatically calibrating the delay time of each link of the additional delay line.

A pulse, the moment of receipt of which is converted by the device into a digital code, arrives at the input of an additional delay line and then appears on its intermediate taps, sequentially delayed by each link. The pulse delay time in each section is determined by the expression

where T _o is the reference period, N and M are the number of links of the main and additional delay lines, respectively.

The pulses from the taps of the additional delay line are fed to the clock inputs of the corresponding M registers, which record the states of all the MGI outputs at the moments separated by the Δt quantum. As a result, on a complete set of outputs of all N-bit registers, a digital thermometric code of N × M capacity is formed, which can then be converted into a regular binary code by known means.

The prototype device is characterized by high time resolution, since the time quantum Δt is N times less than the delay time of one link of the main delay line. For example, if the delay element of the main delay line is a coupled CMOS type inverter, then the prototype achieves a resolution of 48.8 picoseconds, which is much less than the propagation delay time of two inverters.

The prototype device has disadvantages. Firstly, its basis, which provides precision conversion of time into code, is an additional delay line with a distributed integrated RC structure that is difficult to manufacture. Such a delay line requires individual adjustment of the links during the manufacturing process and calibration of their delay time during operation. Secondly, the prototype device does not provide technical means for converting the time interval into the code as the difference between the recession moments and the front of the input pulse.

SUMMARY OF THE INVENTION

The aim of the present invention is to simplify the time-code converter and expand its functionality. This goal is achieved by replacing an RC type passive delay line with an active phase interpolator that does not require adjustments and introducing blocks that capture the decay and front edges of the input signal in the form of digital codes and calculate their difference.

The time-code converter contains a buffer element connected to the input terminal, a digital delay line, covered by feedback through a phase comparison unit with a reference oscillator that starts the digital delay line, as well as a first register block, the register information inputs of which are connected to the corresponding outputs of the digital delay line, and each register in the first block of registers has its own clock input. To achieve this goal, a controlled delay element, a phase interpolation unit, a second block of registers, first and second encoders, a pulse counter and a subtraction unit are additionally introduced into the device. The outputs of the subtraction unit are the outputs of the time-code converter, and its corresponding inputs are connected to the outputs of the pulse counter, the second and first encoders. The inputs of the first and second encoders are connected to the corresponding outputs of the first and second block of registers, respectively, the information inputs of the second block of registers are combined with the corresponding information inputs of the first block of registers, the clock inputs of all the registers in both blocks of the registers are connected to the corresponding outputs of the phase interpolation block. The first input of the phase interpolation unit together with the control input of the pulse counter and the input of the controlled delay element is connected to the output of the buffer element, and its second input is connected to the output of the controlled delay element. The control input of the controlled delay element is combined with the control input of the digital delay line, the main output connected to the counting input of the pulse counter.

The digital delay line can be made in the form of a series circuit of controlled delay elements, the combined control inputs of which serve as the control input of the digital delay line, and their outputs - the outputs of the digital delay line.

In a preferred embodiment, the phase interpolation unit contains sequentially connected interpolation stages, each i-th interpolation stage has (2 ^i-1 + 1) inputs and (2 ⁱ + 1) outputs, the outputs of the terminal interpolation stage serve as outputs of the phase interpolation unit. Each interpolation stage includes (2 ^i-1 + 1) interpolation elements having the first and second paraphase inputs and a paraphase output, the first and second inputs of the interpolation elements with odd serial numbers are combined and serve as inputs of the interpolation cascade. The first and second inputs of interpolation elements with even serial numbers are connected to the combined inputs of the corresponding interpolation elements with odd serial numbers differing from the serial number of this interpolation element by ± 1, the outputs of all interpolation elements make up the set of outputs of the interpolation cascade.

Each of the phase interpolation elements, interconnected in the phase interpolation unit as described above, is a unit for the weighted summation of two input signals and in the bipolar version can be made in the form of a double balanced mixer on three differential transistor stages. In a double balanced mixer circuit, the first and second differential transistor stages have common collector resistors in the right and left shoulders, respectively, and the bias current sources are the collector circuits of the corresponding transistors of the third differential transistor stage, which have a common bias current source in the emitter circuit. The differential inputs of the first and second differential transistor stages serve as the first and second paraphase inputs of the phase interpolation element. To ensure the load capacity and matching of the input / output circuits of the phase interpolation elements, the combined collectors of the first and second differential transistor stages are connected to the paraphase outputs of the phase interpolation element through emitter repeaters.

The principle of the proposed device is based on the gating of the states of the digital delay line at the moments of the beginning and end of the converted time interval by pulses shifted relative to each other by a time Δt during a time equal to the propagation delay time of one link of the digital delay line. The indicated states corresponding to the digital counting of the edge and fall of the time interval are remembered by the first and second blocks of registers, whose registers are clocked by pulses displaced by Δt. The number of full periods of the reference oscillator that fit in the interval is fixed by a pulse counter. A code reflecting the duration of the interval is formed as the difference of the samples after converting the thermometric codes of the register blocks into binary codes in accordance with the expression:

where d _MF - binary state of the pulse counter, d _WG1, d _WG2 - the converted first and second encoders state of the first and second register units, respectively.

Thus, in the proposed time-code converter, the same resolution is achieved as in the prototype, but with significantly simpler means. Clock pulses displaced by Δt are generated by the active phase interpolation unit, which does not require adjustment and regulation. The principle of operation of the phase interpolation unit is discussed below in the description of a preferred embodiment of the invention.

List of drawings

Figure 1 presents a functional electrical diagram of a time-code converter in accordance with the present invention.

Figure 2 shows a schematic diagram of an embodiment of a section of a digital delay line included in a time-code converter.

Figure 3 shows a variant of the circuit diagram of the bipolar phase interpolation element used in the phase interpolation unit.

Figure 4 shows a timing diagram of the signals explaining the principle of operation of the phase interpolation element.

Figure 5 presents the functional diagram of the phase interpolation unit, performed on the elements of phase interpolation.

Figure 6 shows the timing diagrams of the signals in the characteristic nodes of the Converter time-code, explaining the principle of its operation.

Information confirming the possibility of carrying out the invention

The time-code converter circuit shown in FIG. 1 contains an input buffer element 1 connecting the input terminal 2 to the control input of the pulse counter 3, the input of the controlled delay element 4 and the first input of the phase interpolation unit 5, the second input of which is connected to the output of the controlled delay element 4 . The counting input of the pulse counter 3 is connected to the main output of the digital delay line 6, which has many intermediate outputs, a signal input and a control input. The signal input of the digital delay line 6 is connected to the output of the reference oscillator 7 and one input of the phase comparison unit 8, in which the other input is connected to the main output of the digital delay line 7, and the output to its control input. The intermediate and main outputs of the digital delay line 6 are connected to the corresponding information inputs of the first 9 and second 10 blocks of registers, and the clock inputs of the registers of the first block of 9 registers are connected to the corresponding direct outputs of the block 5 of phase interpolation, and the clock inputs of the registers of the second block of 10 registers are connected to the corresponding inverse outputs of block 5 phase interpolation. The outputs of the first block 9 of the registers, which are an ordered collection of all the outputs of all its registers, are connected to the corresponding inputs of the first encoder 11, and the outputs of the second block 10 of the registers are connected to the inputs of the second encoder 12. The outputs of the counter 3 pulses and the second encoder 12 are connected to the corresponding the inputs of the reduced unit of subtraction 13, the inputs of which are subtracted are connected to the corresponding outputs of the second encoder 12. The inputs of the upper digits of the subtracted are connected to the bus "0", because the capacity is smart In general, less than the bit is subtracted. Block 13 subtraction at its outputs 14 forms the result of converting the time interval into a digital code.

Digital delay line 6 in a preferred embodiment is a series circuit of controlled electronic delay elements 15, the combined control inputs of which serve as the control input of the digital delay line, and their outputs are the outputs of the digital delay line 6. The delay element can be any non-inverting logic element that allows electronic control of the propagation delay time. In the bipolar version, it can be a buffer element of emitter-coupled logic with an adjustable bias current, the circuit of which is shown in Fig.2. The circuit consists of a differential current switch on transistors 16, 17 with separate collector resistors 18, 19 with a common emitter current source on transistor 20 and resistor 21. Diodes 22, 23 shunt the collector loads of transistors 16 and 17 to limit the magnitude of the output voltage. The emitter followers on transistors 24, 25 with the corresponding load resistors 26, 27 serve to match the levels of input / output signals. Parasitic capacitance of the circuit may serve as a timing capacitor 28. The differential paraphase input of the delay element 15 is the base 29 of the transistors 16 and 17, and the differential paraphase output is the output 30 of the emitter followers 24 and 25. The base 31 of the transistor 20 in the bias current source serves as the control input of the delay element 15. A change in the voltage at the control input 31 leads to a change in the bias current of the cascade and, consequently, to a change in the charge rate of the capacitor 28. This means a change in the propagation delay time, which is usually measured at half the output voltage swing.

с помощью эмиттерных повторителей на транзисторах 41 и 42, служащих также для согласования уровней входных и выходных сигналов элементов фазовой интерполяции. Конденсатором 43, определяющим задержку распространения элемента фазовой интерполяции, может быть паразитная емкость схемы, приведенная к точкам подключения. На фиг.3 приведено также используемое ниже упрощенное графическое обозначение элемента фазовой интерполяции.The phase interpolation unit 5 is based on phase interpolation elements, each of which in a bipolar embodiment can be constructed as a double balanced mixer, a simplified diagram of which is shown in FIG. 3. The circuit performs a weighted summation of the input signals. The circuit includes three differential transistor stages on transistors 32 and 33, 34 and 35, 36 and 37, respectively, two of which are switched by input paraphase signals A and B, and the third distributes the current of the common source 38 between the two first stages in accordance with the control voltage U. A pair of differential stages on transistors 32 and 33, 34 and 35 have a common collector load in the form of resistors 39 and 40, the voltages from which are output to the paraphase output D,

using emitter followers on transistors 41 and 42, which also serve to match the levels of input and output signals of phase interpolation elements. The capacitor 43, which determines the propagation delay of the phase interpolation element, can be stray capacitance of the circuit, reduced to the connection points. Figure 3 also shows the simplified graphic designation of the phase interpolation element used below.

Figure 4 illustrates the principle of operation of the phase interpolation element, diagram

Where

a R is the resistance of the equalizing resistor in the emitter circuit of the control differential stage. If the arrival times t _A and t _{B of the} edges (or slopes) of the signals differ by t _B -t _A , then in the process of two-stage recharging of the capacitance, first with current I _A , and then with full current I _{0, the} delay of the output signal D relative to input signal A, calculated by the level of half the difference, will be

- время задержки при совпадающих фронтах сигналов А и В. При изменении управляющего напряжения U в пределах от -RI₀ до +RI₀ значение k(U) изменяется от 1 до 0. Коэффициент k(U), следовательно, определяет влияние входа В на задержку распространения сигнала от входа А до выхода D. В описываемом устройстве элемент фазовой интерполяции используется в режиме U=0, при этом k(U)=1/2 и фронт выходного сигнала D располагается по центру между фронтами задержанных на

входных сигналов А и В.Where

- the delay time at the matching edges of the signals A and B. When the control voltage U varies from -RI ₀ to + RI _{0, the} value of k (U) changes from 1 to 0. The coefficient k (U), therefore, determines the effect of input B on the propagation delay of the signal from input A to output D. In the described device, the phase interpolation element is used in the mode U = 0, with k (U) = 1/2 and the front of the output signal D is located in the center between the edges of the delayed

input signals A and B.

где t_B, t_A - моменты поступления сигналов на входы В и А соответственно. Поскольку входы элементов 42, 44 46, 48, 50, 51, 53, 55, 57 и 59 объединены t_B=t_A, то они выполняют функции простых элементов задержки на время

. Остальные элементы фазовой интерполяции в схеме выполняют основную функцию фазовой интерполяции. Выход элемента 59 фазовой интерполяции не используется, данный элемент служит для выравнивания нагрузок элементов в блоке. С каждым каскадом фазовой интерполяции квант времени уменьшается в два раза, если входные сигналы блока 5 фазовой интерполяции разделены интервалом времени

, то в трехкаскадном примере осуществления этого блока парафазные сигналы на смежных выходах оказываются разделенными интервалами Δt=

/8.The phase interpolation unit 5 comprises series-connected interpolation stages. In the example diagram of this block shown in FIG. 5, the first interpolation stage, consisting of phase interpolation elements 43, 44, 45, has two inputs and three outputs, the second interpolation stage includes elements 46 ... 50 and has three inputs connected to three outputs of the first cascade, and five outputs. The third cascade of phase interpolation consists of elements 51 ... 59 of phase interpolation and has five inputs and nine outputs. The paraphase output signal of each of the phase interpolation elements 43 ... 59 is located in the center between the delayed input signals of these elements, that is, the propagation delay of the output signal relative to the signal at the first input is

where t _B , t _A are the moments of arrival of signals at inputs B and A, respectively. Since the inputs of the elements 42, 44 46, 48, 50, 51, 53, 55, 57 and 59 are combined t _B = t _A , they serve as simple time delay elements

. The remaining elements of phase interpolation in the circuit perform the main function of phase interpolation. The output of the phase interpolation element 59 is not used, this element serves to balance the loads of the elements in the block. With each cascade of phase interpolation, the time quantum is halved if the input signals of the phase interpolation unit 5 are separated by a time interval

, then in a three-stage example of the implementation of this block, the paraphase signals at adjacent outputs turn out to be separated by intervals Δt =

/8.

, где N - число секций цифровой линии 6 задержки.The operating order of the device (figure 1) is illustrated by the timing diagrams shown in Fig.6. Until the signal 60 is converted, the reference oscillator 7 continuously supplies the digital delay line 6 with reference pulses, which, as they propagate, appear on its intermediate taps (61, 62, 63, ...) until they reach the main output 64. The pulses 64 of the main digital output the delay lines 6 are compared in phase with its input pulses from the output of the reference oscillator 7 in the phase comparison unit 8, the output voltage of which adjusts the propagation delay time of each controlled delay included in digital line 6 ementa 15 delays so that the delay time of all digital delay line 6 is constantly equal to the period T _of the reference pulse generator 7. Since the controlled delay element 4 is identical to the controllable delay element 15 composed of a digital delay line 6, their propagation delay times are the same and equal to

where N is the number of sections of the digital delay line 6.

(М - число парафазных выходов блока 5 фазовой интерполяции, в данном примере равное 8), тактируются соответствующие регистры в первом блоке 9 регистров и в них записываются состояния выходов цифровой линии 6 задержки. Таким образом производится отсчет состояний выходов цифровой линии 6 задержки, соответствующих началу преобразуемого интервала времени Т_x. Также с момента поступления входного сигнала разрешается работа счетчика 3 импульсов, который в течение интервала T_x заполняется импульсами с основного выхода 64 цифровой линии 6 задержки.When the front of the input signal 60 arrives at the input terminal 2, the phase interpolation unit 5 starts generating clock pulses 65 ... 69 (in this example, eight paraphase signals), which appear sequentially at the outputs of the phase interpolation unit 5 in increasing order of their numbers. On the fronts of these pulses, delayed relative to each other by

(M is the number of paraphase outputs of the phase interpolation unit 5, in this example equal to 8), the corresponding registers in the first block 9 of the registers are clocked and the states of the outputs of the digital delay line 6 are written in them. Thus, the counts of the outputs of the digital delay line 6 corresponding to the beginning of the converted time interval T _{x are made} . Also, from the moment the input signal arrives, the operation of the pulse counter 3 is allowed, which during the interval T _{x is} filled with pulses from the main output 64 of the digital delay line 6.

At the end of the interval T _x begins the process of counting the states of the outputs of the digital delay line 6. In this case, on the inverse outputs of the phase interpolation unit 5, in the order of increasing their numbers with a successively increasing delay by Δt, pulse fronts appear, which clock the corresponding registers in the second block of 10 registers. As a result, in the second block 10 of the registers, the samples of the outputs of the outputs of the digital delay line 6 corresponding to the end of the converted time interval T _x are recorded.

The codes recorded in blocks 9 and 10 of the registers are in the order: register 1 - output 1, register 2 - output 1, register 3 - output 1, ..., register 1 - output 2, register 2 - output 2, ... register ( M-1) - output N, register M - output N are thermometric N × M - bit codes of the form 000 ... 111 or 111 ... 000. These codes are converted into direct binary codes of log ₂ (N × M) resolution with the corresponding first 11 and second 12 encoders. The accumulated over time T _{x the} contents of the S _sc counter of 3 pulses and the binary number S _{w2 of the} output of the second encoder 12 are respectively the highest and lower bits of the full countdown of the state of the digital delay line 6 at the end of the time interval T _x : S ₂ = S _sc S _w2 . A similar sample S _{W1 of the} state of the digital delay line 6, corresponding to the beginning of the time interval T _x , is formed at the output of the first encoder 11.

The number of S ₂ = S _MF and S _w2 number S ₁ = 0S _w1 with ascribed to zero MSBs fed to corresponding inputs of the combination unit 13, subtraction, which forms at its outputs the result of converting the time interval T _x as the difference between two samples:

- коэффициент пропорциональности (ед/сек). Результат преобразования получается в единицах Δt.Where

- proportionality coefficient (units / sec). The conversion result is obtained in units of Δt.

To avoid the need for additional transformations, the product N × M should be chosen equal to an integer power of two. Before the next conversion cycle, the counter 3 pulses must be reset (reset circuit in figure 1 is not shown).

Thus, the proposed device performs the conversion of time-code with a subventive resolution in time, but has a simplified implementation compared to the prototype.

Literature

1. Shlyandin V.M. Digital measuring devices: Textbook for high schools. - M.: Higher School, 1981, p. 166, Fig. 3.27.

2. Ibid., P.163, fig. 3.25.

3. US patent 4439046, IPC G048 / 00, 03/27/1984

4. Device for measuring the time interval. Application for invention No. 2004108575/28 (009039), IPC G04F 10/04, decision on the grant of a patent dated March 22, 2005

5. Mota M., Christiansen J. A High-Resolution Time Interpolator Based on a Delay Locked Loop and an RC Delay Line. - IEEE Jornal of Solid-State Circuits, Vol.34, No. 10, October 1999, pp.1360-1366 (Fig.2, p.1361) - prototype.

Claims (3)

1. The time-code converter containing a buffer element connected to the input terminal, a digital delay line, which has many outputs, a signal input and a control input connected to the reference generator connected to the output of the phase comparison unit, a pair of inputs of which are connected to the input and the main output digital delay line, as well as the first block of registers, the information inputs of the registers of which are connected to the corresponding outputs of the digital delay line, and each register in the first block of registers has its own A specific clock input, characterized in that a controlled delay element, a phase interpolation unit, a second block of registers, a first and second encoders, a pulse counter and a subtraction unit, the outputs of which are the outputs of the time-code converter, are introduced into it, and the corresponding inputs are connected to the outputs of the counter pulses of the second and first encoders, while the inputs of the first and second encoders are connected to the corresponding outputs of the first and second block of registers, respectively, the information inputs of the second block of registers are are integrated with the corresponding information inputs of the first block of registers, the clock inputs of all registers in both blocks of registers are connected to the corresponding outputs of the phase interpolation block, the first input of which, together with the control input of the pulse counter and the input of the controlled delay element, is connected to the output of the buffer element, and the second input to the output of the controlled delay element, the control input of the controlled delay element is combined with the control input of the digital delay line, the main output is connected oh to the counting input of the pulse counter. 2. The time-code converter according to claim 1, characterized in that the digital delay line is made in the form of a series circuit of controlled delay elements, the combined control inputs of which serve as the control input of the digital delay line, and their outputs - the outputs of the digital delay line. 3. The time-code converter according to claim 1, characterized in that the phase interpolation unit contains sequentially connected interpolation stages, each i-th interpolation stage has (2 ^i-1 +1) inputs and (2 ⁱ +1) outputs, outputs the final interpolation stage serve as the outputs of the phase interpolation unit, each interpolation stage includes (2 ^i-1 + 1) interpolation elements having the first and second paraphase inputs and the paraphase output, the first and second inputs of the interpolation elements with odd serial numbers in each mentioned stage round off are not used as inputs of the interpolation cascade, the first and second inputs of interpolation elements with even serial numbers in each cascade are connected to the combined inputs of the corresponding interpolation elements with odd serial numbers differing from the serial number of this interpolation element by ± 1, the outputs of all interpolation elements of this cascade make up the set of outputs of the interpolation cascade.

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