RU2546075C1 - Time interval digital measuring transducer - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device, comprising an interpolating time-to-number converter connected by its first and second inputs to signal clamps of the beginning and end of the interval, includes a plurality of additional analogue interpolating time-to-number converters.

EFFECT: high accuracy of digital conversion of a time interval into a digital code.

2 cl, 2 dwg

Description

FIELD OF THE INVENTION

The present invention relates to techniques for the precision measurement of single time intervals.

State of the art

To convert time intervals to digital code, time counters are widely used, the action of which is based on counting the number of pulses of the reference frequency that fit into the converted time interval [1]. Improving the accuracy of such devices is achieved by reducing the time sampling step, either by increasing the reference frequency, or by interpolating the reference period. The first way has obvious limits due to the speed of the digital element base.

Known digital interpolating time interval meter [2], which contains a reference pulse generator, the output of which is connected through the first element And to the input of the pulse counter, while the remaining input of the first element And is connected to the output of the trigger, the inputs of which serve as inputs of the start and stop signals of the device. In addition, there is a series circuit of a plurality of delay elements connected to the output of the reference generator, the output of each of which is connected to the reset input of the corresponding additional trigger, the number of which is equal to the number of delay elements. The outputs of all additional triggers are connected to the inputs of the encoder. The measurement process begins after resetting the pulse counter and triggers by a start pulse, and ends with a stop pulse. The highest bits of the measurement result are generated at the outputs of the pulse counter and display an integer number of reference periods that fit into the measured interval, and the least significant bits of the result are generated at the encoder outputs and display the fractional part of the reference period - the remainder of dividing the interval by the reference period in units of the delay time of the delay element. The disadvantage of this analogue is the low accuracy of measuring the time interval, since the sampling step cannot be less than the delay time of the delay element.

Analogs of the present invention are also schemes of digital time-code converters, in which a nonius method for evaluating the fractional part of the time interval measured by the reference generator is used, for example, the scheme described in [3]. This device includes a primary and secondary pulse generators, the periods of which differ by a small amount, which is the value of the resolution in time. The known device also includes two triggers and two AND valves, controlling the process of the vernier sweep, as well as two pulse counters that display the measurement result. With high accuracy of measurement of this device, it has low productivity - a large "dead" time, since the process of vernier sweep after the end of the converted interval takes many reference periods.

Another analogue of the present invention is a time interpolator [4] containing a pulse counter and a partitioned delay line, the inputs of which are connected to a common terminal of the reference signals. The device includes a register in the form of a plurality of triggers with common information and fault inputs, the trigger synchronizing inputs being connected to the corresponding intermediate taps of the delay line. In addition, the scheme includes read-only memory (ROM), which serves as a converter of the thermometric code formed by the triggers of the register in binary code. The total delay time of the partitioned delay line is one reference period. The device is started by a start pulse synchronized with the reference signal, which allows the pulse counter to work. At the same time, reference signals propagate along the delay line. At the moment of arrival of the stop pulse, the pulse counter records the number of complete reference periods that fit into the measured interval, and the register indicates the number of taps of the partitioned delay line to which the reference signal has propagated. As a result, the counter reflects the high bits of the measurement result, and the ROM reflects the low bits. The measurement error is determined by the delay time of the delay line section, which is significantly less than the reference period. At the same time, such a resolution of the time-code converter in many applications is insufficient, in addition, there is an additional source of conversion error associated with the uneven delay of individual sections of the delay line.

Of the known analogues, the closest in technical essence to the present invention is a device for measuring the time interval [5] with a reference oscillator in the form of a multiphase ring oscillator (MCG), the set of outputs of which forms a subscale of the time reference. The MCG outputs are connected to the corresponding information inputs of two registers, the clock inputs of which are connected to the input terminals of the signals of the beginning and end of the time interval, and the outputs are connected through the corresponding encoders to the lower inputs of the corresponding operands of the subtraction unit. In this case, the senior inputs of the first operand of the subtraction unit are connected via the third register to the outputs of the pulse counter, which determines the integer number of reference periods in the measured time interval. There is also a fourth register for recording the measurement result at the end of the time interval. In this analogue, there is no need to synchronize the origin of the interval with the reference pulse, and the unevenness of the time slices by the MCG outputs can be obtained quite small. However, the accuracy of the measurement in the prototype device is still limited by the value of the above-mentioned MCG time quantum; an additional error can cause instability of the ICG reference period.

SUMMARY OF THE INVENTION

раз. Особенностью использованного в предлагаемом устройстве метода является то, что процессы измерения величины разнесены не во времени, а в пространстве.The aim of the present invention is to improve the accuracy of digital conversion of a single time interval into a digital code. This goal is achieved by reducing the random component of the error by averaging the results obtained simultaneously by many independent interpolating time-code converters. As is known, an n-fold measurement of the same physical quantity allows one to increase the measurement accuracy in $$\sqrt{n}$$

time. A feature of the method used in the proposed device is that the processes of measuring the magnitude are spaced not in time, but in space.

This goal is achieved by the fact that many additional analogous time-code interpolating converters are introduced into the device containing the time-code interpolating converter with its first and second inputs connected to the terminals of the interval start and end signals. The inputs of the same name of all interpolating time-code converters are combined, and their third combined inputs are connected to the output of the reference generator, and multi-bit outputs are connected to the information inputs of the corresponding registers. The clock inputs of the registers are connected to the terminal signal of the interval through the delay element, and the outputs to the corresponding inputs of the averaging unit.

In a preferred embodiment, each interpolating time-code converter is constructed in the form of a multiphase ring generator, with its many outputs connected to the information inputs of the first and second registers. The clock inputs of the mentioned registers serve as the first and second inputs of the interpolating time-code converter, and the outputs are connected to the inputs of the corresponding first and second encoders, and one of the outputs of the multiphase ring generator is connected directly to the clock input of the first pulse counter and to the reset input of the second pulse counter through the divider frequency. The reset input of the first pulse counter is connected to the first input of the time-code interpolating converter, and the clock input of the second pulse counter serves as the third input of the time-code interpolating converter. In this case, the outputs of the first and second pulse counters are connected to the information inputs of the third and fourth registers respectively, the clock inputs connected respectively to the clock input of the second register and the output of the frequency divider. The outputs of the first and second encoders, the third and fourth registers are connected to the corresponding multi-digit digital inputs of the arithmetic block.

The device does not require stabilization of the MCG period in interpolating time-code converters, which compares it favorably with the prototype, since it becomes possible to implement it on a user-programmable gate array.

List of drawings

In FIG. 1 is a functional electrical diagram of a digital time interval transmitter in accordance with the present invention.

In FIG. 2 shows a functional electrical diagram of a preferred embodiment of a time-code interpolating transducer included in a time interval digital transducer.

Information confirming the possibility of carrying out the invention

As shown in FIG. 1, for definiteness, four identical interpolating converters 1 ... 4 time codes are included, in which the first combined inputs are connected to the input terminal 5 of the beginning signal of the interval, the second combined inputs are connected to the input terminal 6 of the end interval signal, and the third combined inputs to the output of the reference generator 7. The digital outputs of the interpolating converters 1 ... 4 time code are connected to the information inputs of the corresponding registers 8 ... 11, the clock inputs to which through the delay element 12 is connected to the terminal 6 of the interval end signal, and their digital outputs are connected to the corresponding inputs of the averaging unit 13.

In a preferred embodiment, each of the time-code interpolating converters 1 ... 4 (Fig. 2) contains MKG 14, with a plurality of outputs connected to information inputs of the first 15 and second 16 registers, equipped with output encoders 17, 18, the clock inputs of the said registers are connected respectively with the first 19 and second 20 inputs of the described Converter. One of the outputs MKG 14 is connected to the clock input of the first counter 21 pulses and through the divider 22 frequency - with the reset input of the second counter 23 pulses, its clock input connected to the third input 24 of the Converter. The multi-bit outputs of the first 21 and second 23 pulse counters are connected to the information inputs of the third 25 and fourth 26 registers, the clock input of the third register 25 is combined with the clock input of the second register 16, and the clock input of the fourth register 26 is connected to the reset input of the second pulse counter 23. The multi-bit digital outputs of both encoders 17, 18, the third 25 and the fourth 26 registers are connected to the corresponding digital inputs of the operands of the arithmetic unit 27, the set of outputs 28 of which is the digital output of the interpolating converter 1 ... 4 time-code.

To clarify the principle of operation of the device, we first consider the functioning of its main unit - shown in FIG. 2 interpolating time-code converters. The main difference between this unit and the prototype is that there are no special requirements for the accuracy and stability of the MKG 14 pulse frequency, which simplifies the implementation of the device on a Field Programmable Gate Array (FPGA), where analog adjustment of the frequency of the generated pulses is impossible. Instead of stabilizing the frequency, it is continuously measured, and the measurement result is used to calculate the value of the converted time interval.

MKG 14 continuously generates multiphase pulses at its N outputs with a period T _MKG = 2Nt _D , shifted in time with a step t _D , and in phase by π / N (t _D is the delay time of the MCG cascade). These pulses are fed to the information inputs of the first 15 and second 16 registers, which at the timing of the signals, respectively, of the beginning of the interval at input 19 and the end of the interval at input 20, fix the positions of these signals on the ICC internal subscale in the form of thermometric codes, which are further converted by encoders 17 and 18 to the binary numbers indicated in FIG. 2 respectively as K ₂ and K ₁ . These numbers mean the number of quanta t _D time from the beginning of the MCG period to the moments of arrival of input signals at the beginning and end of the time interval. Accordingly, the delay times of these signals relative to the beginning of the MCG period are K ₂ t _D and K ₁ t _D.

In addition, the first pulse counter 21, the operation of which is allowed after the arrival of the interval start signal at input 19, counts the number K _{0 of} MKG pulses 14 that fit into the interval between its start and end signals. At the end of the interval, the number K _{0 is} recorded in register 25, this number displays the duration K _{0 of the} ICG pulse periods, i.e. 2K ₀ Nt _D. Thus, the measured value of the time interval will be equal

To find the value of t _D included in (1), a counter of 23 pulses with a frequency divider 22 is used, which continuously measure the period T of the _MCG pulses of the MCG 14. The frequency divider 22 with the division module D forms meander pulses with half waves of equal duration

During one half-wave, the second counter 23 pulses is kept in the reset state, during the other half-wave it is filled with pulses of the reference oscillator 7 received at input 24, each time reaching the state

This number at the end of the interval is rewritten in the fourth register 26. From the expression (3) it follows that

Thus, at the outputs of the encoders 17, 18 and registers 25, 26, the numbers K ₀ , K ₁ , K ₂ , M are formed, which then arrive at the corresponding inputs of the arithmetic block 27. The arithmetic block 27 calculates the value of the measured time interval by the formula (1) , which, taking into account (4), takes the form

All n conversion channels work in a similar way, after the end of the measured time interval they form n independent results T _X1 , T _X2 , ..., T _Xn . In the main circuit of the device (Fig. 1) with a delay of the delay element 12 sufficient to complete the calculations in the arithmetic unit 27, these results are written in n registers 8 ... 11 (in this example, their number is four), and then they are sent to the averaging unit 13 . Block 13 averaging forms the final result of the conversion in accordance with the expression

where K _0k , K _1k , K _2k are the output numbers of the k-th interpolating time-code converter.

раз, для рассмотренного примера осуществления устройства с четырьмя каналами преобразования случайная ошибка уменьшается в два раза по сравнению с прототипом. Таким образом, в предложенном устройстве может быть достигнуто разрешение по времени, существенно меньшее задержки каскада МКГ - задержки логического вентиля.By averaging the results of n measurements of the same time interval, the random measurement error is reduced by $$\sqrt{n}$$

times, for the considered example of the implementation of the device with four conversion channels, the random error is reduced by half compared with the prototype. Thus, in the proposed device, a time resolution can be achieved that is significantly less than the delay of the MCG cascade — the delay of the logic gate.

Literature

1. Rathor T.S. Digital measurements. ADC / DAC. - M .: Technosphere, 2006, p. 22, fig. 2.1.

2. Shlyandin V.M. Digital measuring devices: Textbook for high schools. - M.: Higher School, 1981, p. 166, fig. 3.27.

3. In the same place, with. 163, fig. 3.25.

4. US patent 4439046, IPC G04 8/00, 03/27/1984

5. RF patent 2260830. A device for measuring the time interval, IPC G04F 10/04, the decision to grant a patent on 09/20/2005 (prototype).

Claims (2)

1. A digital measuring instrument of the time interval, containing an interpolating time-code converter, its first and second inputs connected to the terminals of the signals of the beginning and end of the interval, characterized in that a plurality of additional interpolating time-code converters are introduced into which the inputs of the same name are combined, their third combined inputs are connected to the output of the reference generator, and multi-bit outputs are connected to the information inputs of the corresponding registers, the clock inputs of which are connected They are used to clamp the signal of the end of the interval through the delay element, and the outputs to the corresponding inputs of the averaging block. 2. The digital measuring converter of the time interval according to claim 1, characterized in that each interpolating converter is a time-code made in the form of a multiphase ring generator, with a plurality of its outputs connected to the information inputs of the first and second registers, the clock inputs of which serve as the first and second inputs of the interpolating the time-code converter, and the outputs are connected to the inputs of the corresponding first and second encoders, and one of the outputs of the multiphase ring generator is connected to the clock the input of the first pulse counter directly and with the reset input of the second pulse counter via the frequency divider, the reset input of the first pulse counter is connected to the first input of the time-code interpolating converter, the clock input of the second pulse counter serves as the third input of the time-code interpolating converter, while the outputs of the first and the second pulse counters are connected to the information inputs of the third and fourth registers, respectively, clock inputs connected respectively to the clock during the second register and the output of the frequency divider, the outputs of the first and second encoders, third and fourth registers are connected to the respective multibit digital input of the arithmetic unit.

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