RU2385479C2 - Interpolating digital-time converter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: interpolating digital-time converter has a calibration unit, fourth and fifth registers, an inverter and a pulse frequency metre. Corresponding inputs of the resolver are connected to outputs of the pulse frequency metre, fourth and fifth registers, data inputs of the fourth and fifth registers are connected to corresponding outputs of the first and second coders. Clock inputs of the first and second registers, trigger, as well as inputs of the pulse frequency metre and the calibration unit are connected to outputs the volgate-controlled generator whose control input is connected to the output of the calibration unit, the input terminal is connected to the reset input of the pulse counter, the clock input of the third register, the input of the first digital delay line, the enable input of the first register and through the inverter to the rest input of the trigger and the enable input of the second register, true and complementary outputs of the trigger are connected to the clock inputs of the fourth and fifth registers respectively.

EFFECT: increased stability due to constant evaluation of accuracy and calibration of conversion.

2 dwg, 2 cl

Description

FIELD OF THE INVENTION

The present invention relates to techniques for the precision measurement of time intervals, in particular to devices for measuring the duration of a single pulse.

State of the art

To measure time intervals, time-code converters are widely used, the action of which is based on counting the number of pulses of the reference period that fit into the measured time interval. To improve the accuracy of the conversion by reducing the time quantization step, various methods of interpolation of the reference period are used.

Known digital time interval meter [1], which contains a reference pulse generator, the output of which is connected through the first element And to the input of the pulse counter, while the remaining input of the first element And is connected to the output of the trigger, the inputs of which serve as inputs of the start and stop signals of the device. In addition, there is a series circuit of a plurality of delay elements connected to the output of the reference generator, the output of each of which is connected to the reset input of the corresponding additional trigger, the number of which is equal to the number of delay elements. The outputs of all additional triggers are connected to the inputs of the encoder. The measurement process begins after resetting the pulse counter and triggers by a start pulse, and ends with a stop pulse. The leading bits of the measurement result are generated at the outputs of the pulse counter and display an integer number of reference periods that fit into the measured interval, and the least significant bits of the result are generated at the encoder outputs and display the fractional part of the reference period - the remainder of dividing the interval by the reference period in units of the delay time of the delay element. The disadvantage of this analogue is the low accuracy of the measurement, the error of which cannot be less than the delay time of one delay element.

Analogs of the present invention are also schemes of digital time-code converters in which a nonius method for evaluating the fractional part of a time interval measured by a reference generator is used, for example, the circuit described in [2]. This device includes a primary and secondary pulse generators, the periods of which differ by a small amount, which is the value of the resolution in time. The known device also includes two triggers and two And elements that control the vernier sweep process, as well as two pulse counters that display the measurement result. With high accuracy of measurement of this device, it has low productivity, since the vernier sweep process takes many reference periods, the greater, the higher the measurement accuracy.

Another analogue of the present invention is a time interpolator [3] containing a pulse counter and a partitioned delay line, the inputs of which are connected to a common terminal of the reference signals. The device includes a register in the form of a plurality of triggers with common information and fault inputs, the trigger synchronizing inputs being connected to the corresponding intermediate taps of the delay line. In addition, the scheme includes read-only memory (ROM), which serves as a converter of the thermometric code of the register into binary code. The total delay time of the partitioned delay line is one reference period. The device is started by a start pulse synchronized with the reference signal, which allows the pulse counter to work. At the same time, reference signals propagate along the delay line. At the moment of arrival of the stop pulse, the pulse counter records the number of complete reference periods that fit into the measured interval, and the register indicates the number of taps of the partitioned delay line to which the reference signal has propagated. As a result, the counter reflects the high bits of the measurement result, and the ROM reflects the low bits. The measurement error is determined in analogue by the delay time of one section of the delay line, which is significantly less than the reference period. In addition, there is an additional source of conversion error due to the possible uneven delay of individual sections of the delay line.

The closest in technical essence to the present invention is a device for converting a time interval with double interpolation [4]. This analogue, adopted as a prototype, is built on the basis of a multiphase generator (MFG). One register with the output encoder fixes the binary code of the position of the Start signal inside the MFG reference period, and the second register with its encoder fixes the code of the Stop signal position. During the interval between the input signals, the pulse counter is allowed to operate, which displays in binary code the number of complete reference periods that fit into the converted interval. The status of the pulse counter is also recorded in the third register by the Stop signal.

The MFG, built on the basis of a chain of delay elements, generates meander pulses at each output. At the moments when the Start and Stop input signals arrive, the thermometric codes of their phases are recorded in the first and second registers, which are counted from the interpolating subscale of the MFG. Since the state of the first output of the register serves as a sign of the type registered by the MFG wave, it can be considered as the state of the highest bit of the binary phase code. The encoders convert the thermometric codes of the registers into binary numbers that reflect the serial numbers of the outputs of the registers on which the inversion of the logical state occurs, that is, the binary codes of the moments of arrival of the Start and Stop signals.

The advantages of this device include the simplicity and purely digital design of the device.

The disadvantage of the prototype is the lack of accuracy and low stability with changes in temperature and supply voltage, since there is no calibration mode.

SUMMARY OF THE INVENTION

The aim of the present invention is to improve the accuracy and stability of the time-code Converter. This goal is achieved by introducing a calibration procedure and fixing the recession and the front of the measured interval relative to the fronts of the voltage-controlled generator (VCO), which acts as a reference generator.

The interpolating time-code converter contains a first digital delay line (DLC), the set of outputs of which are connected to the corresponding information inputs of the first and second registers, the outputs of which are connected to the corresponding inputs of the first and second encoders, respectively, as well as a VCO connected to the pulse counter clock input , a trigger, the installation input of which is connected to the input terminal of the device, a third register, information inputs connected to the corresponding outputs of the pulse counter s, and outputs - to the corresponding inputs of the casting unit. To achieve this goal, a calibration block, fourth and fifth registers, an inverter and a pulse frequency meter are additionally introduced, and the corresponding inputs of the deciding block are connected to the outputs of the pulse frequency meter, fourth and fifth registers, while the information inputs of the fourth and fifth registers are connected to the corresponding outputs of the first and second encoders, the clock inputs of the first and second registers, the trigger, as well as the inputs of the pulse frequency meter and the calibration unit are connected to the output of the VCO, The control code of which is connected to the output of the calibration unit, the input terminal is connected to the pulse counter reset input, the third register clock input, the first DLC input, the first register enable input, and through the inverter to the trigger reset input and the second register enable input, direct and inverse trigger outputs connected to the clock inputs of the fourth and fifth registers, respectively.

The calibration unit contains a second DLC, a sixth register, the information inputs of which are connected to the corresponding outputs of the second digital delay line, and the outputs are connected to the corresponding inputs of the third encoder, the outputs associated with the digital input of the comparator, the outputs of which are connected to the corresponding inputs of the reversible pulse counter, and the reversible counter its outputs are connected to the inputs of the digital-to-analog converter (DAC), the output of the DAC is the output of the calibration unit, and the input of the second DLC and the clock input of the sixth Registers are input calibration unit.

The first and second DLC can be made in the form of a sequential chain of delay elements.

The principle of operation of the proposed device is based on the gating of the states of the first CLL during the propagation of a measured time interval over it, relative to the period of the VCO pulses. The indicated states corresponding to the digital counting of the edge and fall of the time interval are remembered by the first and second registers, which are clocked by the pulses generated by the VCO T ₀ . The number of full VCO periods falling within the interval is fixed by a pulse counter and stored in the third register. The calibration unit adjusts the frequency of the VCO so that its pulses propagating along the second DLC pass a certain number of links of the second DLC equal to Q, and the value of Q constantly tends to be equal to the constant A supplied to the input of the comparator. Data from the outputs of the frequency meter, the third, fourth and fifth registers are accumulated and processed in the decision block.

The code reflecting the duration of the interval is:

where N ₀ is the binary state of the third register, N ₁ , N ₂ are the binary states of the fourth and fifth registers of the encoders, A is the constant supplied to the input of the comparator in the calibration block.

Thus, in the proposed interpolating time-code converter, the result is constantly calibrated. Measurement evaluation is performed in each period of the VCO, the number Q received at the output of the third encoder, tending to be equal to constant A, allows us to estimate the current value under the conditions of the delay time of the second link CLS link as t _D = T ₀ / A and take it into account when calculating the duration of the measured interval .

List of drawings

Figure 1 presents a functional diagram of an interpolating time-code converter in accordance with the present invention.

Figure 2 shows the timing diagrams of the signals explaining the principle of operation of the interpolating converter time-code.

Information confirming the possibility of carrying out the invention

The diagram of the time-code interpolating converter shown in FIG. 1 contains an input terminal 1, a first DLC 2, a voltage-controlled generator 3, an inverter 4, a pulse counter 5, the first to fifth registers 6-10, trigger 11, the first 12 and second 13 encoders , a frequency meter 14 pulses, a deciding unit 15 and a calibration unit 16, the corresponding inputs of the deciding unit 15 being connected to the outputs of the third register 8, a frequency meter 14 pulses, the fourth 9 and fifth 10 registers, while the information inputs of the fourth 9 and fifth 10 registers are connectedwith the corresponding outputs of the first 12 and second 13 encoders, the inputs of which are connected to the outputs of the first 6 and second 7 registers, respectively, the information inputs of which are connected to the corresponding outputs of the first DLC 2, and the information inputs of the third register 8 are connected to the corresponding outputs of the pulse counter 5, clock inputs the first 6 and second 7 registers, pulse counter 5, trigger 11, as well as the inputs of the frequency meter 14 pulses and the calibration unit 16 are connected to the output of the generator controlled by voltage 3, the control input If it is connected to the output of the calibration unit 16, the input terminal 1 is connected to the inverse input of the reset of the pulse counter 5, the clock input of the third register 8, clocked down, the input of the trigger setting 11, the input of the first DSC 2, the input of the first work register 6 and the inverter input 4, the output of which is connected to the reset input of the trigger 11 and the enable input of the second register 7, the direct and inverse outputs of the trigger are connected to the clock inputs of the fourth 9 and fifth 10 registers, respectively.

The calibration unit contains a second DLC 17, sixth register 18, the information inputs of which are connected to the corresponding outputs of the second DLC 17, and the outputs to the corresponding inputs of the third encoder 19. The third encoder 19, comparator 20, the reverse counter 21 and the DAC 22 are connected in series with each other moreover, the output of the DAC 22 is the output of the calibration unit 16, and the input of the second DLC 17 and the clock input of the sixth register 18 are the input of the calibration unit 16 connected to the output of the voltage-controlled generator 3.

DLC 2 and 17 in a preferred embodiment are a series circuit of delay elements. A delay element can be any non-inverting logic element. A computer can be used as a decisive block.

The operating order of the device (figure 1) is illustrated by the timing diagrams shown in figure 2. VCO 3 continuously supplies the second DLC 17 with reference pulses 24. The constant A is supplied to the input of the comparator, which determines how many links of the second DLC 17 will pass the pulses generated by the VCO 3. In each period of the VCO 3, the combination of numbers from the output of the second DLC 17, in the form of a thermometric code, through the sixth register 18, it is supplied to the third encoder 19, converting it into binary Q form. Comparator 20, comparing two numbers at its inputs: Q and constant A, produces a sign based on which the reversible pulse counter 21 adds or subtracts nitsu from its previous state. The state of the reverse counter 21 pulses is fed to the DAC 22, which adjusts the frequency of the VCO 3 so that its pulses propagating along the second DLC 17 pass a certain number of links equal to the constant A. Thus, the number at the output of the third encoder 19 Q will always tend to be equal to the constant A. By measuring the frequency of the VCO 3 with a frequency meter of 14 pulses and knowing that the value of Q constantly tends to be equal to the constant A, we find the value of the delay time of the link of the second DLC 17 as t _D = T ₀ / A, valid for two idents egg CLP 2 and 17.

The conversion process is initiated by a pulse of measured duration 23 Tx, which begins to propagate along the DSC 2 and simultaneously enables the operation of the pulse counter 5. At the moments of the appearance of the first 24 pulses from the VCO 3 after the front and the fall of the pulse 23 Tx, the digital states of the taps 25-30 of the DSC 2 are recorded in first 6 and second 7 registers. The codes recorded in registers 6 and 7 are thermometric codes of the form 000 ... 111, or 111 ... 000. These states after conversion in the first 12 and second 13 encoders to direct binary codes reflect the quantization errors Δt ₁ and Δt ₂ 24 at the beginning and end of the pulse as binary numbers N ₁ and N ₂ , which are stored in the fourth 9 and fifth 10 registers. The pulse counter 5 to the end of the pulse 23 T _X reaches the state N ₀ , remembered by the third register 8. The value at the output of the frequency meter 14 pulses and the number N ₀ from the outputs of the third register 8, N ₁ and N ₂ from the outputs of the fourth 9 and fifth 10 registers, respectively , the operation of which is controlled by the trigger 11, are transmitted to the corresponding inputs of the decision block 15 to calculate the value of the interval:

The conversion error consists of the error in estimating the delay time of the link of the second CLL 17 and the estimation error Δt ₁ and Δt ₂ 24 and is:

Thus, the proposed device performs the conversion of time-code and at the same time evaluates the accuracy of the conversion, compensating for the low stability when using the CLZ.

Compared with the prototype, the proposed device provides higher stability due to the constant assessment of accuracy and calibration of the conversion.

Literature

1. Shlyandin V.M. Digital measuring devices: Textbook for high schools. - M.: Higher School, 1981, p. 166, Fig. 3.27.

2. Ibid., P.163, fig. 3.25.

3. US patent 4439046, IPC G04 8/00, 03/27/1984

4. Device for measuring the time interval. - RF patent №2260830 / Chulkov V.A.

Claims (2)

1. An interpolating time-code converter containing a first digital delay line, the set of outputs of which are connected to the corresponding information inputs of the first and second registers, the outputs of which are connected to the corresponding inputs of the first and second encoders, respectively, as well as a voltage-controlled generator connected to the input clock of the pulse counter, a trigger, the installation input of which is connected to the input terminal of the device, the third register, information inputs connected to the corresponding the output outputs of the pulse counter, and the outputs to the corresponding inputs of the decisive unit, characterized in that it includes a calibration unit, fourth and fifth registers, an inverter and a pulse frequency meter, and the corresponding inputs of the decisive block are connected to the outputs of the pulse frequency meter, fourth and fifth registers, while the information inputs of the fourth and fifth registers are connected to the corresponding outputs of the first and second encoders, the clock inputs of the first and second registers, the trigger, as well as the measurement inputs The pulse frequency amplifier and the calibration unit are connected to the output of a voltage controlled generator, the control input of which is connected to the output of the calibration unit, the input terminal is connected to the pulse counter reset input, the third register clock input, the first digital delay line input, the first register enable input and through the inverter - with the trigger reset input and the second register enable input, the direct and inverse trigger outputs are connected to the clock inputs of the fourth and fifth registers, respectively. 2. The time-code interpolating converter according to claim 1, characterized in that the calibration unit comprises a second digital delay line, a sixth register, the information inputs of which are connected to the corresponding outputs of the second digital delay line, and the outputs to the corresponding inputs of the third encoder, outputs connected with a digital input of a comparator, the outputs of which are connected to the corresponding inputs of a reversible pulse counter, and the reversible counter with its outputs connected to the inputs of the digital-analog converter , Output digital to analog converter is an output of the calibration unit and the input of the second digital delay line and a clock input of the sixth register are input calibration unit.

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