SU1451830A1 - Program-controlled sine-wave oscillator - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to increase the stability of the output voltage level. The generator contains the reference Mr. 1, two dividers 2 and 18 frequencies, a sensor 3 of the frequency grid, 4 with adjustable transmission ratio, two 5 5 and 25 power, an automatic output block

Description

The invention relates to radio engineering and communications, is intended to receive sinusoidal oscillations from program control signals and can be used in measurement and control systems.

The aim of the invention is to increase the stability of the output voltage level.

FIG. Figure 1 shows a structural electrical circuit of a software-controlled sinusoidal oscillator; in fig. 2 - the same, control unit; in fig. 3 - the same, operational memory unit; in fig. 4 the same, pulse shaping unit; in fig. 5 a, b, c, d, e, g, g, h, and timing diagrams that explain the operation of the program-controlled oscillator.

Software controlled generator

sinusoidal oscillations (figure 1) contains a reference oscillator 1, the first frequency divider 2, a frequency grid sensor 3, an amplifier 4 with adjustable transmission coefficient, the first power amplifier 5, black 6 automatic gain control (AGC), switch 7, the first register 8 memory, the first digital-to-analog converter (DAC) 9, the second register 10 of memory, the second decoder 11, the operational memory unit 12, the digital indicator 13, the information input unit 14, the control unit 15, the oscillator 16, the output pulses, the comparator 17,

a frequency divider 18, a pulse counter 19, a permanent memory block 20, a code converter 21, a buffer register 22, a second DAC 23, a low-pass filter 24, a second power amplifier 25, a voltage level converter 26, an adder 27, a first decoder 28, a pulse shaping unit 29, an inverter 30, the first element AND 31, the second element AND 32

trigger 33.

The control unit 15 (FIG. 2) contains the first decoder 34, the trigger 35, the first and second elements OR 36, 37, the first and second elements 38, 39, the first and second counters 40, 41, the first and second inverters 42, 43, shift register 44, the second decoder 45, differentiating the KS circuit 46.

The operational memory unit 12 (FIG. 3) contains the first, second and third memory registers 47 to 49, multiplexer 50.

The pulse shaping unit 29 (FIG. 4) contains the first and second elements IPI-NE 51, 52, the AND-NE element 53, the AND element 54, the shift register 55.

A software-controlled generator of sinusoidal oscillations operates as follows.

Software control signals for the frequency and amplitude of the output signal are sequentially input by the operator through information input block 14, from whose output the control signal is fed to the input of the first control unit.

the decoder 34 and through the differentiating KS circuit 46 to the inputs of the first 40 and second 41 counters of the control unit 15, as well as to the information inputs of registers 47 - 49 of the memory of the operational memory unit 12.

The signal from the output of the first decoder 34 changes the state of the trigger 35 and simultaneously, having passed the first element OR 36, sets the initial state of the operational storage unit 12, releasing the first 47, second 48 and third 49 memory registers of operational unit 12 storing from the previously entered information, after which a new information is recorded on the clock signal with the value of the frequency set by the operator exceeds the low frequency range of the output signal level stabilization, then at the output of the trigger 33 The state of a logical zero is brought into being by supplying pulses from an output of an AND 31 element (FIG. 5e) to its input, forming a 1x when the pulses coincide with the outputs of the pulse shaping unit 29 (inverted inverters 30), the first And 38 element and the second decoder 45 of the control unit . In this state, the logical zero at the output of the flip-flop 33 switches the switch 7, and the signal of the set frequency from the output of the first power amplifier 5 is fed directly to the output of the software-pn

of the decoder 34. Pulses.tact-20 equal to the generator sinusoidal

synchronization from the generator output 16 clock pulses arrive at the synchronization input of the first counter 40 and then through the first 42, the second 43 inverters and the shift register 44 to the inputs of the first and second elements 38, 39 (Fig. 5c).

The address outputs of the control unit 15 are the outputs of the second counter 41. According to the address received at the input of the multiplexer 50, the memory registers 47-49 of the memory unit 12 are polled.

The data is changed with the end of the input signal, after which, from the output of the decoder 34, the corresponding pulse through the second element OR 37 is fed to the input of the first element 38 and further to the clock input of the register 8 of the memory. The set value of the frequency of the output signal is displayed on the display of the digital indicator 13.

ment 38 (fig. 5 b) and the decoder 45 of the control unit 15 (fig. 5 c). The state of the logical unit from the output of the trigger 33 is fed to the input of the adder 27, which corresponds to adding to the value of the current code an additional address number. The address code modified in this way is fed to the input of the second decryptor In accordance with the frequency code set at the output of register 8 of memory- g pa 28 and the frequency grid sensor 3 determines the recording of the frequency connected to the bits of memory register 8, connected to the reference oscillator 1 through which it turns out to be more luminescent — the first divider 2 frequencies produced on the digital display panel sine wave signal arrives 13 times 10,000 times. The blanking signal is unknowing to the input of the amplifier 4. Block 6 AGC gQ of querying zeros is formed by block 29

provides a constant output voltage level, and when the reference voltage produced by the first DAC 9 changes, it allows you to change the output voltage level. From the output of the power amplifier 5, the signal of the set frequency is fed to the first input of the switch 7 controlled from the trigger 33.

55

forming pulses (Fig. 5 g, d) when the information signal from the output of the operational value block 12 is applied to the first element ILTH-HE 51, and the control signals (Fig. 5 a) to the inputs of the AND-NE elements 53 and 54 and the input synchronization register 55 shift. Formed zero quenching impulses from the output of the second ele

fluctuations. In addition, the state of the logical zero at the gate input of the comparator 17 prohibits the passage of pulses to the input of the second divider 18.

If the value set by the operator frequency is in the range of stabilization of the output signal level, the trigger 33 is set to one state due to the arrival at its input of pulses from the output of the second element AND 32 (figure 5 and) formed when the pulses from the outputs of the formation unit 29 coincide. pulses (fig. 5, h), first ele

ment 38 (fig. 5 b) and the decoder 45 of the control unit 15 (fig. 5 c). The state of the logical unit from the output of the trigger 33 is fed to the input of the adder 27, which corresponds to adding to the value of the current code an additional address number. The address code modified in this way is fed to the input of the second decoder 28 and determines the recording of the frequency value in the register 8 bits of the memory, which is more than the digital indicator 13 displayed on the display 10 times 10,000 times. The zero blanking signal is generated by block 29

g pa 28 and determines the recording of the frequency value in the bits of the memory register 8, which is more than the digital indicator 13 displayed on the display 10 times 10,000 times. The blanking signal of unqualified zeros is generated by block 29

55

forming pulses (Fig. 5 g, d) when the information signal from the output of the operational value block 12 is applied to the first element ILTH-HE 51, and the control signals (Fig. 5 a) to the inputs of the AND-NE elements 53 and 54 and the input synchronization register 55 shift. Formed zero quenching impulses from the output of the second ele10

COP OR NOT 52 is fed to the inverter 30 and the second element AND 32.

The bit outputs of memory register 8 control the frequency variation of frequency grid sensor 3 and, from the output of the first power amplifier 5, the signal of the set frequency is fed to the input of the comparator 17, which converts the sinusoidal signal to square pulses fed to the input of the second frequency divider 18.

Thus, in the low-frequency range, the frequency grid sensor 3, together with the amplifier 4, is used as a clock frequency driver. The output signal is generated by the method of passive synthesis, based on the use of counter 1 9 as the source of the phase code and the permanent storage unit 20 as a functional converter of the phase code to the code of the output signal level values. Passing through the code converter 21 and the Shufer register 22, the signal is converted by the second DAC 23 into analog form and through the low-pass filter and the second power amplifier 25 is fed to the input of the switch 7. At the same time, the equivalent division factor of the second divider 18 and the counter 19 is selected such that the frequency to be synthesized will always coincide with the value on the display of digital indicator 13.

The output voltage level is set in the same way, while the clock signal through the second element 1 of the 37 and the second element 39 comes to the clock input of the buffer register Y. The binary-decimal code of the signal level at the output of the buffer register 10 is converted by the first DAC 9 to the reference voltage The voltage supplied to the AGC block and the voltage level converter 26, which is the reference for the second DAC 23. This allows the two channels of the output signal to be matched by the output voltage level. and get better stability level of the output voltage in the region of lower frequencies.

formula

and 3

gain 55

opa le le re ko ne som pits and 15 p 25 p 40

Claims (2)

1 Software-controlled sinusoidal oscillation generator, containing 1 connected successively ten with . - - about 20 55 - / W reference oscillator, first frequency divider and frequency grid sensor, the first power amplifier connected in series, an automatic gain control unit with an adjustable gain, a switch, the first information input of which is connected to the output of the first power amplifier, and the output is the output of a software-controlled oscillator sinusoidal oscillations, serially connected the first decoder and the first memory register, the output of which 15 is connected to the control input of the frequency grid sensor, sequentially the second decoder, the second memory register and the first digital-to-analog converter, the output of which is connected to the control input of the automatic gain control unit, the shift register, the serially connected information input unit and the operational memory unit, the output of which is connected to information inputs of the first memory register and the second memory register, serially connected clock generator and a control unit, the control input of which is connected to the output of the input block The address, the output of the control unit is connected to the input of the second decoder and the address input of the operational memory unit, the first, second and third clock outputs of the control unit are connected to the clock inputs of the first and second memory registers and the operational memory unit. The control unit output is connected to the setup input of the initial state of the operational memory unit, characterized in that, in order to increase the stability of the output voltage level, compactly connected comparator, second frequency divider, pulse counter, block of permanent memory and code converter, buffer register, second digital-to-analog converter, low pass filter and second power amplifier, the output of which is connected to the second information input of the switch, voltage level converter, output which is connected to the reference input of the second digital-to-analog converter, the series-connected forming unit thirty 35 45 50 t4 pulse, inverter, first element And, the trigger and the adder, the output of which is connected to the input of the first decoder, the second element AND, a digital indicator, the second input of the adder is connected to the address output of the control unit, the trigger output is connected to the comparator gating input and the control input of the switch, the control input of the forming unit the pulses are connected to the second control output of the control unit, and the information input of the pulse shaping unit is connected to the output of the operational memory block, the second and third inputs of the first element I are connected respectively It is connected with the third control and first clock outputs of the control unit, the output of the second element I is connected to the second input of the trigger, and the first, second and third inputs of the second element I are connected respectively to the output of the formation unit of the pulses and the first clock output the control unit, the control input of the digital indicator is connected to the address output of the control unit, and the information input of the digital indicator is connected to the output of the on-line memory unit, the second the frequency divider is connected to the clock input of the shift register, the high-end output of the pulse counter is connected to the control input of the code converter and the high-level input of the buffer register, the output of the frequency grid sensor is connected to the input of a variable gain amplifier whose output is connected to the first the power amplifier, the information input of the comparator is connected to the output of the first power amplifier, the information input of the second digital-to-analog converter is connected to the register register pass n, and the input voltage level converter coupled to the output of the first digital to analog converter. 2. The generator according to claim 1, about t l and five 0 five 0 five 0 five 0 The control unit contains serially connected first decoder, trigger and first element AND serially connected first counter, first inverter, shift register and second element AND, serially connected second counter and second decoder, first element OR whose inputs are connected to the corresponding the outputs of the lower bits of the first decoder, the second element OR, the output of which is connected to the second inputs of the first and second elements AND, as well as the second inverter, while the inputs of the second element OR is connected to the corresponding outputs of the higher bits of the first decoder, the output of the second inverter is connected to the information input of the shift register, the input of the second inverter is connected to the output of the senior bit of the first counter, and the first, second and third clock outputs of the control unit are And the second element and one of the high-order outputs of the first decoder, the control outputs of the control unit are the bit outputs of the second counter, and the first, second and third control their outputs of the control unit are the outputs of the first OR element, respectively, the upper bit output of the first counter and the second bit of the second decoder, the input of the first counter is combined with the input of the second counter and connected to the input of the first decoder, which is also connected to the trigger input of the trigger and is the control input of the control unit, the output of the higher bit of the first counter is connected to the clock input of the second counter, the third inputs of the first and second element And in connected respectively to the output of the shift register and M inverse trigger output, and a clock input of the control unit is taktovyr input of the first counter. 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