SU1732465A1 - Controlled divider of pulse repetition frequency - Google Patents

Abstract

The invention relates to computing and can be used in automation devices, in particular, as a frequency generator for a stepper drive. The purpose of the invention is the expansion of the range of output frequency and the expansion of functionality by forming an additional frequency signal, the device contains an element OR 1, a divider 2 frequencies with a variable division factor, trigger 3, counter 4, element 5 coincidence, whose first input is connected to the input bus 9 , which receives clock pulses, inverter 6, element 7, bus 8 Start, first output bus 10 of the device, bus 11 of the code of the division factor, bus 12 of the code setting of the frequency divider with variable frequency the division factor, the second output bus 13 of the device, while the divider 2 frequency contains the first and second counters and the element P-2I-OR-NOT. 1 h. n. f-ly, 3 ill.

Description

The invention relates to computing and can be used in automation devices, in particular as a frequency generator for a stepper drive.

A controlled frequency divider following the pulses is known, which contains an OR element, coincidence elements, the first and second three (heres, pulse counter, input bus, source bus, control bus, and output bus,

Closest to the proposed technical solution is a controlled pulse frequency divider comprising first and second triggers, a pulse counter, a coincidence element, an input bus to which the clock pulses, an output bus, and a divider 2 division coefficient code bus are used.

The disadvantage of this divider is that two impulses of the input frequency disappear from the process of forming the output frequency. which are used to generate a load pulse of a new division coefficient code in the counter, therefore, this must be taken into account in the law of variation of the division coefficient code. In addition, the range of change, the frequency at the output of the divider at a fixed input frequency is determined by the counter size and is limited by the finite number of counter bits, and with the same law of change of the input code of the division factor recorded in the counter, at a fixed the number of counter bits at the output is obtained only one frequency range, corresponding to the law of change of the input code of the division factor. In addition, the presence of one output in the future when generating synchronization signals for the following after the splitter circuit requires an increase in hardware costs, which reduces the functionality of the device.

The purpose of the invention is to expand the range of variation of the output frequency and expand the functionality by generating an additional frequency signal.

This goal is achieved in that a variable frequency divider with a variable division factor is entered into a divider containing a trigger, a counter, a matching element, the first input of which is connected to the input bus of the device to which the clock pulses go, the first output bus of the device and the code bus of the device dividing ratio. , OR element, inverter, And element, Start bus, the frequency divider contains the first, second and third inputs and output connected to the second output bus of the device whose Start bus is connected to the first input

frequency divider with variable division factor, with the first input of the OR element, and through an inverter with the second input of the AND element, the first input of which is connected to the output of the counter, and the output - with the S input

0 flip-flop, D-input of which is connected to the logic zero level, C-input is connected to C-input of the counter and connected to the output of a frequency divider with a variable division factor, the second input of which is 5 keys to the output of the OR element, the second input of which is connected to the input bus device, and the third with the inverse output of the trigger and the second input of the coincidence element, the output of which is connected to the counting input of the counter, the information inputs of which are respectively connected to the bus of the dividing ratio code of the device, the first output of which connected to the forward trigger output, the third input of the splitter with

5 is connected by a variable division factor to an n-bit device bus; in addition, a variable division factor frequency divider contains first and second counters and a P-2I-OR-NOT element,

0 while the output of the frequency divider with a variable division factor, which is the second output bus of the device, is connected to the output of the second counter, whose R input is connected to the R input of the first counter and connected to the first input of a frequency divider with a variable division factor, the second input which is connected to the C-input of the first counter, the outputs of which are respectively connected to the second inputs of the n elements 2I included in the P-2I-OR-NOT element, the first inputs of which are connected to the third input of the frequency divider dividing effect, connected respectively with n5 bit bus device, and the output of the element P-2I-OR-NOT connected to the C-input of the second counter.

FIG. Figure 1 shows the electrical functional diagram of the controlled unit of the pulse frequency body; in fig. 2 is an electrical functional frequency divider circuit with a variable division factor; in fig. 3 - timing diagrams, explaining the principle of operation

5 controlled pulse frequency divider.

The device contains the element OR 1, the divider 2 frequencies with a variable division factor, the trigger 3, the counter 4, the element 5 matches, the inverter 6, the element AND

7, start bus 8, input bus 9, first output bus 10, bus 11 of the division factor code, bus 12 for setting the frequency divider code with a variable division factor, second output bus 13. while the frequency divider 2 contains the first 14 and second 15 counters and element p-2I-OR-NOT 16, the output of which is connected to the C-input of the second counter 15. The R-input of which is connected to the R-input of the first counter 14 and connected to the first input of frequency divider 2, the second input of which is connected to C- the input of the first counter 14, the outputs of which are respectively connected to the second in 2I n rows of elements. element P-2I-OR-NOT 16, the second inputs n of elements 2I of which are connected to the third input of the frequency doubler 2, the output of which is the second output of the device and connected to the C inputs of trigger 3 and counter 4, information the inputs of which are connected to the bus 11 of the dividing ratio code of the device, and the output is connected to the first input of the element I7, the output of which is connected to the S-input of the trigger 3, the D-input of which is connected to the logic zero level, and the direct output is connected to the first output 10 of the device . bus 8 whose start is connected to the first input of the element OR 1, through the inverter 6 to the second input of the element AND 7 and to the first input of the frequency divider 2, the second input of which is connected to the output of the element OR 1, the second input of which is connected to the input bus 9 of the device and with the first input of coincidence element 5, the output of which is connected to the counting input of counter 4. And the second input is connected to the inverse output of trigger 3 and connected to the third input of the OR 1 element, while the third input of frequency divider 2 is connected to the bus 12. of the device.

The device works as follows.

In the initial state on bus 8 Start there is a level of logical units. which blocks the element OR 1 by its first input, resets the counters 17 and 18 to zero, and through the inverter 6 and the AND 7 element sets the trigger 3 to the state when the level of the logical unit is present at its forward output and the level of the logical one at the inverse the zero that blocks the coincidence element 5 generates at its output the level of a logical unit that arrives at the counting input of the counter 4. On the bus 11 of the code of the division coefficient any required code is set, for definiteness we assume that the bus 11 has the binary code of the number 100, and on bus 12 there is a binary code 10 ... Oh,

those. on the P-2I-OR-NOT 16 element, the upper assembly 2I was selected from item one of the first input of which is connected to the first output of counter 14. Counter 14 is binary, while at its first 5 output the frequency is two times less than the input frequency, on the second - four etc Counter 15 has a constant division factor, even though for example counter 15 is ten ,.

0 fine

Thus, for the example, the total division factor of the 2 frequency divider is twenty. In general, it can be equal to any constant number, depending on the binary code 12 installed on the bus with a unit in one of bits 1 ... P and the division factor of the counter 15. The zero level from the output of the counter 15 records the binary code .

0 installed on bus 11. into counter 4 with a single signal level at its counting input.

The operation of the divider begins at the time of the signal transition on the bus 8 Start to zero,

5 while the clock pulses fT arrive at the second input of the element OR 1 and through it to the second input of the divider frequency 2, which begins to count, Through the element 5 of coincidence the pulses of the input

0 frequency is not passed to the counting input of the counter 4 and the counter 4 does not count yet.

Divider 2 frequencies with a fixed division factor equal to for our example twenty, counts and through ten

5 impulses of the input frequency at its output there appears a difference from zero to one (fig. Za, b, c), according to which trigger 3 is triggered (fig. Zd), the inverse output of which by its unit level blocks the element

0 or 1 and. accordingly, the divider 2 frequencies and unlocks the coincidence element 5, through which the input frequency pulses arrive at the counting input of the counter 4. It counts for subtraction (it was written into it

5 binary code number 100). At the moment of the appearance of the one-hundredth of the input pulse, a negative pulse is generated at the output of counter 4, which again sets trigger 3 to unit state 0 (Fig. 3g, d). in this case, coincidence element 5 is blocked and counter 4 no longer counts and element OR 1 is unlocked, and divider 2 frequencies again continue to count. He perceives another ten pulses.

5 and at its output a transition from one to zero occurs, over which the binary code from the device bus 11 is written to the counter 4. The frequency divider 2 continues to count, and after another ten pulses at its output, the transition from zero continues again.

in the unit, the trigger 3 is triggered again, and g, d (Fig. Ws-d).

At the first output of the device, a sequence of pulses of period T and duration L is formed, and at the second, period T and duration TZ. moreover, n 2 T2,

In accordance with the change of the code on the device bus 11, according to any law, the period T of both pulse sequences will change, but the ratio m 2 Ha and the mutual arrangement of the two pulses will always be constant, which makes it possible to eliminate the input frequency pulses from the coefficient code writing procedure dividing into counter 4 and using combinations of these pulses to generate various sync signals, clearly tied to the input frequency, to control the operation of subsequent circuits, which expands the functional possibilities Nost device.

In addition, with the same law of change of the dividing ratio code on the device bus 11, with different dividers of dividing frequency 2, n ranges of two output frequencies can be obtained, inside each of which the law of frequency variation is the same and corresponds to the law of change of dividing ratio code on bus 11, which expands the range of output frequency variation.

Claims (2)

Claim 1. Controlled pulse frequency divider comprising a trigger, a counter, a matching element, the first input of which is connected to the input bus of the device to which the clock pulses arrive, the first output bus of the device and the bus of the device dividing code, characterized in that in order to expand the functionality and simplify the device, a variable divider frequency divider, an OR element, an inverter, an AND element, a Start bus have been entered into it, and the frequency divider contains he first, second and the third inputs and output connected to the second output bus of the device, whose bus start is connected to the first input of a frequency divider with a variable division factor, to the first input of the OR element and through an inverter to the second input of the AND element, the first input of which is connected to the output of the counter, and the output - with the S-input of the trigger, the D-input of which is connected to the logic zero level, the C input is connected to the C input of the counter and connected to the output of a frequency divider with a variable division factor, the second input of which is connected to the output of the OR element, the second input which is connected to the input bus device, and the third - with the inverse trigger output and the second input element a match, the output of which is connected to the counting input of the counter, information inputs which, respectively, are connected to the bus of the dividing ratio code of the device, the first output of which is connected to the forward trigger output, the third divider input with variable dividing ratio is connected to the four-bit bus of the device. 2. The divider according to claim 1, of which is a frequency divider with a variable division factor containing the first and the second counters and the element 4-2И-OR-NOT, while the output of the frequency divider with a variable division factor, which is the second output bus of the device, is connected to the output of the second counter, R-input which is connected to the R input of the first counter and connected to the first input of a frequency divider with a variable division factor, the second input of which is connected to the C input of the first counter whose outputs respectively, are connected to the second inputs of four elements 2I, which are part of element 4-2I-OR-NOT, the first inputs of which are connected to the third input of a frequency divider with a variable coefficient dividing, connected respectively to the four-bit bus of the device, and the output of element 4-2 and-OR-NOT is connected to the C-input of the second counter. / FIG. 2 ff0