SU1171999A1 - Device for generating pulse sequence - Google Patents

Abstract

A DEVICE FOR THE FORMATION OF A PULSE SEQUENCE, containing a pulse generator, the output of which is connected to the counting input of a controlled frequency divider. A binary counter, characterized in that, in order to expand its functionality and increase its speed, a second controlled frequency divider, a second binary, a counter, a mode switching unit, the first and second delay elements, and the output of the first controlled frequency divider are additionally introduced into it connected to the counting input of the second controlled frequency divider, to the counting input of the first binary counter and through the first delay element to the installation input of the first controlled frequency splitter The bit inputs of which are connected to the bit outputs of the first binary counter, whose setup input is connected to the counting input of the second binary counter via the mode selector, to the output of the second controlled frequency divider (L directly and through the second delay element to the setup input of the second controlled frequency divider, the bit inputs of which are connected to the bit outputs of the second binary counter. (UD WITH CO

Description

S An exclusion refers to a pulse technique and can be used in radiolocation as a form of a body of coding impulses, as well as in automatic frequency tuning systems of oscillators with linear and quadratic frequency variation laws (respectively, with a square and cubic phase variation) . . . The purpose of the invention is to increase the speed of distribution and the expansion of functional capabilities due to the formation of pulses with different laws of changing the period. The drawing shows the structures on the electrical circuit of the device. A device for forming a pulse sequence contains a pulse generator 1, the first 2 second 3 controlled frequency dividers, the first A and the second 5 elements of the alternate, the first 6 and the second 7 double counters, the operating mode switching unit 8, and the generator is connected in series to the device 1 pulses, controlled dividers 2 and 3 frequencies and a binary counter 7, while the output of the controlled splitter 2 frequency is connected to the input of the binary counter 6 and through the delay element 4 with the second input of the controlled splitter 2 frequency, and output controlled frequency divider 3 is connected via block 8 to the second input of binary counter 6 and through delay element 5 to the second input of controlled frequency divider 3, as well as outputs of binary counters 6 and 7, respectively, to the other inputs of controlled frequency dividers 2 and 3. The device operates as follows. In the initial state, the controlled dividers 2 and 3 frequencies and binary counters 6 and 7 recorded the code O. The installation of these elements in the initial state can be performed by additional signals that are fed to their installation inputs (as in the drawing communications are not shown), Controlled, dividers 2 and 3 frequencies are made on the basis of a reverse binary counter operating in subtraction mode. The pulse generator 1 generates a sequence of 9 2 pulses with a period Tj, which are fed to the input of the controlled divider 2 frequencies. From the output of controlled frequency divider 2, the pulses arrive at the input of the second bit of binary counter 6, each time increasing the number code written in it by two units. In this case, in a binary counter 6, a sequence of even Numbers is formed. One time after the appearance of a pulse at the output of the controlled frequency divider 2 by a pulse from the output of the delay element 4, the code of the next even number is written to the controlled frequency divider 2. The output frequency of the pulses is determined by the formula 1b, x Fex / (K, x + O where F, FO, is the output and input clock OUT 6 to g is the input code of the frequency divider. Thus, at the output of the controlled frequency divider 2, a sequence of pulses is generated the linear law of the period change, in particular, the law of the period change: -1 pulses corresponds to a sequence of odd numbers. Similarly, pulses from the {controlled-divisor output 3 frequencies arrive at the input of the first digit of the binary counter 7, each time increasing the code written in it numbers on the unit. In this case, a binary sequence of numbers of a natural series is formed in binary counter 7. After the appearance of a pulse at the output of the controlled frequency divider, 3 a frequency pulse from the output of the delay element 5 records the code of the next number of the natural number in the control divisor 3 is frequency. Thus, the controlled divider 3 frequency linearly increases by one the number of the pulse from the output of the controlled divider 2 frequency passed to the output of the device. When pulses are formed in the device with a quadratic law of variation of the period, block 8 is closed. At the same time, each pulse from the output of the controlled frequency divider 3 sets the binary counter 6 to the initial state, i.e. writes the code of the number O into it. Thus, after 3. each output pulse, controlled frequency divider 2 forms a series of pulses, the follow-up period of which varies in proportion to a sequence of odd numbers (with a linear law of period change), starting with a value of 1, and controlled frequency divider 3 linearly increases the number of the output pulse divisible frequency 2, passed to the output of the device as a whole, In table. Figure 1 shows the formation of pulses with a quadratic law of variation of the period. When forming the impulses with a cubic locking change of the front by the proposed device, block 8 is open. At the same time, the controlled frequency divider 2 frequencies the sequence of pulses without returning to the initial state after each output pulse, and the 99 99 elements of the devices operate in a similar way. Table 2 shows the process of forming pulses with the cubic law of a period change. TabLo 1 and 2 in the fraction splitter indicate the code value after the next pulse from the pulse generator 1, and the denominator indicates the code value after the pulse delayed in elements 4 and 5 of the delay for time Cj, O is the state of the frequency divider, to which he passes from O after the impact of the next impulse. The next division codes for controllable dividers 2 and 3 frequencies are generated simultaneously and independently from each other. Therefore, the speed of the proposed device determines the generation time of the next division code for one controlled frequency divider. Table 1

ABOUT

b / o

D / 2

I

ABOUT

b / o 0/2

one

ABOUT

0/4

About 1 1 1

oh oh

2 2

2

one

About 2

2 2

2

2 2

four

Table 2

Claims (1)

A DEVICE FOR FORMING A PULSE SEQUENCE, containing a pulse generator, the output of which is connected to the counting input of a controlled frequency divider, A binary counter, characterized in that, in order to expand its functionality and increase speed, a second controlled frequency divider, a second binary counter unit switching operation modes, the first and second delay elements, the output of the first divider managed frequency ^f is connected to the counting input of the second controlled removable frequency divider, to the counting input of the first binary counter and through the first delay element to the installation input of the first controllable frequency divider, the bit inputs of which are connected to the discharge outputs of the first binary counter, the installation input of which is connected to the counting input of the second binary counter through the mode switching block, to the output of the second controlled frequency divider • directly and through the second delay element to the installation input of the second controlled frequency divider, ode whose outputs are connected to the second bit binary counter. with lyisms to Vedism10 1 1171999