SU1128390A1 - Pulse repetition frequency divider - Google Patents

Abstract

A DELETER OF FREQUENCY FOLLOWING THE PULSES, containing the shift register, the element OR, and the control element whose output is connected to the information input of the register. shift, in order to expand its functional capabilities by providing the possibility of generating output pulses, the duration is equal to half the period of clock pulses shifted relative to each other by the same amount, the first and second elements EXCLUDING OR are entered into it and a trigger, the counting input of which is connected to the output of the second element EXCLUSIVE OR, which is an odd bit of the shift register, and the output with the first input of the first element EXCLUSIVE OR, the second input of which Wow is connected to the bus clock pulse-. and the output is from the first input of the second element EXCLUSIVE OR, the output of which is connected to the clock input of the shift register, and the second input to the OUTPUT of the OR element, whose corresponding inputs are connected to the output, turns of all odd, except the last, bits of the register shift, and the outputs of all but the last bits of the shift register are connected to the corresponding inputs of the control element.

Description

The invention relates to a pulse technique and can be used in discrete information processing systems, for example, in control systems for generating a series of periodic control signals.

A device for synchronizing pulses is known, comprising three flip-flops, two coincidence elements, and a series of successively connected inverters and triggers, the number of which is selected depending on the number of output pulses which is. It is required to get on the output tires l and.

A disadvantage of this device is its limited functionality due to the impossibility of forming output pulses forming output pulses with a duration equal to half the period of clock pulses shifted relative to each other by half of their period. The closest to the invention in technical essence and the achieved result is a device containing a shift register, an OR element and the first NAND element, acting as a control element, the output of which is connected to the information input of the shift register, the clock input of which is connected to the bus bar pulses and the first inputs of the second NAND element and the element, OR, the second inputs of which are connected to the shift register register and the first input of the first NID element, the second input of which is connected to the M-digit shift register through an inverter to the third input element of the second OR and AND-NO element, whose outputs are connected respectively to first and second inputs of third AND-NO. At the input of the device, an output signal is generated, which represents a pulse with a frequency of 1.5; 2.5; 3.5, etc. times less than the frequency of the input pulses, while the duration of the output pulse is equal to the duration of the clock pulses G2}. A disadvantage of the known device also consists in limited functionality, since it does not provide for the formation of output pulses.

the duration of which is equal to half the period of clock pulses shifted one relative to the other by the same amount. .

The purpose of the invention is to expand the functionality of the capabilities of the divider by allowing the formation of output pulses, the duration of which is equal to half the period

clock pulses shifted relative to each other by the same amount.

The goal is achieved by the fact that the first and second elements EXCLUSIVE OR and the trigger, whose counting input is connected to the output of the second, are introduced into the pulse frequency divider containing the shift register, the OR element and the control element whose output is connected to the information input of the motor register 1. an EXCLUSIVE OR element, which is an odd bit of the shift register, and the output is at the first input of the first EXCLUSIVE OR element, the second input of which is connected to the clock bus, and the output is connected to the first input of the second ele EXCLUSIVE OR, whose output is connected to the clock input of the shift register, and the second input - to the output of the OR element, whose corresponding inputs are connected to the outputs of all odd, except the last, bits of the shift register, and the outputs of all, except the last, bits of the register the shift is connected to the corresponding inputs of the control element. The drawing shows the electrical structure of the device. The pulse frequency divider contains the shift register 1, the OR element 2 and the control element 3, the output of which is connected to the information input of the shift register 1, the first and second elements EXCLUSIVE OR 4 and 5 and the trigger 6, the counting input of which is connected to the output of the second element EXCLUSIVE OR 5, which is an odd bit of shift register 1, and the output is from the first input of the first element EXCLUSIVE OR 4, the second input of which is connected to the bus 7 clock pulses, and the output to the first input of the second element EXCLUSIVE OR 5, the output of which It is connected to the clock input of the shift register 1, and the second input to the output of the element OR 2, the corresponding inputs of which are connected to the outputs of all are odd: c, except for the last, register 1 bits. shift, and the outputs of all but the last bits of the shift register 1 are connected to the corresponding inputs of control element 3, the output of which is connected to the information input of register 1, the outputs of which bits are the corresponding output buses 8 of the device. A pulse frequency divider operates as follows. Consider the operation of the device using the example of dividing the pulse frequency with a division factor of 2.5. In this case, register 1 has five bits, and control element 3 is designed as a four-input element OR NOT, the number n of register bits is equal to twice the division factor. The initial state of the device is the presence of logic levels O at all outputs of register I and output of trigger 6. At this, logic levels O, coming from outputs of trigger 6 and element OR 2, allow the passage from bus 7 to the clock input of register 1 of pulses direct frequency through the elements of the TIPPLE OR 4 and 5, and from the output of element 3 - to the information input of register I receives the level of logic I. On the leading edge of the first so Ivogo pulse in the first discharge of register I is recorded logical 1 from the output of element 3, to register I code 10000 is set. At this output of element 3, a signal of logical O is set, and at the output of element OR 2, a signal of logical 1, which, arriving at the top input of the element EXTRA OR 5, causes an output signal input at its output. On such an input, register 1 sets the logical O. I level. On the rear-front of the first clock pulse, a single differential is formed at the clock input of register 1, which is shifted by one bit in register I, and recorded for the first logical O from the output of element 3. In the register, the code 01000 is set. At the output of the SHSh 2 element, a logical signal O is set, which removes the inversion signal from the input of the element EXCEPTING OR 5. At the clock input of register 1, a logical O level is set. On the leading edge of the second clock pulse, a single difference is formed at the clock input of register 1, which is followed by another shift of information in register 1 by one bit and the code 00100 is set in it. OR 2, a logical 1 signal is set, which at the output of the EXCLUSIVE element OR 5 causes the input signal to be inverted. At the clock speed of register 1, the logic level O is set. On the falling edge of the second clock pulse, a single difference is formed at the clock input of register 1, which is followed by another information shift by one bit in register 1, and the code 00010 is set. the output of the OR 2 element is set to a logical O signal, which removes an INvert signal from the input of the element EXCLUSIVE OR 5. At the clock input of register 1, a logical O level is set. On the leading edge of the third clock pulse, a unit differential is formed at the clock input of register 1, which is followed by another shift of information in register 1 by one bit, and the code 00001 is set. This output element 3 is set to a logical signal 1, trigger 6, switches to one state, the logical signal 1 from the output of which, arriving at the second input of element 4, on its input, inverts the input signal. At the clock input of register 1, a logical O is set. On the falling edge of the third clock pulse on the clock input of register 1, a single difference is formed, according to which another information shift occurs in register 1 by one bit, while it sets the code 10000, as at the information input of register 1 - the signal of logical 1 from the output of element 3. At the output of element 3, a logical signal O is set, and at the output of the element OR 2 - a logical signal, which, entering the second input of element 5, causes an investment at its output tirovanie input signal. At the clock input of the register f, the level of logic O is set.

Then, on each leading and falling edges of the clock pulses, information is shifted by one bit at the inverse input frequency from the output of the EXCLUSIVE OR 4 element. On the falling edge of the fifth clock pulse, trigger 6 switches to the zero state. The device is reset and all the processes are repeated.

Thus, for each leading and falling edges of clock pulses, information in register I shifts by one bit, while register 1 successively receives five stable states corresponding to codes 10,000,01000, 00,100,00010, 00001, then the device operation cycle repeated again. At the output buses 8, output pulses appear, the duration of which is equal to half the period of clock pulses shifted relative to each other by the same amount. At the same time, their repetition rate is 2.5 times less than the follow frequency of the clock pulses.

Similarly, the device works with any other fractional division factor: 1.5; 2.5; 3.5; 4.5, etc., generally equal to 1c N-0.5, where N is an integer.

Introduction to the frequency divider of the pulses of the first and second elements EXCEPTING IDNs and a trigger ensures the formation of output pulses with a frequency of 1.5; 2.5; 3.5, etc. times less than the frequency of the following clock pulses, the duration of which is equal to half the period of clock pulses shifted one relative to the other by half the period of clock pulses. As a result, the functionality of the pulse frequency divider and the scope of its application are expanded.

Claims (1)

(.54) PULSE FOLLOW-UP DIVISOR containing a shift register, an OR element, and a control whose output is connected to the register information input. a shift, which is due to the fact that, in order to expand its functional capabilities by providing the possibility of generating output pulses, the duration is equal to half the period of the clock pulses, shifted one relative to the other by the same amount, the first and second elements are EXCLUDED into it OR and trigger count input which Cpd nen with output of the second exclusive OR element _(being the odd shift register discharge, and an output to a first input of the first exclusive-OR gate, to whose second input unified with the bus clock momentum