JPH02223866A - Frequency-voltage converter - Google Patents

Abstract

PURPOSE:To obtain data being near a true variation of a frequency of a frequency signal with satisfactory responsiveness by latching a clock counting output signal of a counter at the end time point or the start time point of each period of the frequency signal, and comparing a clock counting output of an arbitrary time point from the counter and a latch output from a latch circuit. CONSTITUTION:To an input terminal 1 of a frequency - voltage converter, a frequency signal converted to a voltage is inputted, and by a waveform shaping circuit 2, an input signal is converted to a square wave and outputted. Also, from an oscillator 3, a higher clock than the frequency signal is generated, reset at every one period of the frequency signal from the circuit 2 by a counter 8, and a clock counting output from the counter 8 is latched by a latch 9 at the end time point or the start time point of each period of the frequency signal. Subsequently, a count output value of an arbitrary time point of the counter 8 and an output value of the latch 9 are inputted to a data synthesizing circuit 11 and compared, and by a result of its comparison, the respective latch output value or counter output value is selected and outputted, and brought to conversion processing by a data converting circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency-voltage converter for obtaining a voltage corresponding to the frequency of a frequency signal.

[Prior Art] A typical conventional frequency-to-voltage converter triggers a mono multivibrator at the leading edge of a pulse of a frequency signal to generate a pulse with a constant width, and then passes the resulting pulse train through a low-pass filter. It is configured to smooth (average).

[Problems to be Solved by the Invention] This type of conventional frequency-voltage converter has a drawback of poor followability, that is, poor response to frequency changes.

Furthermore, since the low-pass filter has a cutoff frequency, it has been impossible to perform frequency-voltage conversion in a low frequency range below the cutoff frequency.

Therefore, a first object of the present invention is to provide a frequency-voltage converter with good followability and responsiveness to frequency changes.

A second object of the present invention is to provide a frequency-voltage converter that can perform frequency-voltage conversion even in a low frequency region.

[Means for Solving the Problems] The present invention for achieving the first object described above includes an input terminal for inputting a frequency signal to be converted into a voltage, and a clock signal having a higher frequency than the frequency signal. a counter whose counting input terminal is connected to the clock signal generation circuit and whose reset terminal is associated with the input terminal so as to be reset every cycle of the frequency signal; a latch circuit that latches the clock count output obtained from the counter at the end or start point of each cycle of the frequency signal; a counter output value obtained from the counter at any point in time; and a latch output value obtained from the latch circuit. When the counter output value is smaller than the latch output value, the latch output value is selected and output, and when the counter output value is larger than the latch output value, the counter output value is selected and output. and a data conversion circuit that converts an output value corresponding to the period of the frequency signal obtained from the data synthesis circuit into a digital voltage value corresponding to the frequency. It is related to converters.

Furthermore, in order to achieve the second objective, it is desirable to configure the clock signal generation circuit as a variable clock signal generation circuit.

[Function] The counter according to the present invention outputs a value corresponding to the period of the frequency signal. Since the output of the counter changes every time a clock signal is input, it changes in the form of a triangular wave or a sawtooth wave. on the other hand,
The output of the latch circuit changes in the form of a staircase wave according to changes in the period of the frequency signal.

The output of the latch circuit includes period information, but since it is a staircase wave, it has poor followability and response to changes in the period.However, the larger of the latch output and the counter output must be selected and output. For example, a counter output that increases with time is placed between a low stage and a high stage of latch output, and the followability and responsiveness to cycle changes are improved.0 cycle T and frequency f are f = 1/T. Because of the relationship, it is possible to convert period T data into frequency data, ie, voltage V data, in a known manner.

[Embodiment] Next, a frequency-voltage converter according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

A waveform shaping circuit 2 is connected to the frequency signal input terminal 1 shown in FIG. The waveform shaping circuit 2 shapes the input signal into a rectangular wave and outputs a frequency signal shown in FIG. 2(B).

The oscillator 3 generates a clock of IHH2 which is sufficiently higher than the frequency signal.The frequency divider 4 connected to the oscillator 3 divides the output of the oscillator 3 into multiple stages and outputs the result. The multiplexer 5 selectively modulates the signals of the plurality of terminals a to h connected to the oscillator 3 and the frequency divider 4 and sends the signals to the output line 6 . Note that the clock signal obtained on the output line 6 also has a higher frequency than the frequency signal at the input terminal 1. The switch SW of the multiplexer 5 is automatically controlled by the control circuit 7.

The clock input terminal or counting input terminal CK of the counter 8 is connected to the output line 6 of the multiplexer 5, and the reset terminal R is connected to the waveform shaping circuit 2. counter 8
is a digital counter that generates a 16-bit output, and the leading edge (tl) of the frequency signal pulse shown in FIG.
, t2, t3, etc.), that is, at the end (beginning) of each period, and the clocks are counted again. FIG. 2(C) schematically (analog) shows the digital output of the counter 8.

As is clear from FIG. 2(C), the counter 8 measures one cycle of the frequency signal.

Upper 3 bits of counter 8 (MSB, 23B, 33B)
The output of is connected to the control circuit 7 of the multiplexer 5. The control circuit 7 sets the upper 3 bits of the counter 8 to [000
] to [0011, the output frequency of the multiplexer 5 is lowered by one step, and thereafter, the switch SW is controlled so that the frequency signal of the frequency divider 4 that is one step lower is selected every time the frequency increases by one digit. Therefore, the input clock frequency of the counter 8 changes as shown in FIG. 2(A).

The latch circuit 9 has 16 D flip-flops connected in parallel, and has 16 input terminals connected to the 16-bit output line 10 of the counter 7 and a clock input terminal connected to the waveform shaping circuit 2. It has a terminal CK. When the frequency signal pulse shown in FIG. 2(B) is input to the clock input terminal CK of the latch circuit 9, the output of the counter 8 is read in response to this leading edge (rising edge). Therefore, the latch circuit F! 89 holds the counter output (data indicating the cycle) of the frequency signal one cycle before the next cycle, and
) is sent to the Q output terminal. That is, the counter output data D1 at tl in FIG. 2(C) is held in the counter circuit 9.

The clock is input to the latch circuit 9 at time t2, but since the counter output is the same, the latch output does not change.At time t4, the counter output data has changed to D2, so the output of latch #19 is also D2. become.

The data synthesis circuit 11 includes a first data selection circuit 12 consisting of a latch connected to the counter output line 10 , a second data selection circuit 13 consisting of a latch connected to the latch circuit 9 , and a second data selection circuit 13 consisting of a latch connected to the counter output line 10 . Latch circuit 9
A data comparison circuit (comparator) 14 connected to the comparison port F! Data selection circuit 12.13 with @14 output
and a selection control circuit 15 for controlling. The comparison circuit 14 digitally compares the 16-bit counter output and the 16-bit latch output, and generates an output indicating the magnitude of both.The 0 selection control circuit 15 selects the first output when the counter output is larger than the latch output. The second data selection circuit 13 is controlled to turn on the counter output to the 16-bit common output line 16, and conversely, when the counter output is less than the latch output, the second data selection circuit 13 turns on the second data selection circuit 12 of the latch circuit 9. The output is sent to common output line 16. As a result, data schematically shown in FIG. 2(E) is obtained on the common output line 16. As is clear from the comparison of FIG. 2 (C), (D), and (E), 10~t1, t3~t4, t7
In the intervals from ~t8 to t9, the output of the counter 7 is sent to the common output line 16, and in the other intervals, the output of the latch circuit 9 is sent out. The data in Figure 2 (E) has better followability and responsiveness to the frequency and changes in the input signal than the latch output data in Figure 7 (D), that is, the current cycle even within one cycle. If it is determined that is longer than the previous period, the counter output is selected from that point on,
Data indicating the new cycle is obtained. As a result, the output of FIG. 2(E) has better response characteristics to the input frequency signal than the output of FIG. 2(D).

Furthermore, even during one cycle period from T2 to t4, when the counter output reaches a predetermined level, the input clock frequency of the counter 7 decreases from fl to fl, and the rising speed (slope) of the output data of the counter 7 is slow. At time t10 in FIG. 2, the clock frequency further decreases to f3 in response to the increase in the counter output. If the clock frequency is lowered in accordance with the increase in the output of the counter 7, it is possible to prevent the counter 7 from overflowing when the period of the input frequency signal is long, and it becomes possible to measure up to an extremely long period.

The data conversion circuit 17 is a circuit that converts periodic data given from the common output line 16 into voltage data, and RO
Consists of M. Various voltage data corresponding to various periodic data are written in advance in the ROM of this data conversion circuit 17, and the zero period T at which voltage data is read using the periodic data of the common output line 16 as an address signal is determined according to the following formula. It is converted into voltage V.

V=K(1/T) However, K is a constant. Since 1/T in the above equation is the frequency, a voltage (digital value) corresponding to the frequency can be obtained from the data conversion circuit 17.

The data (voltage) obtained from the data conversion circuit 17 is converted into an analog voltage value by a digital-to-analog converter (DAC>18).

The frequency-voltage converter of this embodiment has the following effects.

(1) Even if the frequency signal is in the middle of one cycle, if the cycle becomes longer (the frequency becomes lower), the counter value is output from that point on, so a value close to the true value can be obtained without waiting for one cycle. can be obtained.

(2) Unlike the conventional method, which forms pulses with a constant width based on the frequency signal and averages them with a low-pass filter,
A data converter consisting of ROM! Since the i'817 is used to obtain a digital voltage corresponding to the period, it is also possible to measure low frequencies (long periods).

(3) When the period of the frequency signal becomes longer, the frequency of the input clock of counter 7 automatically decreases.
R of the data conversion circuit 17.
A wide range of measurements can be performed while suppressing an increase in the capacity of the OM.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) Without configuring data converter #117 with ROM,
It may be configured with an arithmetic circuit that performs the arithmetic operation of V=K(1/T).

(2) The data obtained on the common output line 16 or the output data of the data converter N17 may be written to the storage device.

(3) Trailing edge of the frequency signal pulse shown in Figure 2 (B) (
The counter 7 is reset at the falling edge), and the latch circuit 9
It may also be configured to provide a clock to the

(4) A circuit for forming narrow pulses (trigger pulses) may be added to the output stage of the waveform shaping circuit 2, and if a rectangular wave is input, the waveform shaping circuit 2 can be omitted.

[Effects of the Invention] As described above, according to the present invention, data close to the true change in frequency of a frequency signal can be obtained with good responsiveness.

Further, according to claim 2, by changing the frequency of the input clock of the counter, frequency-voltage conversion in a low frequency region becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a frequency-voltage converter according to an embodiment of the present invention, and FIG. 2 is a diagram schematically showing the state of each part in FIG. 1. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Waveform shaping circuit, 3... Oscillator, 4... Frequency divider, 5... Multi-breather, 8...
...Counter, 11...Data synthesis circuit, 12...
First data selection circuit, 13... Second data selection circuit, 14... Comparison circuit, 15... Selection control circuit, 1
6... Common output line, 17... Data conversion circuit,
18...Digital-to-analog converter.

Claims (1)

[Claims] [1] An input terminal for inputting a frequency signal to be converted into a voltage, a clock signal generation circuit for generating a clock signal with a higher frequency than the frequency signal, and a counting input terminal connected to the clock signal. connected to the signal generation circuit,
a counter whose reset terminal is associated with said input terminal so as to be reset every period of said frequency signal; and a clock counting output obtained from said counter at the end or beginning of each period of said frequency signal. a latch circuit that latches, a counter output value obtained from the counter at an arbitrary point in time, and a latch output value obtained from the latch circuit,
A data synthesis circuit that selects and outputs the latch output value when the counter output value is smaller than the latch output value, and selects and outputs the counter output value when the counter output value is larger than the latch output value. and a data conversion circuit that converts an output value corresponding to the period of the frequency signal obtained from the data synthesis circuit into a digital voltage value corresponding to the frequency. [2] The clock signal generation circuit is a variable clock signal generation circuit, and includes: an oscillator; a frequency divider that divides the output of the oscillator to generate a plurality of frequency division outputs; and a control circuit that controls the multiplexer to reduce the frequency of the input clock of the counter in response to the output value of the counter exceeding a predetermined value. The frequency-voltage converter according to claim 1.