CN112910338A - Micro-step motor counting sequence circuit - Google Patents

Abstract

The application discloses a micro-step motor counting sequence circuit, which comprises an interpolation circuit and a counting sequence output circuit which are connected with each other; the interpolation circuit comprises a subdivision value calculation circuit and a counting decrement module which are connected with each other, and the counting decrement module is connected with the counting sequence output circuit; the subdivision value calculation circuit is used for obtaining an interpolation subdivision value according to the stepping signal, the clock signal and the micro-stepping subdivision signal; the counting and decrementing module is used for outputting an interpolated counting pulse signal by using the interpolated subdivision value and the microstep subdivision signal; count sequence output circuit for count according to count pulse signal, output count sequence, this application utilizes step signal, clock signal and microstep subdivision signal, interpolates step signal, carries out average division to a step signal for the count sequence is more level and smooth, lets follow-up sinusoidal waveform according to count sequence generation more level and smooth, and is no longer precipitous, makes step motor operation more steady.

Description

Micro-step motor counting sequence circuit

Technical Field

The invention relates to the field of automatic control, in particular to a micro-step motor counting sequence circuit.

Background

The stepped driving current is generally a sine-cosine curve, and the noise effect and stability are better when the curve is closer to the operation of the sine motor. In the conventional application, the higher the subdivision of the stepping motor is, the more stable the operation is, therefore, in the case that the stepping motor operates in the whole step, the half step, the 1/4 step or the 1/8 step, the current of the stepping motor is in a step shape compared with the case that the stepping motor operates in the 1/16 step, the 1/32 step, the 1/64 step or the 1/128 step, and the vibration and noise generated during the operation are obvious.

The reason is that the existing subdividable digital sine wave has steep output current waveform when low subdivision is performed, a meter reading counter changes rapidly, the noise of a motor is increased or the application is unstable, and the wear of devices is easily caused.

In order to stabilize the operation of the stepping motor even in low subdivision conditions such as whole, half, 1/4, 1/8 steps

For this reason, a counter sequence circuit that can operate smoothly even in the case of low subdivision of the stepping motor is required.

Disclosure of Invention

In view of the above, the present invention is directed to a micro-step motor counting sequence circuit, which reduces the instability of a step motor under low subdivision. The specific scheme is as follows:

a micro-step motor counting sequence circuit comprises an interpolation circuit and a counting sequence output circuit which are connected with each other;

the interpolation circuit comprises a subdivision value calculation circuit and a counting decrement module which are connected with each other, and the counting decrement module is connected with the counting sequence output circuit;

the subdivision value calculation circuit is used for obtaining an interpolation subdivision value according to the stepping signal, the clock signal and the micro-step subdivision signal;

the counting decrement module is used for outputting an interpolated counting pulse signal by utilizing the interpolated subdivision value and the micro-step subdivision signal;

and the counting sequence output circuit is used for counting according to the counting pulse signals and outputting a counting sequence.

Optionally, the subdivided value calculating circuit includes a measuring module and a dividing module connected to each other;

the measuring module is used for calculating how many clock signals exist in one stepping signal period according to the stepping signals and the clock signals, and outputting a calculation result unit stepping period to the division module;

and the division module is used for calculating the interpolation subdivision value according to the unit stepping period and the micro-step subdivision signal and outputting the interpolation subdivision value to the counting decrement module.

Optionally, the division module is specifically configured to calculate the interpolation component value by using an interpolation component value calculation formula according to the unit stepping period and the micro-step subdivision signal, and output the interpolation component value to the count decrementing module;

the interpolation detail value calculation formula is as follows: MICRO ═ MSTEP/2^ (MRES);

where MICRO represents the interpolated subdivision value, MSTEP represents the unit step period, and MRES represents the microstep subdivision signal.

Optionally, the device further comprises a non-interpolation circuit and a data selector;

the non-interpolation circuit and the interpolation circuit are respectively connected with the data selector, and the data selector is connected with the counting sequence output circuit;

the non-interpolation circuit is used for generating a subdivided jump count according to the stepping signal and the micro-stepping subdivision signal, and outputting the jump count to the data selector when the count sequence output circuit is not equal to the jump count;

and the data selector is used for selecting and outputting the jump count of the non-interpolation circuit or outputting the counting pulse signal of the interpolation circuit to the counting sequence output circuit according to an interpolation control signal.

Optionally, the non-interpolation circuit includes a first counter and a comparator connected to each other, and a comparison end of the comparator is connected to an output end of the count sequence output circuit;

the first counter is used for outputting the subdivided jump count to the comparator according to the stepping signal and the microstep subdivision signal;

and the comparator is used for comparing whether the count sequence output by the count sequence output circuit is equal to the jump count or not, if not, outputting the jump count to the data selector, and if so, not outputting the jump count to the data selector.

Optionally, the first counter is further configured to select forward counting or reverse counting according to the forward and reverse control signal, so as to control the stepping motor to rotate forward or reverse.

In the invention, the micro-step motor counting sequence circuit comprises an interpolation circuit and a counting sequence output circuit which are mutually connected; the interpolation circuit comprises a subdivision value calculation circuit and a counting decrement module which are connected with each other, and the counting decrement module is connected with the counting sequence output circuit; the subdivision value calculation circuit is used for obtaining an interpolation subdivision value according to the stepping signal, the clock signal and the micro-stepping subdivision signal; the counting and decrementing module is used for outputting an interpolated counting pulse signal by using the interpolated subdivision value and the microstep subdivision signal; and the counting sequence output circuit is used for counting according to the counting pulse signals and outputting a counting sequence.

The invention uses the step signal, the clock signal and the micro-step subdivision signal to interpolate the step signal and averagely divide one step signal, so that the counting sequence is smoother, the sine wave generated according to the counting sequence is smoother and not steeper, and the operation of the step motor is more stable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a micro-step motor counting sequence circuit structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another micro-step motor counting sequence circuit structure disclosed in the embodiment of the present invention;

FIG. 3 is a waveform diagram of an interpolation mode count sequence according to an embodiment of the present invention;

FIG. 4 is an enlarged view of a portion of the counting cycle of FIG. 3 according to an embodiment of the present invention;

FIG. 5 is an enlarged view of a portion of the counting cycle of FIG. 4 according to an embodiment of the present invention;

FIG. 6 is a waveform diagram of a non-interpolation mode counting sequence of the first counter according to an embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating a non-interpolation mode count sequence according to an embodiment of the present invention;

FIG. 8 is an enlarged view of a portion of the counting cycle of FIG. 7 according to an embodiment of the present invention;

fig. 9 is an enlarged view of a portion of the counting cycle of fig. 8 according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention discloses a micro-step motor counting sequence circuit, which comprises an interpolation circuit 1 and a counting sequence output circuit 2 which are connected with each other, wherein the interpolation circuit 1 is connected with the counting sequence output circuit 2;

the interpolation circuit 1 comprises a subdivision value calculation circuit 11 and a counting decrement module 12 which are connected with each other, and the counting decrement module 12 is connected with the counting sequence output circuit 2;

a fine value calculation circuit 11 for obtaining an interpolated fine value (MICRO) from the STEP Signal (STEP), the clock signal (CLK) and the microstep fine signal (MRES);

a count decrement module 12 for outputting an interpolated count pulse signal (FSTEP) using the interpolated subdivision value and the micro-step subdivision signal;

and a counting sequence output circuit 2 for counting according to the counting pulse signal and outputting a counting sequence.

Specifically, in order to make the stepping motor operate stably, a large step needs to be decomposed into a plurality of small steps so as to make the stepping motor operate rapidly and stably, and for this purpose, the original stepping signal is interpolated and divided into a plurality of rapid and continuous signals so that the stepping motor can operate according to a smoother sine wave signal; for this purpose, the sub-divided value calculating circuit 11 determines how many clock signals are in a step signal period according to the step signal and the clock signal, determines whether the step of the stepping motor is an integral step or an 1/2 step or a 1/4 step according to the micro-step sub-divided signal, and so on, determines how many clock signals are equal to one step of the micro-step motor, that is, an interpolated sub-divided value, according to the step mode of the stepping motor, and the count down module 12 outputs the interpolated count pulse signal according to the interpolated sub-divided value and the micro-step sub-divided signal, so that the count sequence output circuit 2 counts according to the frequency of the count pulse signal, thereby outputting a more smooth sine wave current according to the count sequence output by the subsequent control circuit.

Specifically, due to the effect of decrementing the count by the count decrementing module 12, the count sequence output circuit 2 performs corresponding average counting in one step, that is, the count sequence output circuit 2 can count to a jump smoothly. For example, when the full rate is 256 divisions, each step signal in the non-interpolation mode makes the count sequence output circuit 2 jump by 4 when 64 divisions are selected, and the length of 4 clock signals in the count sequence output circuit 2 of the embodiment of the present invention is equal to the length of one step signal, so that the count sequence output circuit 2 makes 4 times of transitions, and outputs a smooth sine wave current.

Note that the count sequence output circuit 2 corresponds to a counter.

Therefore, the embodiment of the invention interpolates the stepping signals by using the stepping signals, the clock signals and the micro-step subdivision signals, and averagely divides one stepping signal, so that the counting sequence is smoother, the sine waveform generated according to the counting sequence is smoother and not steeper, and the operation of the stepping motor is more stable.

It is understood that the counting sequence output by the micro-step motor counting sequence circuit of the embodiment of the invention can be used as the input of a sine wave reading table, and can also be used as other circuits which need different subdivision but have smooth counting.

Further, the subdivision value calculating circuit 11 may include a measuring module 111 and a dividing module 112 connected to each other;

the measuring module 111 is configured to calculate how many clock signals are in a step signal period according to the step signal and the clock signal, and output a calculation result unit step period to the division module 112;

the division module 112 is configured to calculate an interpolated fine value according to the unit step period and the micro-step fine-division signal, and output the interpolated fine value to the count decrementing module 12.

Specifically, the division module 112 is specifically configured to calculate an interpolation component value by using an interpolation component value calculation formula according to the unit stepping period and the micro-step subdivision signal, and output the interpolation component value to the count decrementing module 12;

the interpolation fine value calculation formula is: MICRO ═ MSTEP/2^ (MRES);

where MICRO denotes the interpolated subdivision value, MSTEP denotes the unit step period, and MRES denotes the microstep subdivision signal.

Specifically, the sub-divided value calculating circuit 11 measures the number of clocks of the input step, and shifts the sub-divided value bit to the right, i.e., divides the measured number of clocks by 2^ (sub-divided value).

Wherein, for the step signal, because the interpolation fine value is equal to the number of clocks in one step signal, MCRO ═ MICRO ═ FSTEP/2^ (MRES), and the maximum fine value is MRES ═ 1000 ^ 8. The interpolation fine value is at minimum 2^ (MRES) 2^8 ^ 256. The STEP signal STEP period is a minimum of 256 clock periods.

Further, the embodiment of the present invention also discloses a specific embodiment of an interpolation mode, for example, assuming 2 subdivision, one counting period needs 8 steps, each step is increased by 128, and one step period equals 12800 clock periods. The measurement module 111 is configured to calculate how many clock cycles a step cycle is equal to, and if a step cycle is equal to 12800 clock cycles, the output of the measurement module 111 is 12800, and the division module 112 divides the result of the measurement module 111 by 2^ (subdivision value), and if the current subdivision is 2 subdivision, the result of the division module 112 is 100, that is, the count down module 12 performs count down of 100, and sends a signal, that is, a count pulse signal to the data selector 4 every time the count down module 12 counts 0. The count pulse signal is input to the count sequence output circuit 2 and the count down block 12 through the data selector 4. After the counting pulse signal is inputted to the counting decrement module 12, the counting decrement module 12 restarts counting from 100 to 0 and then issues a new counting pulse signal, and so on. The counting pulse signal input to the counting sequence output circuit 2 will make the counting sequence output circuit 2 add 1, and as a result, the counting sequence output circuit 2 will add 1 every 100 clock cycles in the 2-subdivision interpolation mode, and after 12800 clock cycles add 128, it is just equal to the value that a step needs to be added in the 2-subdivision case. However, at this time, the count sequence output circuit 2 adds 1 to every 100 clock cycles, instead of adding 1 to every 1 clock cycle, so that 128 values are evenly distributed on the time axis, and as a result, the waveform is a smooth waveform as shown in fig. 3, wherein two count cycles are taken from fig. 3 and enlarged as shown in fig. 4, it can be seen that the count sequence output circuit 2 evenly distributes the changed values on the time axis, and then two count cycles are taken from fig. 4 and enlarged to obtain fig. 5, it can be seen that the count sequence output circuit 2 in fig. 5 evenly distributes the changed values on the time axis, so that the output waveform of the count sequence output circuit 2 is smoother.

The embodiment of the invention discloses a specific micro-step motor counting sequence circuit, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Referring to fig. 2, the non-interpolation circuit 1 and the data selector 4 are specifically included;

the non-interpolation circuit 3 and the interpolation circuit 1 are respectively connected with a data selector 4, and the data selector 4 is connected with the counting sequence output circuit 2;

the non-interpolation circuit 3 is used for generating a subdivided jump count according to the stepping signal and the micro-stepping subdivision signal, and outputting the jump count to the data selector 4 when the count sequence output circuit 2 is not equal to the jump count;

and a data selector 4 for selectively outputting the transition count of the non-interpolation circuit 3 or the count pulse signal of the interpolation circuit 1 to the count sequence output circuit 2 in accordance with the interpolation control signal (INTPOL).

Specifically, in order to increase the adaptation scene of the circuit, a non-interpolation circuit 3 and a data selector 4 are provided, and mode switching of the micro-step motor counting sequence circuit in an interpolation mode and a non-interpolation mode can be realized by using the data selector 4.

Specifically, the data selector 4 selects and outputs the signal of the non-interpolation circuit 3 or the signal of the interpolation circuit 1 to the calculation sequence output circuit according to the interpolation control signal, so that the mode of the counting sequence circuit is switched, when the data selector 4 outputs the signal of the non-interpolation circuit 3, the micro-step motor counting sequence circuit works in the non-interpolation mode, and when the data selector 4 outputs the signal of the interpolation circuit 1, the micro-step motor counting sequence circuit works in the interpolation mode.

It should be noted that, after the data selector 4 selects any mode, another circuit is not affected, the operation and output can continue, except that the output will only stay at the data selector 4, and will not reach the count sequence output circuit 2, e.g., when the data selector 4 selects the interpolation mode, the signal output from the interpolation circuit 1 is output to the count sequence output circuit 2 via the data selector 4, while the non-interpolation circuit 3 can continue to operate, outputting the transition count to the data selector 4, but the transition count does not reach the count sequence output circuit 2 through the data selector 4, in the non-interpolation mode, the interpolation circuit 1 can continue to operate, the counting pulse signal does not reach the counting sequence output circuit 2, of course, it may be set that after the data selector 4 selects one mode, the circuit corresponding to the other mode does not operate.

Specifically, the non-interpolation circuit 3 includes a first counter 31 and a comparator 32 connected to each other, and a comparison end of the comparator 32 is connected to an output end of the count sequence output circuit 2;

a first counter 31 for outputting the subdivided transition count to the comparator 32 according to the step signal and the micro-step subdivision signal;

and a comparator 32 for comparing whether the count sequence output from the count sequence output circuit 2 is equal to the transition count, and if not, outputting the transition count to the data selector 4, and if so, not outputting the transition count to the data selector 4.

Specifically, the count sequence output circuit 2 in the non-interpolation mode is controlled by the result of the comparator 32. The comparator 32 outputs a control signal during counting to control the count sequence output circuit 2 to perform count of addition or subtraction at the frequency of the clock until it is equal to the first counter 31. The counter then outputs a control signal that keeps the value of the count sequence output circuit 2 unchanged until a new STEP signal STEP comes in, causing the first counter 31 to change, the comparator 32 to change the result, the output control signal controls the count sequence output circuit 2 to count at the clock frequency until it equals the first counter 31, and then waits for the next STEP. And so on.

For example, 64, the first counter 31 transitions by 4 every step, and the count sequence output circuit 2 counts up to equal the first counter 31 very quickly in several clock cycles and then keeps until the next count arrives.

The result is that the count sequence output circuit 2 in the non-interpolation mode does not actually count in true jumps, but counts to the same as the first counter 31 in a short time in clock cycles after the first counter 31 makes a jump, and then waits for the next jump. It looks like a jump but is in fact a very fast count plus a hold time.

In addition, the first counter 31 is further configured to select a forward count or a reverse count according to the forward/reverse control signal (DIR) to control the stepping motor to rotate forward or reverse.

Further, the embodiment of the present invention also discloses a specific non-interpolation mode example, which is subdivided into 2: two step signals are required for the motor in one step, 4 steps for a stepping motor revolution, 8 step signals are required, and it is assumed that the period of one step signal equals 12800 clock signal periods. Referring to fig. 6, the output of the first counter 31 is a pattern corresponding to Z1, the first counter 31 counts one turn from 0 to 1024, which represents one turn of the motor, in the case of subdivision 2, the first counter 31 will add 128 steps at the time of each step signal, and count to 1024 after 8 steps, which we convert to 10-ary and form a broken line graph with time as the horizontal axis, forming a step-like counting sequence in fig. 6.

Specifically, at the very beginning of counting, the values of both counters are 0. When the first counter 31 comes a step, the first counter 31 directly increments 128 and holds, waiting for the next step to come and then increments 128. At this time, the count sequence output circuit 2 is still 0, the values of the two counters are not equal, and the comparator outputs a signal, that is, the transition count allows the count sequence output circuit 2 to start counting. At this time, the count sequence output circuit 2 does not add 128 directly, but adds 1 every clock Cycle (CLK), and becomes equal to the value of the first counter 31 after 128 clock cycles, and at this time, the values of the two counters are equal, and the comparator outputs transition count to make the count sequence output circuit 2 suspend counting. Since the step period is much larger than the clock CLK period, when the count sequence output circuit 2 becomes the same as the value of the first counter 31, the first counter 31 is far from the next step, and no transition occurs. When the second step comes, the first counter 31 adds 128 to 256, the two counters are not equal, the comparator 32 allows the counting sequence output circuit 2 to start counting until the same as the first counter 31, stops counting, waits for the next step again, and thus repeatedly obtains two counter waveforms shown in fig. 7, after amplifying one period in fig. 7, it can be seen that the counting change of the counting sequence output circuit 2 is slightly inclined, not the vertical change of directly adding 128, and then amplifies the change of the two steps in fig. 8, as shown in fig. 9, it can be seen that the first counter 31 directly jumps when the step comes, the counting sequence output circuit 2 becomes equal to the value of the first counter 31 after a certain change process, and then waits for the next step to come and repeat again. Although the count sequence output circuit 2 has a certain change process, the non-interpolation mode has a steep waveform and an interpolation mode because the clock period is too short and actually looks like a direct transition.

The waveform of the first counter 31 is Z1, and the waveform of the count sequence output circuit 2 is Z2.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (6)

1. A micro-step motor counting sequence circuit is characterized by comprising an interpolation circuit and a counting sequence output circuit which are connected with each other;

the interpolation circuit comprises a subdivision value calculation circuit and a counting decrement module which are connected with each other, and the counting decrement module is connected with the counting sequence output circuit;

the subdivision value calculation circuit is used for obtaining an interpolation subdivision value according to the stepping signal, the clock signal and the micro-step subdivision signal;

the counting decrement module is used for outputting an interpolated counting pulse signal by utilizing the interpolated subdivision value and the micro-step subdivision signal;

and the counting sequence output circuit is used for counting according to the counting pulse signals and outputting a counting sequence.

2. The micro-step motor counting sequence circuit of claim 1, wherein the sub-division value calculation circuit comprises a measurement module and a division module connected together;

the measuring module is used for calculating how many clock signals exist in one stepping signal period according to the stepping signals and the clock signals, and outputting a calculation result unit stepping period to the division module;

and the division module is used for calculating the interpolation subdivision value according to the unit stepping period and the micro-step subdivision signal and outputting the interpolation subdivision value to the counting decrement module.

3. The micro-step motor counting sequence circuit according to claim 2, wherein the division module is specifically configured to calculate the interpolated fine-step value by using an interpolated fine-step value calculation formula according to the unit stepping period and the micro-step fine-step signal, and output the interpolated fine-step value to the count decrementing module;

the interpolation detail value calculation formula is as follows: MICRO ═ MSTEP/2^ (MRES);

where MICRO represents the interpolated subdivision value, MSTEP represents the unit step period, and MRES represents the microstep subdivision signal.

4. The micro-step motor count sequence circuit of any of claims 1 to 3, further comprising a non-interpolation circuit and a data selector;

the non-interpolation circuit and the interpolation circuit are respectively connected with the data selector, and the data selector is connected with the counting sequence output circuit;

the non-interpolation circuit is used for generating a subdivided jump count according to the stepping signal and the micro-stepping subdivision signal, and outputting the jump count to the data selector when the count sequence output circuit is not equal to the jump count;

and the data selector is used for selecting and outputting the jump count of the non-interpolation circuit or outputting the counting pulse signal of the interpolation circuit to the counting sequence output circuit according to an interpolation control signal.

5. The micro-step motor count sequence circuit of claim 4, wherein said non-interpolation circuit comprises a first counter and a comparator connected, a comparison terminal of said comparator is connected to said count sequence output circuit output terminal;

the first counter is used for outputting the subdivided jump count to the comparator according to the stepping signal and the microstep subdivision signal;

and the comparator is used for comparing whether the count sequence output by the count sequence output circuit is equal to the jump count or not, if not, outputting the jump count to the data selector, and if so, not outputting the jump count to the data selector.

6. The micro-step motor counting sequence circuit of claim 5, wherein the first counter is further configured to select a forward count or a reverse count according to the forward and reverse control signals to control the forward or reverse rotation of the stepping motor.

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