JP2008182494A - Sampling rate converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sampling rate converter for performing sampling frequency conversion by always calculating a frequency ratio of a sampling frequency of input data and output data with high accuracy without a multiplication circuit. <P>SOLUTION: The sampling rate converter for converting a first sampling frequency into a second sampling frequency has a measurement adjusting part for generating a measurement adjustment signal on the basis of a ratio between the first sampling frequency and an input clock frequency being a frequency proportional to the first sampling frequency, a frequency ratio detecting part for counting the number of pulses of an input clock inputted during a predetermined measurement period by an increment amount per pulse determined on the basis of the measurement adjustment signal to determine a frequency ratio between the first sampling frequency and the second sampling frequency, and a sampling frequency converting part for performing sampling frequency conversion of input data on the basis of the frequency ratio. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to sampling rate converters, and more particularly to asynchronous sampling rate converters.

  Conventionally, a sampling rate converter is used as means for converting the sampling rate (sampling frequency) of input data into data having different sampling rates. Non-Patent Document 1 discloses an asynchronous sampling rate converter. The asynchronous sampling rate converter receives input data having a predetermined sampling rate and outputs output data having a predetermined sampling rate (see, for example, Non-Patent Document 1). Therefore, in the sampling rate conversion process (sampling frequency conversion process) performed by the asynchronous sampling rate converter, the ratio between the sampling rate of the input data that is actually input and the predetermined sampling rate of the output data It is important to calculate accurately.

The asynchronous sampling rate converter disclosed in Non-Patent Document 1 first measures the period T1 required to output 32 samples of data using an input clock having a frequency 128 times the sampling rate of the input data. To do. Here, this input clock is a clock signal input to the sampling rate converter separately from the input data. The sampling rate converter receives input data and an input clock that are sequentially input, repeats the measurement of the period T1 64 times in the same manner as described above, and measures 64 periods T1. Here, these 64 measured periods T1 are defined as T1 _{01 to} T1 ₆₄ , respectively. Next, the sampling rate converter, the total value of _T1 01 _{to T1 64} obtained in the measurement _T2 and _{(T2 = T1 01 + T1 02} + ··· + T1 63 + T1 64), the period _{T1 01} 64 times the value Compare with T3 (T3 = 64 × T1 ₀₁ ).

  Based on the comparison result, if the sampling rate converter determines that T2 and T3 are substantially equal, the sampling rate ratio is determined based on the value of T2, and T2 and T3 are substantially equal to each other. If it is determined that they are not equal, the ratio of the sampling rates is determined based on the value of T3.

  In a sampling rate converter using such a sampling frequency conversion method, if an input clock having a frequency 128 times the sampling rate of the input data cannot be received from the outside, the sampling rate converter itself does so. A clock signal having a proper frequency is generated. However, jitter may be included in this clock signal, and the measurement of the period T1 based on the clock signal including the jitter includes a large variation and becomes inaccurate. Therefore, in such a sampling rate converter, the comparison between period T2 and period T3 is naturally less accurate, even if T2 and T3 actually match substantially, Sometimes it was judged as a discrepancy. This was one factor that deteriorated the quality of the sampling frequency conversion.

  The sampling rate converter described in Patent Document 1 solves the above problem, and converts input data having a sampling rate fsin into output data having a sampling rate fsout.

This sampling rate converter includes a phase locked loop circuit that generates a multiplied signal having a frequency fsinx obtained by multiplying a sampling rate fsin of input data (multiplication operation), and a sampling rate of input data based on the multiplied signal. a frequency ratio detecting means for measuring a ratio fsd (frequency ratio) between the sampling rate fsout of the output data and the output data, determining the stability of the frequency ratio fsd, and generating a status flag stflg indicating that the frequency ratio is stable; A sampling rate conversion unit that performs sampling rate conversion based on the ratio fsd and the status flag stflg is provided. Further, the phase-locked loop circuit includes means for generating a completion flag finflg indicating that the multiplication operation has been completed, and the frequency ratio detecting means has a fluctuation range of the value of the frequency ratio fsd in a state of finflg. Stflg is generated by detecting that it falls within the range of a predetermined value that changes based on this. With such a configuration, the sampling rate converter described in Patent Document 1 can operate with high accuracy and stability even when jitter is included in the multiplied signal (input clock).
JP 2002-077063 A Radio Technology, AIA Publishing Co., Ltd., May 1994, p. 133-144

  As described above, the sampling rate converter described in Non-Patent Document 1 cannot perform sampling frequency conversion well when there is no input clock having a frequency that is 128 times the sampling rate of input data. Have

  In addition, the sampling rate converter described in Patent Document 1 includes a multiplier circuit and a configuration for reducing the influence of jitter caused by the multiplier circuit, so that the frequency is 128 times the sampling rate of input data. The sampling frequency can be converted even if the input clock having the signal s is not received. However, since the sampling rate converter requires a multiplication circuit, the circuit scale of the sampling rate converter must be relatively large. Also, if the sampling rate of the input data is shifted to the high frequency side, the sampling rate converter will be operated at a higher speed, but in this case, the frequency of the multiplication signal generated by the multiplication circuit will be higher. There is a problem in that unnecessary radiation and power consumption increase.

  In view of the above problems, the present invention provides a sampling rate converter that has a simple configuration and can accurately convert a sampling rate without causing unnecessary radiation and an increase in power consumption even when operated at high speed. The purpose is to do.

  In one aspect thereof, the present invention is an asynchronous sampling rate converter for converting input data having a first sampling frequency into output data having a second sampling frequency, the first sampling frequency A measurement adjustment unit that generates a measurement adjustment signal based on a ratio of the frequency and an input clock frequency that is proportional to the first sampling frequency; a measurement adjustment signal; an input clock having an input clock frequency; Receiving an output clock having a second sampling frequency, and counting the number of pulses of the input clock input during a predetermined measurement period by an increment per pulse determined based on the measurement adjustment signal; A frequency ratio detector for determining a frequency ratio between the sampling frequency of the second sampling frequency and the second sampling frequency, and sampling frequency conversion of the input data based on the frequency ratio Cormorant a sampling frequency converter, the sampling rate converter having.

  In one aspect of the present invention, a detection accuracy adjustment unit that generates a detection accuracy adjustment signal based on a ratio between the first sampling frequency and the input clock frequency is further included. It is preferable to change the length of the measurement period based on the accuracy adjustment signal.

  In one aspect of the present invention, it is preferable that the detection accuracy adjustment unit changes the detection accuracy adjustment signal according to the measurement adjustment signal.

  In one embodiment of the present invention, the length of the measurement period is preferably proportional to the increment amount.

  In one aspect of the present invention, the information processing apparatus further includes a status flag generation unit that generates a status flag indicating the stability of the frequency ratio, and the status flag generation unit includes the frequency ratio and the frequency measured before the frequency ratio. Preferably, the stability of the frequency ratio is determined based on the ratio and a status flag is generated, and the sampling frequency converter starts sampling frequency conversion of the input data based on the status flag state.

  The sampling rate converter according to the present invention does not require a multiplier circuit unlike the conventional sampling rate converter. Therefore, the circuit scale concerning a sampling rate converter can be made smaller than before.

  Further, the sampling rate converter according to the present invention has the sampling rate of the input data and the output data even when the frequency of the input clock is not as high as in the conventional case in comparison with the sampling rate of the input data. The frequency ratio to the sampling rate can be obtained in the same manner as in the conventional sampling rate converter. Therefore, the sampling rate converter according to the present invention can execute the sampling frequency conversion similar to the conventional one with a small circuit scale.

  Furthermore, the sampling rate converter according to the present invention performs the same sampling frequency conversion with the operation clock lower than the conventional one even when the sampling rate of the input data is shifted to the high frequency side. be able to. Therefore, the sampling rate converter according to the present invention can reduce unnecessary radiation and power consumption as compared with the conventional case.

  Hereinafter, an example of a sampling rate converter according to a preferred embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a sampling rate converter 1a according to the first embodiment of the present invention. The sampling rate converter 1a of the present embodiment is configured to count one pulse based on the ratio of the sampling rate of the input data and the frequency of the input clock in counting the number of pulses of the input clock input in the measurement of the frequency ratio. The increment to be added to the count value is changed with respect to the input clock.

  Sampling rate converter 1a is connected to controller 2a. The controller 2a is also connected to the sampled data output unit 3, and controls the sampling rate converter 1a and the sampled data output unit 3. Conversely, if there is a means for transmitting information related to the input clock output by the sampled data output unit 3 to the controller 2a, the controller 2a does not necessarily need to control the sampled data output unit 3.

  The first control signal is used for controlling the sampling data output device 3 by the controller 2a, and the second control signal is used for controlling the sampling rate converter 1a. Details of the information included in the first control signal and the second control signal will be described later. Here, the sampled data output device 3 may be, for example, a compact disc player (CD player). In this case, the input data to the sampling rate converter 1a is digital audio data. The sampled data output unit 3 outputs input data and an input clock to the sampling rate converter 1a via a digital signal interface (not shown).

  Further, the sampling rate converter 1a is connected to a clock generation unit (CLK) 11 that generates an output clock, and the clock generation unit (CLK) 11 sends a predetermined second sampling signal to the sampling rate converter 1a. Enter the rate (second sampling frequency).

  The sampling rate converter 1a receives input data having a first sampling rate (first sampling frequency), performs sampling frequency conversion (sampling frequency conversion), and outputs a predetermined second sampling rate (first sampling frequency). The ratio of the sampling frequency converter 5 that outputs output data having two sampling frequencies), the sampling rate of the input data (first sampling frequency), and the sampling rate of the output data (second sampling frequency) Frequency ratio detection data, and output a status flag indicating the stability / instability of the input state of the input data to the sampling frequency converter 5 based on the measured frequency ratio detection data And an output unit 10a.

  The frequency ratio detection data output unit 10a receives the second control signal and the input clock, outputs a measurement adjustment signal indicating an increment amount per pulse of the input clock, an input clock, an output clock, and A frequency ratio detection unit 15a that receives the measurement adjustment signal and outputs the frequency ratio detection data, and a status flag generation unit 30 that receives the frequency ratio detection data and generates and outputs a status flag.

  The frequency ratio detection unit 15a counts the pulses of the output clock, measures the frequency ratio between the input data and the output data, and the output clock counting unit 151a that notifies the start and period of the measurement period to the frequency ratio measurement unit 153. A frequency ratio measurement unit 153 that generates and outputs frequency ratio detection data is included.

  The status flag generation unit 30 buffers the frequency ratio detection data, and outputs the frequency ratio detection data as delayed frequency ratio detection data after a predetermined period, and the frequency ratio detection data and delay A data comparison unit 31 that compares the detected frequency ratio detection data and generates and outputs a status flag based on the comparison.

  The operation of the sampling rate converter 1a according to the first embodiment will be described below. In the description, the first sampling frequency (sampling rate of input data) is assumed to be fsin. The frequency of the input clock is fxin. The second sampling frequency (sampling rate of output data) is fsout, and the frequency of the output clock is fxout. fsout and fxout are preset values.

  The controller 2a outputs a second control signal including information on the first sampling frequency fsin and the input clock frequency fxin to the sampling rate converter 1a. Further, when there is means for transmitting information related to the input clock output from the sampling data output device 3 to the controller 2a, a second control signal including information related to the first sampling frequency fsin and the input clock frequency fxin is based on this information. Is output to the sampling rate converter 1a. This information may be information on the magnification of the input clock frequency fxin with respect to the first sampling frequency fsin.

  At the same time, the controller 2a instructs the sampling data output device 3 to output the input data at the first sampling frequency fsin and the input clock at the frequency fxin using the first control signal. Upon receiving an instruction from the controller 2a, the sampling data output unit 3 receives input data having a sampling rate fsin and an input clock having a frequency fxin (fxin = 32 × fsin) that is 32 times fsin, for example. Output to the converter 1a.

  On the contrary, when there is a means for transmitting information related to the input clock output by the sampled data output unit 3 to the controller 2a, the sampled data output unit 3 is provided with input data having a sampling rate fsin and, for example, 32 times fsin. An input clock having the frequency fxin (fxin = 32 × fsin) is output to the sampling rate converter 1a, and the controller 2a is instructed that the input clock is output at the frequency fxin.

  The measurement adjustment unit 13a can be configured by a decode circuit. The measurement adjustment unit 13a generates a measurement adjustment signal based on the received information regarding the first sampling frequency fsin and the input clock frequency fxin, and outputs the measurement adjustment signal to the frequency ratio detection unit 15a. The measurement adjustment signal is a signal indicating an increment amount to be counted up per pulse in counting the pulses of the input clock in the frequency ratio measuring unit 153. The frequency ratio measurement unit 153 counts the input clock with the increment amount indicated by the measurement adjustment signal. For example, when the measurement adjustment signal input to the frequency ratio measurement unit 153 indicates the increment amount “2”, the frequency ratio measurement unit 153 increases the count value by two for one input pulse. The measurement adjustment signal may be generated so as to have a different value depending on the ratio between the first sampling frequency fsin and the input clock frequency fxin. When the input clock frequency fxin has a frequency 32 times the first sampling frequency fsin, the measurement adjustment unit 13a calculates the ratio of “32” with respect to a predetermined reference value (for example, 64) and performs measurement. “2” is output as the adjustment signal to the frequency ratio measuring unit 153 of the frequency ratio detecting unit 15a. As described above, the measurement adjustment signal may be determined based on the ratio of the ratio (magnification) of the input clock frequency fxin to the first sampling frequency fsin and the reference value (here, 64). That is, the measurement adjustment unit 13a acquires information on the ratio of the input clock frequency fxin to the first sampling frequency fsin from the second control signal output from the controller 2a, and outputs a measurement adjustment signal based on the acquired information. The reference value may be an arbitrary value. For example, the reference value may be a generally desirable value as a magnification of the input clock frequency fxin with respect to the first sampling frequency fsin. At this time, the measurement adjustment signal is obtained by multiplying the frequency of the input clock with respect to the sampling frequency of the input data and the magnification of the actually used input clock frequency fxin with respect to the first sampling frequency fsin. A value indicating the ratio.

  The frequency ratio detection unit 15a uses the input clock, the output clock, and the measurement adjustment signal to input the sampling rate (first sampling frequency) of the input data input to the sampling rate converter 1a and the output data. A frequency ratio with the sampling rate (predetermined second sampling frequency) is obtained.

  Specifically, the frequency ratio detection unit 15a counts the number of pulses of the input clock that are input while a predetermined number of pulses of the output clock are input (measurement period), and uses the count value as the frequency ratio (measurement value). To do. For example, the number of pulses of the input clock input during a measurement period equal to a predetermined multiple (for example, 2048 times) of the output clock period (the reciprocal of fxout) is measured (counted).

  Each time the output clock counting unit 151a counts 2048 pulses of the output clock, the output clock counting unit 151a outputs to the frequency ratio measuring unit 153 the end of the measurement period, and the frequency ratio measuring unit 153 is included between the outputs. The number of pulses of the input clock is counted (counted up) while referring to the measurement adjustment signal. That is, at this time, the measurement adjustment signal is used as information for determining the increment amount per one input pulse in the count-up. For example, if the measurement adjustment signal is “2”, the frequency ratio measurement unit 153 sets a value equal to twice the number of pulses of the input clock actually received as the count value.

  The frequency ratio measuring unit 153 obtains the frequency ratio by obtaining the ratio between the count value and the number of pulses of the output clock received in the measured period (in this case, 2048).

  The frequency ratio thus obtained is sent to the sampling frequency conversion unit 5 and the status flag generation unit 30 as frequency ratio detection data N. The delay unit 33 of the status flag generation unit 30 holds a measurement value (frequency ratio detection data measured immediately before) in the immediately previous measurement period. The delay unit 33 can output the held data as frequency ratio detection data Nz delayed to the data comparison unit 31 at an appropriate timing.

  In the data comparison unit 31, the status flag generation unit 30 compares the frequency ratio detection data Nz received by the delay unit 33 in the previous measurement period with the frequency ratio detection data N. However, the measured timing of the delayed frequency ratio detection data Nz is not limited to the immediately preceding measurement period. You may use the frequency ratio detection data measured before 2 measurement periods or more as delayed frequency ratio detection data. When the difference between the two data is included in the predetermined range, the data comparison unit 31 determines that the sampling rate (first sampling frequency) of the input data being input is stable, and indicates a status indicating stability. The flag (for example, “1”) is output to the sampling frequency converter 5.

  The sampling frequency conversion unit 5 monitors the input status flag. When the status flag becomes “1” (stable), the sampling frequency conversion unit 5 starts sampling frequency conversion based on the separately input frequency ratio detection data N. Then, the input data is converted to output data having the second sampling frequency based on the frequency ratio detection data N, and is output.

  FIG. 2 is a block diagram showing details of the measurement adjustment unit 13. The measurement adjustment unit 13 receives a selector 131 that receives information about the first sampling frequency fsin and the input clock frequency fxin included in the second control signal and the input clock, and also relates to the first sampling frequency fsin and the input clock frequency fxin. A measurement fine adjustment unit 133 that receives information and an input clock, and an adder 135 that adds the outputs of the selector unit 131 and the measurement fine adjustment unit 133 are included. The selector unit 131 generates a measurement control main signal based on the second control signal and outputs it to the adder 135. The measurement fine adjustment unit 133 adds the measurement control main signal to the measurement control main signal when the measurement control main signal output from the selector unit 131 alone is not sufficient to generate the desired measurement control signal. The signal is output to the adder 135 in synchronization with the input clock. The selector unit 131 and the measurement fine adjustment unit 133 have a reference table for determining an output with respect to an input in order to generate a measurement control main signal and a measurement control sub signal, respectively.

  The configuration of the reference table included in each of the selector unit 131 and the measurement fine adjustment unit 133 will be described. The ratio between the reference value and the ratio of the input clock frequency fxin to the first sampling frequency fsin (this ratio is referred to as “reference value ratio”) is not necessarily an integer value. On the other hand, the increment amount is desirably an integer value. Therefore, the measurement adjustment unit 13 generates the measurement control signal by configuring the integer part of the reference value ratio with the measurement control main signal and configuring the fractional part of the reference value ratio with the measurement control subsignal. The reference table of the selector unit 131 associates the value of the integer part of the reference value ratio with the value of the measurement control main signal, and the selector unit 131 uses the value equal to the value of the integer part as the measurement control main signal. It outputs to 135. The measurement fine adjustment unit 133 can output a measurement control sub-signal whose value periodically changes in synchronization with the input clock. The reference table of the measurement fine adjustment unit 133 associates the value of the decimal part of the reference value ratio with the period of the measurement control sub-signal and the output pattern in each period. The output pattern is such that the ratio between the total value for one period of the measurement control sub-signal value and the number of pulses of the input clock input in that period is equal to the value of the fractional part of the reference value ratio. It is determined. And the measurement fine adjustment part 133 outputs the measurement control subsignal which has the obtained period and output pattern.

  A specific example is given and operation | movement of the measurement adjustment part 13 is demonstrated. The selector unit 131 and the measurement fine adjustment unit 133 refer to information on the first sampling frequency fsin and the input clock frequency fxin included in the second control signal, respectively. Note that the information input to the selector unit 131 and the measurement fine adjustment unit 133 may include information on the ratio between the input clock frequency fxin and the first sampling frequency fsin. By referring to this information, for example, it is assumed that the input clock frequency fxin is 8 times the first sampling frequency fsin. At this time, the ratio to the reference value is “8.0”. The selector 131 refers to the reference table and determines the measurement control main signal corresponding to the integer part “8” of “8.0”. The measurement fine adjustment unit 133 also refers to another reference table and determines a measurement control sub-signal corresponding to the decimal part “0” of “8.0”. At this time, the measurement control sub-signal is always 0. In this case, compared with the case where the input clock frequency is 64 times the first sampling frequency, the number of pulses of the input clock included in the same period is 1/8. Therefore, the selector 131 and the measurement fine adjustment unit 133 refer to the reference table and increment the count value so that the count value always increases by 8 each time one input clock pulse is input to the frequency ratio measurement unit 153. A measurement adjustment main signal and a measurement adjustment sub-signal constituting the measurement adjustment signal indicating the quantity “8” are respectively output.

  The selector 131 outputs the value 8 to the adder 135 as a measurement adjustment main signal, and the measurement fine adjustment unit 133 always outputs the value 0 to the adder 135 as a measurement control sub-signal. Therefore, the adder 135 always outputs the value 8 as the measurement adjustment signal. The frequency ratio detection unit 15a receives the measurement adjustment signal of value 8 and counts up by 8 for each pulse of the input clock.

  Further, for example, it is assumed that the frequency fxin of the input clock is found to be 48 times the first sampling frequency fsin by the above reference. At this time, the ratio to the reference value is “1.33 (4/3)”. The selector 131 refers to the reference table, and determines the measurement control main signal corresponding to the integer part “1” of “1.33 (4/3)”. The measurement fine adjustment unit 133 also refers to another reference table and determines a measurement control sub-signal corresponding to the decimal part “0.33 (1/3)” of “1.33 (4/3)”. . At this time, the measurement control sub-signal is output in an output pattern that repeats 0 and 1 (0, 1, 0, 0, 1, 0,...) In synchronization with the cycle of the input clock. Is done. In this case, compared with the case where the input clock frequency is 64 times the first sampling frequency, the number of pulses of the input clock included in the same period is 3/4. In this case, the selector 131 and the measurement fine adjustment unit 133 refer to the reference table, and the count value increases by 1.33 (4/3) every time one pulse of the input clock is input to the frequency ratio measurement unit 153. As described above, it is desirable to output the measurement adjustment main signal and the measurement adjustment sub-signal that constitute the measurement adjustment signal. However, the increment amount is preferably an integer value. Therefore, the selector 131 and the measurement fine adjustment unit 133 count the pulses input in a certain input clock cycle by the increment amount “1”, and the pulses input in the next input clock cycle The pulses input in the next input clock cycle as counted by “2” are incremented by “1” in synchronization with the cycle of the input clock so as to be counted by increment amount “2”. And “2” are (1, 2, 1, 1, 2, 1,...), The measurement adjustment main signal and the measurement adjustment sub-signal are respectively output. In this way, for example, when 48 input clock pulses are input, the count value can be set to “64”.

  The frequency ratio detector 15a receives the measurement adjustment signal of value 1, counts up by one for each pulse of the input clock, and receives the measurement adjustment signal indicating value 2 when receiving the next input clock pulse. In response, each input clock pulse counts up by two.

  In this way, the frequency ratio detection unit 15a measures the frequency ratio by changing the count-up amount (increment amount) for one pulse of the input clock based on the measurement adjustment signal. Therefore, even when the magnification of the input clock frequency fxin with respect to the first sampling frequency fsin is different from a general magnification (for example, 64 times), the value measured (counted up) in a certain period is The value (measured value) counted up using the general magnification is substantially the same.

  The sampling frequency converter 5 performs sampling frequency conversion based on the frequency ratio detection data N detected by the frequency ratio detector 15a. When the measurement period (a period of 2048 times the period of the output clock (reciprocal of the frequency fxout) in the above example) is constant, the magnification of the input clock frequency fxin with respect to the first sampling frequency fsin changes. The value of the frequency ratio detection data N changes greatly, and sampling frequency conversion is performed based on a frequency ratio different from the frequency ratio between the sampling rate of the input data actually input and the sampling rate of the output data. As a result, sampling frequency conversion cannot be performed correctly. Therefore, the frequency ratio detector 15a changes the amount of count-up per pulse of the input clock based on the second control signal output from the measurement adjuster 13a, and quickly changes the frequency ratio without changing the measurement period. To achieve accurate sampling frequency conversion.

  Accordingly, in the sampling rate converter 1a according to the first embodiment of the present invention, the magnification of the input clock frequency fxin with respect to the first sampling frequency fsin is a desirable magnification that has been generally used (for example, 64 times). Even if it is lower than that, it is possible to accurately measure the frequency ratio without using the multiplier circuit and to accurately perform the sampling frequency conversion.

  The sampling rate converter 1a performs frequency ratio detection accurately and quickly without having a multiplier circuit even when the magnification of the input clock frequency with respect to the first sampling frequency can take various values. High sampling frequency conversion is realized.

  In a conventional sampling rate converter, when converting input data having a sampling rate of 44.1 kHz to output data having a sampling rate of 48 kHz, for example, an input clock having a frequency of (44.1 × 64) kHz. When sampling frequency conversion is performed using the above and the input data is converted at sampling speed, it is necessary to perform sampling frequency conversion using an input clock having a frequency of (44.1 × 64 × 2) kHz. there were. For this reason, conventionally, there have been problems such as unnecessary radiation and increased power consumption. However, the sampling rate converter 1a does not need to shift the frequency of the input clock to the high frequency side even when performing the sampling frequency conversion at the double speed as described above. Reduction is possible.

  Further, since the sampling rate converter 1a does not require a multiplication circuit, the circuit area can be made smaller than that of a conventional sampling rate converter that requires a multiplication circuit.

(Second Embodiment)
FIG. 3 is a block diagram showing the configuration of the sampling rate converter 1b according to the second embodiment of the present invention. The sampling rate converter 1b of the present embodiment can change the measurement period for detecting the frequency ratio based on an input signal from the outside. For example, the frequency ratio can be measured by changing the measurement period to a measurement period different from the standard measurement period based on an input signal having information regarding the ratio between the sampling rate of the input data and the frequency of the input clock. Constituent elements similar to those of the sampling rate converter 1a shown in FIG. In addition, detailed description of such components will be omitted in the following description.

  Sampling rate converter 1b is connected to controller 2b. The controller 2b outputs an accuracy adjustment signal to the detection accuracy adjustment unit 17a newly added in the second embodiment. The accuracy adjustment signal may include information for changing the measurement period. The detection accuracy adjustment unit 17a generates a detection accuracy adjustment signal based on the received accuracy adjustment signal, and outputs the detection accuracy adjustment signal to the output clock counting unit 151b. When counting the pulses of the output clock, the output clock counter 151b adjusts the output interval (measurement period) indicating the end of the measurement period based on the received detection accuracy adjustment signal.

  The operation of the sampling rate converter 1b according to the second embodiment will be described below.

  The controller 2b outputs a second control signal including information on the first sampling frequency fsin and the input clock frequency fxin to the sampling rate converter 1a.

  At the same time, the controller 2a uses the first control signal to instruct the sampling data output device 3 to output the input data at the first sampling frequency fsin and the input clock at the frequency fxin. On the contrary, when there is means for transmitting information related to the input clock output from the sampled data output unit 3 to the controller 2a, the controller 2b does not necessarily need to control the sampled data output unit 3, and the sampled data output unit 3 Outputs to the sampling rate converter 1b input data having a sampling rate fsin and an input clock having a frequency fxin (fxin = 32 × fsin) 32 times fsin, for example, and the input clock at the frequency fxin. Is output to the controller 2a.

  As an example, it is assumed that the input clock frequency fxin is 32 times (fxin = 32 × fsin) with respect to the first sampling frequency fsin. At this time, the measurement adjustment unit 13a outputs the value 2 as a measurement adjustment signal to the frequency ratio detection unit 15b by referring to the reference table.

  The detection accuracy adjustment unit 17a can be configured by a decode circuit. The detection accuracy adjustment unit 17a has a reference table for determining an output with respect to an input, and outputs a detection accuracy adjustment signal to the output clock counting unit 151a based on the received accuracy adjustment signal. The accuracy adjustment signal input to the detection accuracy adjustment unit 17a is a signal for adjusting the length of the measurement period of one frequency ratio measurement. For example, if the standard measurement period is 2048 times the output clock period as in the first embodiment, the measurement period should be three times, that is, a period corresponding to 6144 times the output clock period. For example, the controller 2b may output the value 3 to the detection accuracy adjustment unit 17a as an accuracy adjustment signal.

  Then, the detection accuracy adjustment unit 17a outputs a detection accuracy adjustment signal for changing the measurement period to the output clock counting unit 151a based on the accuracy adjustment signal. The detection accuracy adjustment signal may be, for example, a binary signal having high (H) and low (L). For example, the detection accuracy adjustment unit 17a that receives the value 3 as the accuracy adjustment signal refers to the reference table, and synchronizes with the output clock as the detection accuracy adjustment signal once in one cycle of the output clock. Outputs a value (for example, high). The detection accuracy adjustment signal may also be input to the frequency ratio detection unit 153 via the output clock counting unit 151a. Each time the output clock counting unit 151a counts 2048 detection accuracy adjustment signals, the frequency ratio measuring unit 153 outputs to the frequency ratio measuring unit 153 the end of the measurement period, so that the measurement period is 3 times the standard measurement period. Doubled to a period.

  The frequency ratio detector 15b uses the input clock, the output clock, the measurement adjustment signal, and the detection accuracy adjustment signal to sample the input data that is actually input to the sampling rate converter 1a (the first sampling rate). The ratio of one sampling frequency) to a predetermined sampling rate (second sampling frequency) of the output data is obtained.

  Specifically, the frequency ratio detection unit 15b has a period equal to (standard measurement period) × (value indicated by the detection accuracy adjustment signal), (for example, a period three times 2048 times the period of the output clock). The number of pulses of the existing input clock will be measured. When the output clock counting unit 151a counts 2048 detection accuracy adjustment signals, the output clock counting unit 151a outputs to the frequency ratio measurement unit 153 an output indicating the end of the measurement period. The frequency ratio measuring unit 153 counts (counts up) the number of pulses for the input clock input during the period while referring to the measurement adjustment signal and changing the increment amount as necessary.

  The frequency ratio is obtained by obtaining the ratio between the counted value of the counted number of pulses of the input clock and the number of pulses of the output clock received during the measurement period (in this case, 6144). The number of pulses of the output clock included in the measurement period can be determined based on the detection accuracy adjustment signal.

  Thus, the frequency ratio detection unit 15b can change the period required for one measurement based on the detection accuracy adjustment signal output from the detection accuracy adjustment unit 17a. By increasing the measurement period, the measurement accuracy can be improved. In particular, when the value of the measurement adjustment signal is large, it is possible to prevent a decrease in the accuracy of frequency ratio detection by lengthening the measurement period.

  The frequency ratio obtained in this way is sent to the status flag generation unit 30 and the sampling frequency conversion unit 5 as frequency ratio detection data N. Subsequent operations may be the same as those in the first embodiment, and thus description thereof is omitted here.

  FIG. 4 is a block diagram showing details of the detection accuracy adjustment unit 17. The detection accuracy adjustment unit 17 includes a detection accuracy adjustment signal generation unit 171 that receives the accuracy adjustment signal and the output clock, a detection accuracy adjustment signal fine adjustment unit 173 that similarly receives the accuracy adjustment signal and the output clock, and a detection accuracy adjustment signal generation unit 171. And an adder 175 that adds the outputs of the detection accuracy adjustment signal fine adjustment unit 173. The detection accuracy adjustment signal generation unit 171 includes a reference table for determining an output for the input, generates a detection accuracy adjustment main signal based on the accuracy adjustment signal, and outputs the detection accuracy adjustment main signal to the adder 175 in synchronization with the output clock. The detection accuracy adjustment signal fine adjustment unit 173 also includes a reference table for determining an output with respect to the input, and the detection accuracy adjustment signal cannot be generated satisfactorily only with the detection accuracy adjustment main signal output from the detection accuracy adjustment signal generation unit 171. In this case, the detection accuracy adjustment sub-signal is output to the adder 175 in synchronization with the output clock so as to be added to the detection accuracy adjustment main signal to generate a desired detection accuracy adjustment signal.

  The configuration of the reference table included in each of the detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 will be described. The magnification of the measurement period changed with respect to the standard measurement period indicated by the accuracy adjustment signal received by the detection accuracy adjustment unit 17 (this magnification is referred to as “versus standard measurement period magnification”) is not necessarily an integer value. . The detection accuracy adjustment signal is a binary signal of high and low. Therefore, the detection accuracy adjustment unit 17 uses the detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 as the detection accuracy adjustment main signal and the detection accuracy adjustment sub-signal in the output pattern corresponding to the standard measurement period magnification. Configure and add both signals to generate a measurement control signal. The reference table associates the magnification with respect to the standard measurement period with the output pattern of the detection accuracy adjustment signal. This output pattern is determined so that the ratio between the number of pulses of the output clock and the number of highs of the detection accuracy adjustment signal is equal to the value of the standard measurement period magnification. Based on the determined output pattern, the detection accuracy adjustment main signal and the detection accuracy adjustment subsignal are refined and output to the adder 135 in synchronization with the output clock. As a result, the ratio of the high number of detection accuracy adjustment signals to the number of pulses of the output clock within a certain period is equal to the value of the standard measurement period magnification.

  The operation of the detection accuracy adjustment unit 17 will be described with a specific example. Each of the detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 refers to the accuracy adjustment signal. By reference, for example, it is assumed that the accuracy adjustment signal is found to indicate that the measurement period is three times the standard measurement period. The detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 refer to the reference table to obtain an output pattern corresponding to “3.0 times”. In this case, the detection accuracy adjustment signal generation unit 171 outputs high to the adder 175 as a detection accuracy adjustment main signal once every three cycles of the output clock in synchronization with the output clock. In this case, the detection accuracy adjustment signal fine adjustment unit 173 always outputs low to the adder 135 as a detection accuracy adjustment sub-signal. Therefore, the detection accuracy adjustment signal is output as a signal that goes high once every three output clock cycles. The output clock counting unit 151a counts high included in the detection accuracy adjustment signal, and when the count value reaches a predetermined value (for example, 2048), outputs to the frequency ratio measuring unit 153 that indicates the end of the measurement period. Therefore, the measurement period is three times as long as the standard measurement period.

  Further, for example, a case will be described in which the accuracy adjustment signal indicates that the measurement period is 1.5 times the standard measurement period. Each of the detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 refers to the accuracy adjustment signal. By reference, it is assumed that the accuracy adjustment signal is found to indicate that the measurement period is 1.5 times the standard measurement period. The detection accuracy adjustment signal generation unit 171 and the detection accuracy adjustment signal fine adjustment unit 173 refer to the reference table and obtain a signal pattern corresponding to “1.5 times”. In this case, the detection accuracy adjustment signal generation unit 171 outputs high to the adder 175 as a detection accuracy adjustment main signal once every three cycles of the output clock in synchronization with the output clock. In this case, the detection accuracy adjustment signal fine adjustment unit 173 outputs “high” as a detection accuracy adjustment sub-signal to the adder 175 once every three cycles of the output clock at a timing different from that of the detection accuracy adjustment signal generation unit 171. Therefore, the detection accuracy adjustment signal is output as a signal that goes high twice every three output clock cycles. Therefore, the output clock counter 151a counts twice every three cycles of the output clock. Therefore, the measurement period is extended to 1.5 times the standard measurement period.

  Here, data output from the frequency ratio detector 15b will be considered. It is assumed that the measurement adjustment signal is always 2 in one measurement period. In this case, the frequency ratio detection unit 15b counts up two by two each time an input clock pulse is received, and outputs the counted up value (measured value) as frequency ratio detection data N. Then, the step size of the difference between the frequency ratio detection data N and the delayed frequency ratio detection data Nz is doubled as compared with the case where the measurement adjustment signal is always 1. Therefore, the detection accuracy adjustment unit 17a is delayed by making the measurement period longer than the standard measurement period and dividing the number of input pulses counted up based on the magnification to be increased to obtain the frequency ratio detection data N. The step size of the difference from the frequency ratio detection data Nz is reduced. This has the effect of making the determination of the frequency ratio and the stability / instability of the frequency ratio more accurate.

  Therefore, the sampling rate converter 1b according to the second embodiment of the present invention improves the accuracy of the frequency ratio measurement as compared with the case where the frequency ratio is detected in a fixedly determined measurement period.

(Third embodiment)
FIG. 5 is a block diagram showing a configuration of a sampling rate converter 1c according to the third embodiment of the present invention. The sampling rate converter 1c of this embodiment can change the measurement period based on the ratio of the input clock frequency fxin to the first sampling frequency fsin. The sampling rate converter 1c can determine the extent of extension of the measurement period according to the increment amount with respect to one pulse of the input clock. Constituent elements similar to those of the sampling rate converter 1a shown in FIG. 1 or the sampling rate converter 1b shown in FIG. 3 are denoted by the same reference numerals. In addition, detailed description of such components will be omitted in the following description.

  Sampling rate converter 1b is connected to controller 2a. The controller 2a also outputs the second control signal to the detection accuracy adjustment unit 17b. The detection accuracy adjustment unit 17a generates a detection accuracy adjustment signal based on the received second control signal, and outputs the detection accuracy adjustment signal to the output clock counting unit 151b. As in the second embodiment, the output clock counter 151b adjusts the output interval (measurement period) indicating the end of the measurement period based on the received detection accuracy adjustment signal when counting the pulses of the output clock. To do.

  The operation of the sampling rate converter 1c according to the third embodiment will be described below.

  The controller 2a outputs a second control signal including information on the first sampling frequency fsin and the input clock frequency fxin to the sampling rate converter 1c.

  At the same time, the controller 2a uses the first control signal to instruct the sampling data output device 3 to output the input data at the first sampling frequency fsin and the input clock at the frequency fxin. On the contrary, when there is means for transmitting information related to the input clock output from the sampled data output unit 3 to the controller 2a, the controller 2b does not necessarily need to control the sampled data output unit 3, and the sampled data output unit 3 Outputs to the sampling rate converter 1b input data having a sampling rate fsin and an input clock having a frequency fxin (fxin = 32 × fsin) that is 32 times fsin, for example, and the input clock at the frequency fxin. Is output to the controller 2a.

  Also in the description of the third embodiment, as in the description of the first and second embodiments, as an example, the frequency fxin of the input clock is 32 times the first sampling frequency fsin (fxin = 32 × fsin). ). At this time, like the first and second embodiments, the measurement adjustment unit 13a outputs the value 2 as a measurement adjustment signal to the frequency ratio detection unit 15b.

  The second control signal input to the detection accuracy adjustment unit 17b may be the same signal as the signal input to the measurement adjustment unit 13a. The detection accuracy adjustment unit 17b can adjust the length of the measurement period in which the number of pulses of the input clock is counted based on the information of the first sampling frequency fsin and the input clock frequency fxin. This information only needs to include at least the ratio of the input clock frequency fxin to the first sampling frequency fsin. At this time, the detection accuracy adjustment unit 17b generates and outputs a detection accuracy adjustment signal including high once every two cycles of the output clock so that the measurement period is twice the standard measurement period.

  The frequency ratio detection unit 15b counts for each pulse of the input clock while counting up with an increment amount of 2 while doubling the standard measurement period (a period corresponding to 2048 × 2 times the cycle of the output clock). The frequency ratio detection data N is determined based on the count-up.

  As described above, the detection accuracy adjustment unit 17b, like the measurement adjustment unit 13a, inputs the input pulse indicated by the measurement adjustment signal based on the information regarding the input clock frequency fxin and the first sampling frequency fsin included in the second control signal. A detection accuracy adjustment signal for extending the measurement period so as to be proportional to the increment amount per one is generated and output. For example, when the measurement adjustment signal “2” is output so that 32 input pulses are counted as 64, the detection accuracy adjustment signal is output so that the measurement period is twice as long as the standard measurement period. The Thus, the measurement period can be changed according to the increment amount. The relationship between the increment amount and the measurement period may be linear (proportional relationship) or may be a secondary or higher relationship. Alternatively, it may be a stepped shape determined with reference to a table. The operation of the detection accuracy adjustment unit 17b can be changed in conjunction with the operation of the measurement adjustment unit 13a, and an optimal measurement period can be set according to the increment amount per pulse of the input pulse count-up.

  When the increment amount of the count-up per input clock pulse is 2, the measurement period may be set to twice the standard measurement period. By doing so, the step size of the difference between the frequency ratio detection data N and the delayed frequency ratio detection data Nz is approximately the same as when incrementing by one each time a pulse of the input clock is received. Can be.

  Alternatively, if the increment amount alternates between 1 and 2 each time an input clock pulse is input, the measurement period can be set to 1.5 times the standard measurement period. Good. Similarly, in this case, the step size of the difference between the frequency ratio detection data N and the delayed frequency ratio detection data Nz is the same as that when the input clock pulse is incremented by one. Can be about.

  The sampling rate converter 1c according to the third embodiment can automatically optimize the measurement period for determining one frequency ratio detection data N according to the frequency fxin of the input clock. Even in the case of frequency, the frequency ratio can be measured with sufficient accuracy. Also in the third embodiment, it is possible to set the measurement period without providing a direct correlation with the increment amount.

(Modification of the third embodiment)
FIG. 6 is a block diagram showing a configuration of a sampling rate converter 1d according to a modification of the third embodiment. In the sampling rate converter 1d, the measurement adjustment unit 13a generates an accuracy adjustment signal and outputs it to the detection accuracy adjustment unit 17c. Components similar to those of the sampling rate converter 1a shown in FIG. 1, the sampling rate converter 1b shown in FIG. 3, or the sampling rate converter 1c shown in FIG. Yes. In addition, detailed description of such components will be omitted in the following description.

  The controller 2a outputs a second control signal to the measurement adjustment unit 13a. The sampling rate converter 1d does not output the second control signal to the detection accuracy adjustment unit 17b, unlike the sampling rate converter 1c shown in FIG. Instead, the measurement adjustment unit 13a that has received the second control signal generates a signal equivalent to the accuracy adjustment signal output from the controller 2b in the sampling rate converter 1b shown in FIG. 3 to the detection accuracy adjustment unit 17c. Output. Alternatively, the measurement adjustment unit 13a may directly pass the received second control signal and output it to the detection accuracy adjustment unit 17c.

  With this configuration, in the sampling rate converter 1d, the measurement adjustment unit 13a and the detection accuracy adjustment unit 17c can operate in cooperation. Therefore, the measurement period can be extended or shortened based on the ratio between the frequency fxin of the input clock and the first sampling frequency fsin. Note that the measurement period can be determined regardless of the magnification of the frequency fxin of the input clock and the first sampling frequency fsin.

  In describing the present invention, an example in which the frequency fxin of the input clock is 32 times or 48 times the first sampling frequency fsin is used. Further, although the measurement period is set to 2048 times, 2048 × 2 times, and 2048 × 1.5 times the frequency fxout of the output clock, the present invention is not limited to these example values. Measurement adjustment signal determined based on frequency fxin of input clock, increment amount per pulse of input clock determined based on measurement adjustment signal, value of measurement adjustment signal, specific mode of accuracy adjustment signal, detection accuracy The specific mode for outputting the adjustment signal, the end of the measurement period to the frequency ratio measuring unit 153, the specific mode for deriving the frequency ratio N, and the like are variously possible in addition to the mode shown in this example. .

  The sampling rate converter of the present invention is useful in the field of digital signal processing.

The block diagram which shows the structure of the sampling rate converter by 1st Embodiment Block diagram showing details of measurement adjustment unit The block diagram which shows the structure of the sampling rate converter by 2nd Embodiment Block diagram showing details of detection accuracy adjuster The block diagram which shows the structure of the sampling rate converter by 3rd Embodiment The block diagram which shows the structure of the modification of the sampling rate converter by 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Sampling rate converter 1b ... Sampling rate converter 1c ... Sampling rate converter 2a ... Controller 2b ... Controller 3 ... Sampling data output device 5 ... Sampling frequency conversion unit 10a ... Frequency ratio detection data output unit 10b ... Frequency ratio detection data output unit 10c ... Frequency ratio detection data output unit 11 ... Clock generation unit 13a ... Measurement adjustment unit 15a .. Frequency ratio detection unit 15b ... Frequency ratio detection unit 17a ... Detection accuracy adjustment unit 17b ... Detection accuracy adjustment unit 17c ... Detection accuracy adjustment unit 30 ... Status flag generation unit 31 ... Data comparison unit 33 ... delay unit 131 ... selector unit 133 ... measurement fine adjustment unit 135・ ・ ・ Adder 151a ・ ・ ・ Output clock counting unit 151b ・ ・ ・ Output clock counting unit 153 ・ ・ ・ Frequency ratio measurement unit 171 ・ ・ ・ Detection accuracy adjustment signal generation unit 173 ・ ・ ・ Detection accuracy adjustment signal fine adjustment unit 175 ... Adder

Claims (5)

An asynchronous sampling rate converter for converting input data having a first sampling frequency into output data having a second sampling frequency,
A measurement adjustment unit that generates a measurement adjustment signal based on a ratio between the first sampling frequency and an input clock frequency that is a frequency proportional to the first sampling frequency;
The measurement adjustment signal, an input clock having the input clock frequency, and an output clock having the second sampling frequency are received, and the number of pulses of the input clock input during a predetermined measurement period is A frequency ratio detector that counts in increments per pulse determined based on a measurement adjustment signal, and determines a frequency ratio between the first sampling frequency and the second sampling frequency;
A sampling rate converter comprising: a sampling frequency conversion unit that performs sampling frequency conversion of the input data based on the frequency ratio. A detection accuracy adjustment unit configured to generate a detection accuracy adjustment signal based on a ratio between the first sampling frequency and the input clock frequency;
The sampling rate converter according to claim 1, wherein the frequency ratio detection unit changes the length of the measurement period based on the detection accuracy adjustment signal.   The sampling rate converter according to claim 2, wherein the detection accuracy adjustment unit changes the detection accuracy adjustment signal according to the measurement adjustment signal.   The sampling rate converter according to claim 2, wherein the length of the measurement period is proportional to the increment amount. And a status flag generator for generating a status flag indicating the stability of the frequency ratio,
The status flag generation unit determines stability of the frequency ratio based on the frequency ratio and a frequency ratio measured before the frequency ratio, generates the status flag,
The sampling rate converter according to claim 1, wherein the sampling frequency converter starts sampling frequency conversion of the input data based on the status flag.

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