KR101579678B1 - Time-digital converter and method for controlling the time-digital converter thereof - Google Patents

Abstract

The present invention relates to a time-to-digital converter and a control method thereof, wherein the time-to-digital converter uses a plurality of first delay elements connected in series to output a plurality of first delay signals A first delay circuit for outputting a first clock signal; An input selector for providing at least one of the first delay signals as an input signal to the first delay circuit; A second delay circuit for outputting a plurality of second delay signals having different delay times with respect to an input second signal by using a plurality of second delay elements connected in series; And an encoder for outputting a digital signal corresponding to a time difference between the first and second signals using the first and second delay signals respectively input from the first and second delay circuits.

Description

TIME-DIGITAL CONVERTER AND METHOD FOR CONTROLLING THE TIME-DIGITAL CONVERTER THEREOF BACKGROUND OF THE INVENTION [0001]

The present invention relates to a time-to-digital converter for outputting a digital signal corresponding to a time difference between input signals using a plurality of delay elements.

A time-to-digital converter (TDC) is a device that converts the time difference between two signals into a digital signal, the input signal may be in the form of a pulse and a simple rising signal from a different source Rising signal.

As wireless communications are mostly implemented in wideband communications and the demand for higher time resolution increases, a time-to-digital converter with a high temporal resolution and short latency is required.

In general, the time-digital converter can be broadly divided into a CDL (chain delay line) method, a VDL (vernier delay line) method, a PS (pulse shrinking) method, and a method using both methods. The time-to-digital converter is a device that converts the time difference between two input signals (START STOP signal) into a digital signal.

The VDL time-to-digital converter implements a time-to-digital converter (TDC) using a vernier delay stage. Although high resolution can be obtained, a delay mismatch can occur due to process, voltage and temperature changes, There is a problem that the chip area increases.

It is an object of the present invention to provide a time-digital converter having a configuration capable of efficiently utilizing delay elements and a control method thereof.

A time-to-digital converter according to an embodiment of the present invention includes a first delay circuit for outputting a plurality of first delay signals having different delay times to an input first signal by using a plurality of first delay elements connected in series, ; An input selector for providing at least one of the first delay signals as an input signal to the first delay circuit; A second delay circuit for outputting a plurality of second delay signals having different delay times with respect to an input second signal by using a plurality of second delay elements connected in series; And an encoder for outputting a digital signal corresponding to a time difference between the first and second signals using the first and second delay signals respectively input from the first and second delay circuits.

According to another aspect of the present invention, there is provided a time-to-digital converter including a plurality of first delay elements connected in series, a first delay circuit for outputting a plurality of first delay signals having different delay times to an input first signal, Circuit; A first mux providing one or more of the first delay signals as an input signal to the first delay circuit; A second delay circuit for outputting a plurality of second delay signals having different delay times with respect to an input second signal by using a plurality of second delay elements connected in series; A second mux connected to the second delay circuit to correspond to a connection position of the first mux; And outputting a digital signal corresponding to a time difference between the first and second signals using the first and second delay signals input from the first and second delay circuits, respectively.

The time-to-digital converter according to another embodiment of the present invention outputs a digital signal corresponding to a time difference between input signals using a plurality of delay elements, and uses the plurality of delay elements connected in series to output a frequency And outputting the amplified signal; And an input selector for selecting one of the reference signal and the frequency-amplified reference signal and inputting the selected signal to the delay elements, wherein the frequency body allocator is configured to select one of the reference signal and the frequency- And outputs a plurality of delay signals having different delay times.

Also, the communication apparatus according to the embodiment of the present invention may be configured to include the time-to-digital converter.

In the meantime, a time-digital converter control method according to an embodiment of the present invention includes a first and second delay circuits each having a plurality of delay elements serially connected to each other to output a digital signal corresponding to a time difference between input signals, Selecting at least one of a plurality of first delay signals having different delay times output from the first delay circuit; And providing the selected first delay signal as an input signal to the first delay circuit.

According to an embodiment of the present invention, by combining the delay elements of the frequency multiplying device and the vernier time digital converter, the configuration area and power consumption of the communication device can be reduced.

Also, time information of a signal inputted at a high frequency with a low reference frequency can be measured by analyzing the time difference between the reference signal and the input signal by using the frequency multiplication device.

1 is a diagram showing an embodiment of a configuration of a frequency multiplication device.
2 is a diagram showing an embodiment of a configuration of a vernier time digital converter.
3 is a block diagram showing a first embodiment of the configuration of a time-digital converter according to the present invention.
4 is a block diagram showing a second embodiment of the configuration of a time-digital converter according to the present invention.
5 is a flowchart illustrating a method of controlling a time-digital converter according to an embodiment of the present invention.
6 is a diagram showing a third embodiment of the configuration of the time-digital converter according to the present invention.
7 is a diagram showing a fourth embodiment of the configuration of a time-digital converter according to the present invention.
8 is a diagram showing a fifth embodiment of a configuration of a time-digital converter according to the present invention.

The operation principle of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings and description. It should be understood, however, that the drawings and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention, and are not to be construed as limiting the present invention. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terms used below are defined in consideration of the functions of the present invention, which may vary depending on the user, intention or custom of the operator. Therefore, the definition should be based on the contents throughout the present invention.

As a result, the technical idea of the present invention is determined by the claims, and the following embodiments are merely means for effectively explaining the technical idea of the present invention to a person having ordinary skill in the art to which the present invention belongs Only.

1 shows an embodiment of a configuration of a frequency multiplication device.

Referring to FIG. 1, the frequency multiplication device may include a plurality of time delay elements 101 to 108 and a multiplexer (MUX) 110.

The frequency multiplication device can amplify the frequency of the input reference signal REF using a plurality of time delay elements 101 to 108 and output a frequency amplified reference signal REF_MUL having a higher frequency .

The frequency multiplication apparatus according to an embodiment of the present invention as shown in FIG. 1 is based on a delay locked loop (DLL), which can be used to generate an internal clock in a communication apparatus have.

The delay locked loop may delay the received external clock by a predetermined time using a delay line including a plurality of delay elements 101 to 108 to generate an internal clock synchronized with the external clock.

Although the frequency multiplication device is shown as including eight delay elements 101 to 108 in FIG. 1, the present invention is not limited thereto, and may be configured to include seven or fewer delay elements as necessary . Also, the signal fed back to the MUX 110 can be any one of the first delay signals d21 to d28.

The delay multiplier-based frequency multiplication device as described above has less phase noise due to the absence of jitter accumulation as compared with the phase locked loop based device, and can be miniaturized since the structure of the loop filter is simple. In particular, in the case of a semiconductor memory device, the data transfer rate can be increased by using an internal clock having a frequency multiplied by the frequency of the external clock, and by using clocks having an accurate phase delay and duty ratio for data transfer, Errors can be reduced.

2 shows an embodiment of the configuration of a vernier time digital converter, and the illustrated time-to-digital converter includes a first delay circuit 200, an encoder 210 and a second delay circuit 220 .

The vernier time digital converter shown in Fig. 2 can measure the time difference of the rising edges of the first signal and the second signal to convert the time difference of the transition timing between the two signals into a digital value.

For example, the first delay circuit 200 receives the reference signal REF as the first signal, and the second delay circuit 220 receives the second signal DIV for which the time difference of the reference signal is to be measured Input can be received.

The encoder 210 generates a digital signal TDC_OUT corresponding to a time difference between the first signal REF and the second signal DIV using the delay signals input from the first and second delay circuits 200 and 220. [ ).

The first delay circuit 200 includes a plurality of first delay elements 201 to 208 connected in series and a plurality of first delay signals having different delay times for the input first signal REF d11 to d18.

The second delay circuit 220 uses a plurality of second delay elements 221 to 228 connected in series to output a plurality of second delay signals having different delay times to the input second signal DIV d21 to d28.

2, the first and second delay circuits 200 and 220 are shown as including eight delay elements 201 to 208 or 221 to 228, respectively, but the present invention is not limited thereto. And may include not more than seven or not less than nine delay elements.

The plurality of first delay elements 201 to 208 included in the first delay circuit 200 may have the same time delay value and the plurality of second delay elements 201 to 208 included in the second delay circuit 220 may have the same time delay value, The time slots 221 to 228 may have the same time delay value.

However, the first delay elements 201 to 208 included in the first delay circuit 200 and the second delay elements 221 to 228 included in the second delay circuit 220 have different time delay values from each other Lt; / RTI >

Specifically, the first delay circuit 200 includes a plurality of first delay elements 201 to 208 connected in series. The first delay circuit 200 is connected to the reference signal REF, which is the first signal, It is possible to provide the encoder 210 with a plurality of first delay signals d11 to d18 given different delays by corresponding time delays.

The second delay circuit 220 includes a plurality of second delay elements 221 to 228 connected in series and gives a second delay time t2 corresponding to the second delay time t2 to the second signal DIV It is possible to provide the encoder 210 with a plurality of second delay signals d21 to d28 to which different delays are given.

In this case, the first delay value t1, which is the time delay value of each of the first delay elements 201 to 208, is a time delay value of the second delay elements 221 to 228, May be set longer than the delay value t2.

Accordingly, the time difference between the first signal REF and the second signal DIV is Δt = (t1 (t1) / t2) every time the delay elements in the first delay circuit 200 and the second delay circuit 220 pass through the delay element by one stage, -t2).

For example, when the initial time difference between the first signal REF and the second signal DIV is T, at the time of passing through the delay elements of (T /? T) 2 < / RTI > signal DIV can be reversed.

The encoder 210 outputs 0 until the edge timing of the second signal DIV catches the edge timing of the first signal REF and the edge of the second signal DIV The encoder 210 can output 1 after the timing catches the edge timing of the first signal REF.

The encoder 210 generates the second signal DIV using the first and second delay signals d11 to d18 and d21 to d28 input from the first and second delay circuits 200 and 220, The edge timing of the first signal REF is detected at the edge timing of the first signal REF and the digital signal TDC_OUT corresponding to the time difference between the two signals REF and DIV can be output.

The case where the time delay value t1 by each of the first delay elements 201 to 208 is longer than the time delay value t2 by each of the second delay elements 221 to 228 is taken as an example, Although the operation of the time-digital converter according to one embodiment has been described, the present invention is not limited thereto.

For example, the time delay value t1 by each of the first delay elements 201 to 208 may be set shorter than the time delay value t2 by each of the second delay elements 221 to 228, In this case, the encoder 210 outputs 0 until the edge timing of the first signal REF catches the edge timing of the second signal DIV, and the edge timing of the first signal REF becomes the second signal DIV < / RTI >), the encoder 210 can output a 1.

FIG. 3 is a block diagram of a first embodiment of the configuration of a time-to-digital converter according to the present invention. The time-to-digital converter shown includes a frequency multiplication device 300, an encoder 310 and a delay circuit 320 can do.

The operation of the frequency multiplication apparatus 300 and the time-digital converter including the frequency multiplication apparatus 300 shown in FIG. 3 will be omitted from the following description with reference to FIGS. 1 and 2.

The time digital converter according to an embodiment of the present invention as shown in FIG. 3 can reduce the configuration area and power consumption of the communication device by combining the delay elements of the frequency multiplication device and the Vernier time digital converter.

For example, the frequency multiplication apparatus 300 may perform a frequency multiplication function for amplifying a frequency of an input first signal REF using a plurality of first delay elements connected in series and outputting a frequency-amplified reference signal REF_MUL And outputs a plurality of first delay signals having different delay times together with the first delay circuit 200 described with reference to FIG.

In this case, either the reference signal REF or the frequency-amplified reference signal REF_MUL may be selected and used as an input signal for outputting the first delay signals having different delay times. Also, any one of the first delay signals may be used as the output (REF_MUL) of the frequency multiplier 300.

As described above, it is possible to analyze the time difference between the input signal and the reference signal REF_MUL by amplifying the frequency using the frequency multiplication device 300 provided in the time digital converter, The time information of the signal DIV input at a high frequency can be measured.

The delay circuit 320 outputs a plurality of second delay signals having different delay times to the input second signal DIV using a plurality of second delay elements connected in series.

The encoder 310 generates a digital signal TDC_OUT corresponding to a time difference between the first signal REF and the second signal DIV using the delay signals input from the frequency doubling device 300 and the delay circuit 320, ).

4 is a block diagram of a second embodiment of the configuration of a time digital converter according to the present invention. The time digital converter shown includes a first delay circuit 400, an encoder 410, a second delay circuit 420 And an input selection unit 430. The input selection unit 430 may include a plurality of input units.

The first delay circuit 400 uses a plurality of first delay elements connected in series to provide a plurality of first delay signals having different delay times to the input first signal REF to the encoder 410 .

Meanwhile, the input selector 430 may provide at least one of the first delay signals as an input signal to the first delay circuit 400.

For example, the input signal to the first delay circuit 400 may be a signal having the longest delay time among the plurality of first delay signals, or may be a signal having the longest delay time among the plurality of first delay signals, Or a frequency amplified reference signal REF_MUL of the first delay circuit 400 that performs a frequency multiplying function.

According to an embodiment of the present invention, the input selector 430 selects either the reference signal REF or the frequency-amplified reference signal REF_MUL as an input signal to the first delay circuit 400 .

The second delay circuit 420 may output a plurality of second delay signals having different delay times to the input second signal DIV using a plurality of second delay elements connected in series.

The encoder 410 is connected between the first signal REF or REF_MUL and the second signal DIV using the first and second delay signals input from the first and second delay circuits 400 and 420, And outputs the digital signal TDC_OUT corresponding to the time difference of the time difference.

5 is a flowchart illustrating a method of controlling a time-digital converter according to an embodiment of the present invention. Referring to FIG. 5, a control method of the time-digital converter according to the third embodiment of the present invention shown in FIG. Will be described with reference to the drawings.

5, the input selector 430 included in the time-digital converter includes at least one of a plurality of first delay signals d11 to d18 having different delay times output from the first delay circuit 400, (Step S500).

For this purpose, the input selection unit 430 may include a multiplexer 431 that can select one of the two or more signals to be input according to the selection signal SEL and output the multiplexed signal.

For example, the reference signal REF and the reference signal REF_MUL frequency-amplified by the frequency-doubling function of the first delay circuit 400 are input to the mux 431 included in the input selector 430, The mux 431 can select either the reference signal REF or the frequency-amplified reference signal REF_MUL as the input signal to the first delay circuit 400 according to the selection signal SEL.

Thereafter, the input selector 430 provides the selected signal as an input signal to the first delay circuit 400 (step S510).

In the case shown in Fig. 6, the time delay circuit for frequency multiplication and the time delay circuit necessary for time digital conversion are each composed of eight stages, and a time-digital converter is configured to have the same number of stages.

According to another embodiment of the present invention, a frequency multiplication device and a time-to-digital converter whose numbers are different from each other may be combined as described with reference to Figs. 1 to 6.

For example, when the number of stages of time delay circuits for frequency multiplication included in the time-digital converter is n and the number of stages of time delay circuits required for time-to-digital conversion is m (m ≠ n) (N) of the time delay circuit for frequency multiplication can be changed.

7 illustrates a fourth embodiment of the configuration of the time-digital converter according to the present invention. The description of the configuration shown in FIG. 7 that is the same as that described with reference to FIGS. 1 to 6 will be omitted below .

Referring to FIG. 7, if a 3-bit time digital converter is required, the first and second delay circuits 400 and 420 included in the time-to-digital converter must each be composed of eight stages.

In this case, if there are five stages of time delay circuits for frequency multiplication, a frequency multiplication device having five and eight stages, respectively, and a time digital converter can be combined as shown in FIG.

That is, the first delay signal d15 that has passed through the five delay elements 401 to 405 is fed back to the mux 431, so that a time delay circuit composed of five stages can be used for frequency multiplication.

On the other hand, the stage of the first delay circuit 400 included in the time-to-digital converter is maintained at 8, so that a 3-bit time-digital converter can be constructed.

At this time, the amplified reference signal REF_MUL may be any one or more of the first delay signals d11 to d18 or an output terminal signal of the mux 431, .

As described above, when the position of a signal fed back to the multiplexer 431 is changed, an additional load for providing an input signal to the multiplexer 431 is generated in the delay element at the preceding stage, The time difference may be different from the time difference between the other adjacent delay elements.

According to another embodiment of the present invention, in order to solve the problem of the difference in the time difference between adjacent delay elements as described above, Or an element having the same load as the mux 431 may be connected to the same position of the second delay circuit 400. [

8, the position (delay element 425) of the second delay circuit 420, which is the same as the position of the signal fed back from the first delay circuit 400 to the mux 431 (the rear end of the delay element 405) The rear end of the mux 431 may be connected to a mux 441 having the same size as the mux 431 or a device having the same load as the mux 431 to solve the above problems.

In this case, the selection signal SEL2 of the multiplexer 441 connected to the second delay circuit 420 can be fixed so that the output of the multiplexer 441 always becomes the second signal DIV.

According to another embodiment of the present invention, in a frequency multiplication device or a time-digital converter as described with reference to Figs. 1 to 8, a time delay circuit (for example, first and second delay circuits 400 and 420 ) May be connected to a control signal line to be implemented in the form of a multiplexing delay-locked loop (MDLL).

The control method of the time digital converter according to the present invention may be implemented as a program to be executed by a computer and stored in a computer readable recording medium. Examples of the computer readable recording medium include a ROM, a RAM, a CD -ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet).

The computer readable recording medium may be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And, functional programs, codes and code segments for implementing the above method can be easily inferred by programmers of the technical field to which the present invention belongs.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (16)

In a vernier time digital converter using a plurality of delay elements,
A first delay circuit for outputting a plurality of first delay signals having different delay times with respect to an input first signal by using a plurality of first delay elements connected in series;
An input selector for providing one or more of the first delay signals as an input signal to the first delay circuit;
A second delay circuit for outputting a plurality of second delay signals having different delay times with respect to an input second signal by using a plurality of second delay elements connected in series; And
And an encoder for outputting a digital signal corresponding to a time difference between the first and second signals using the first and second delay signals respectively inputted from the first and second delay circuits,
Wherein a position at which the first delay signal is fed back to the input selection section corresponds to a time delay stage of the second delay circuit when the time delay stage of the first delay circuit is different from the time delay stage of the second delay circuit, And an element having the same size or the same load as the input selector of the first delay circuit is connected to the same position of the second delay circuit. 2. The semiconductor memory device according to claim 1, wherein the first delay circuit
And a frequency multiplication function for amplifying and outputting the frequency of the reference signal using the plurality of first delay elements. 3. The semiconductor memory device according to claim 2, wherein the first delay circuit
And using any one of the plurality of first delay signals as an output according to the frequency multiplying function. 4. The semiconductor memory device according to claim 3, wherein the first delay circuit
And using one or more of the plurality of first delay signals as an output according to the frequency multiplying function. 4. The semiconductor memory device according to claim 3, wherein the first delay circuit
A time-digital converter that uses one or more of the signals that have passed through all of the plurality of first delay elements among the plurality of first delay signals or the output signals of the first delay elements as outputs based on the frequency multiplying function, converter. 3. The apparatus of claim 2, wherein the input selector
And provides said frequency amplified reference signal as an input signal to said first delay circuit. 3. The apparatus of claim 2, wherein the input selector
And provides either the reference signal or the frequency-amplified reference signal as an input signal to the first delay circuit. 8. The apparatus of claim 7, wherein the input selector
And a MUX for receiving the reference signal and the frequency-amplified reference signal and outputting one of the two input signals. 9. The method of claim 8,
And outputs either the reference signal or the frequency-amplified reference signal according to an input selection signal (SEL). In a vernier time digital converter using a plurality of delay elements,
A first delay circuit for outputting a plurality of first delay signals having different delay times with respect to an input first signal by using a plurality of first delay elements connected in series;
A first mux providing one or more of the first delay signals as an input signal to the first delay circuit;
A second delay circuit for outputting a plurality of second delay signals having different delay times with respect to an input second signal by using a plurality of second delay elements connected in series;
A second mux connected to the second delay circuit to correspond to a connection position of the first mux; And
And an encoder for outputting a digital signal corresponding to a time difference between the first and second signals using the first and second delay signals respectively inputted from the first and second delay circuits,
Wherein a position at which the first delay signal is fed back to the first mux corresponds to a time delay stage of the second delay circuit when the time delay stage of the first delay circuit is different from the time delay stage of the second delay circuit Wherein the second mux having the same magnitude or the same load as the first mux of the first delay circuit is connected to the same position as the first mux of the second delay circuit, . delete delete A communication device comprising the time-to-digital converter according to any one of claims 1 to 10. There is provided a method of controlling a vernier time digital converter that outputs a digital signal corresponding to a time difference between input signals using first and second delay circuits each having a plurality of delay elements connected in series,
Selecting one or more of a plurality of first delay signals having different delay times output from the first delay circuit by an input selector; And
And returning the selected first delay signal as an input signal to the first delay circuit,
Wherein a position at which the first delay signal is fed back to the input selection section corresponds to a time delay stage of the second delay circuit when the time delay stage of the first delay circuit is different from the time delay stage of the second delay circuit, And an element having the same size or the same load as the input selector of the first delay circuit is connected to the same position of the second delay circuit. 15. The method of claim 14,
And amplifying and outputting the frequency of the reference signal using the plurality of first delay elements. 16. The method of claim 15,
And selecting one of the reference signal and the frequency-amplified reference signal as an input signal to the first delay circuit.

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