JP2009303034A - Frequency converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency converter capable of selecting a relationship of free conversion including a decimal point. <P>SOLUTION: Using a multiplier, an input pulse string signal is multiplied by a multiplication number N set in advance and converted into a multiplied pulse string signal. Next, the multiplied pulse string signal is divided into m-divisions by a divider and thus an output pulse string signal having a frequency Fo in a constant relationship with a frequency Fi of the input pulse string signal is obtained. A frequency conversion coefficient R indicative of a relationship between the frequency of the input pulse string signal and the frequency of the output pulse string signal is determined by R=N/m. It is possible to obtain the frequency conversion coefficient R of a value including a decimal number by varying values of the multiplication number N and the number of divisions m. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention measures the output signal from the sensor and converts the frequency of the pulse train signal to another frequency maintaining a certain relationship in the field of measurement and control in which the object is controlled according to the result. The present invention relates to a frequency converter.

  In some cases, the input / output signal format of the device is a pulse train signal, and the number of pulses and the period of the signal are important. In order to use such a pulse train signal in another device, it is necessary to convert the frequency of the pulse train signal to another frequency maintaining a certain relationship.

Conventionally, a frequency divider that inverts the output every time a certain number of pulses are counted has been proposed for the above applications (see, for example, Patent Document 1). Further, there has been proposed a doubler that detects a rising edge and a falling edge of each pulse and generates a pulse at each timing to obtain a doubled pulse train signal (see, for example, Patent Document 2). .
JP 2004-228812 A JP 2001-111347 A

  In the frequency divider described in Patent Document 1, it is possible to divide the input pulse train signal by an integral multiple, but the conversion relationship is such that the relation between the input pulse train and the output pulse train includes a decimal number. I can't.

  The double multiplier described in Patent Document 2 can obtain a pulse number that is an even number multiple of the input pulse number by combining a plurality, but the conversion relationship in which the relationship between the input pulse train and the output pulse train includes a decimal number Can not be.

  Further, when a plurality of doublers as described in Patent Document 2 are combined, the period and waveform of the output pulse become discontinuous. For example, an output pulse train signal with a duty ratio of 50% is obtained. It is difficult.

  In addition, frequency multipliers using special techniques such as DDS (Direct Digital Synthesizer) and PLL (Phase Locked Loop) have been put into practical use. However, such a frequency multiplier requires an expensive and highly accurate reference clock oscillation element and a complicated circuit configuration, and is not suitable for a response to a high-speed input change.

  An object of the present invention is to provide a frequency converter capable of selecting a free conversion relation including a decimal point.

  In order to solve the above problems, a frequency converter according to the present invention includes a multiplier that multiplies an input pulse train signal by an arbitrary multiplication number to convert it to a multiplied pulse train signal, and a multiplied pulse train signal converted by the multiplier. And a frequency divider that divides the frequency by the frequency dividing number and converts it to an output pulse train signal.

  In the frequency converter according to the present invention, first, an input pulse train signal is multiplied by a preset multiplication number using a multiplier to be converted into a multiplied pulse train signal. Then, by passing the multiplied pulse train signal through a frequency divider, the frequency of the input pulse train signal is converted to another frequency maintaining a certain relationship, and an output pulse train signal is obtained.

  According to the frequency converter of the present invention, the frequency conversion coefficient indicating the relationship between the frequency of the input pulse train signal and the frequency of the output pulse train signal is selected by separately selecting the multiplication number and the frequency division number. Can be.

  Hereinafter, the best mode for carrying out the frequency converter of the present invention will be described with reference to the drawings, but the present invention is not limited to the following mode.

[Converter configuration example]
FIG. 1 is a block diagram showing the configuration of the first embodiment of the frequency converter of the present invention.
The frequency converter 1 multiplies an input pulse train signal by an arbitrary multiplication number to convert it into a multiplied pulse train signal, and divides the multiplied pulse train signal output from the multiplier 2 by an arbitrary division number. Thus, a frequency divider 3 for converting to an output pulse train signal and a setting unit 4 for setting the multiplication number and the frequency division number are provided.

  The multiplier 2 includes a reference clock oscillator 11, an input period measurement counter 12, a multiplied pulse output counter 13, and a counter control unit 14.

  The reference clock oscillator 11 transmits a reference clock having an input frequency f0 to the input cycle measurement counter 12 and the multiplied pulse output counter 13. An input pulse train signal is input to the input cycle measuring counter 12. The input cycle measuring counter 12 measures the input pulse cycle of the input pulse train signal by counting the reference clock transmitted from the reference clock oscillator 11.

  The counter control unit 14 is configured by a CPU (Central Processing Unit). The counter control unit 14 calculates the multiplied pulse period by dividing the input pulse period measured by the input period measuring counter 12 by an arbitrary multiplication number, and sets it as the output period of the multiplied pulse output counter 13. The multiplied pulse output counter 13 generates a multiplied pulse train signal by generating a multiplied pulse every time the reference clock is counted by a value corresponding to the multiplied pulse period. Then, the multiplied pulse output counter 13 outputs the generated multiplied pulse train signal to the frequency divider 3.

  The frequency divider 3 divides the multiplied pulse train signal output from the multiplied pulse output counter 13 by an arbitrary frequency division number and outputs it as an output pulse signal. The setting unit 4 is connected to the counter control unit 14 and the frequency divider 3. By operating this setting unit 4, the multiplication number of the multiplier 2 and the division number of the frequency divider 3 can be set to arbitrary values.

  In the frequency converter 1, the multiplier 2 is used to convert the input pulse train signal into a multiplied pulse train signal. The multiplied pulse train signal has a frequency larger than the frequency of the input pulse train signal. Then, by dividing the multiplied pulse train signal by the frequency divider 3, it is converted into an output pulse train signal having a frequency having a free conversion relation including a decimal with respect to the frequency of the input pulse train signal.

Assuming that the multiplication number of the multiplier 2 is N and the frequency division number of the frequency divider 3 is m, a frequency conversion coefficient R indicating a conversion relationship from the frequency of the input pulse train signal to the frequency of the output pulse train signal is:
R = N / m
Is calculated by
If the frequency of the input pulse train signal is Fi and the frequency of the output pulse train signal is Fo, Fi and Fo satisfy the following relationship.
Fo = R × Fi

  Values of the multiplication number N and the frequency division number m that determine the frequency conversion coefficient R can be freely selected by the setting unit 4. Therefore, in the frequency converter 1, the frequency conversion coefficient R can be set to a value including a decimal. For example, if 5 is selected as the multiplication number N and 2 is selected as the frequency division number m, the frequency conversion coefficient R becomes 2.5.

[Description of frequency conversion]
FIG. 2 is an explanatory diagram for explaining the conversion from the input pulse train signal to the output pulse train signal performed by the frequency converter 1.

  As described above, the frequency conversion coefficient R is determined by a combination of the multiplication number N set in the multiplier 2 and the frequency division number m set in the frequency divider 3. The input pulse train signal is multiplied by N by the multiplier 2 and converted to a multiplied pulse train signal. The multiplied pulse train signal is frequency-divided by m by the frequency divider 3 to be converted into an output pulse train signal.

When the input pulse train signal is input, the counter 12 for measuring the input cycle of the multiplier 2 counts the reference clock transmitted from the reference clock oscillator 11 and the cycle of the input pulse train signal (hereinafter referred to as “input pulse cycle”). Measure. At this time, if the frequency of the reference clock is f0 and the input pulse period is T _k , the count number C _k of the input period measuring counter 12 is
C _k = f0 × T _k
It becomes.

The counter control unit 14 calculates the reference clock number corresponding to the multiplied pulse period by dividing the count number C _k of the input period measuring counter 12 by the multiplied number N, and sets it as the output period of the multiplied pulse output counter 13. To do. That is, if the reference clock number corresponding to the multiplied pulse period is the multiplication count number C _B , the multiplication count number C _B and the input period measurement counter 12 count number C _k satisfy the following relationship.
C _B = C _k / N

Multiplied pulse output counter 13, each time counting the reference clock only multiplication for counting the number of C _B, to output a multiplied pulse to generate a multiplied pulse train signal. When obtaining a multiplied pulse train signal in this way, the multiplied pulse period _TN satisfies the following relationship.
T _N = C _B / f0
= (C _k / N) / f0
= (F0 × T _k / N) / f0
= T _k / N

Thus, since the count number C _k and the multiplication count number C _B are counted using the same reference clock, the multiplication pulse period T _N can be calculated regardless of the value of the frequency f0 of the reference clock. it can. As a result, the frequency converter 1 can measure the multiplied pulse period _TN without using a high-precision and expensive reference clock oscillator.

  The frequency divider 3 divides the multiplied pulse train signal by the frequency division number m and converts it to an output pulse train signal. At this time, the frequency divider 3 inverts the output every time the multiplied pulse of the multiplied pulse train signal is counted m / 2 (one period of the output pulse train signal corresponds to the multiplied pulse m count). If the period is constant, the waveform of the output pulse train can be 50% Duty ratio.

Here, the multiplication number N and the frequency division number m will be described.
The multiplication number N according to the present invention may be a value including not only a positive integer but also a small number. That is, the multiplication number N is a rational number. This is because the multiplication number N is used to determine the cycle of the multiplied pulse train signal (hereinafter referred to as “multiplied pulse cycle”) having a fixed relationship with the input pulse train signal. This is because it is only necessary to be able to calculate.
The frequency division number m according to the present invention is a positive integer. This is because the frequency division number m is used to count the number of multiplied pulses, and the counter cannot count less than one.

  In the frequency converter 1, the period during which the multiplied pulse is output corresponds to the input pulse period. That is, the multiplied pulse based on the current input pulse is output in the output period corresponding to the next input pulse cycle. Therefore, if the input pulse period is constant and stable, the period during which the multiplied pulse is output is also constant and stable, and no problem occurs.

  However, when the period of the input pulse train signal changes, the following problem occurs.

(1) When the current input pulse period is shorter than the previous input pulse period When the current input pulse period is shorter than the previous input pulse period, the output of the multiplied pulse based on the previous input pulse is completed. A new input pulse is detected. At this time, waiting for the output of the multiplied pulse based on the current input pulse until the output of the multiplied pulse based on the current input pulse is completed until the output of the multiplied pulse based on the previous input pulse is completed. It will shift. As a result, it is necessary to store the times at which the output of the multiplied pulse is started, which increases the load of output control and deteriorates the responsiveness of the output pulse train signal.

(2) If the current input pulse period is longer than the previous input pulse period If the current input pulse period is longer than the previous input pulse period, the output of the multiplied pulse based on the previous input pulse is completed. The output period of the multiplied pulse output based on the current input pulse is not determined. Therefore, the multiplication pulse and the output pulse are not continuously output, and the responsiveness is deteriorated.

  Therefore, every time an input pulse is detected, the frequency converter 1 reviews the number of multiplied pulses and the multiplied pulse period based on the current input pulse so that the influence of fluctuations in the input pulse period does not remain for a long time. A multiplied pulse train signal is obtained.

  FIG. 3 is an explanatory diagram showing an output relationship between the input pulse and the multiplied pulse when the input pulse period of the input pulse train signal is constant.

The multiplier 2 of the frequency converter 1, and the time t _k which detects the current of the input pulse, and calculates the current input pulse period T _k from time t _{k + 1} that has detected the next input pulse. Then, the multiplied pulse period _TN is determined according to the result of comparing the current input pulse period T _k and the previous input pulse period T _k−1 , thereby realizing a quick response characteristic.

The counter control unit 14 of the multiplier 2 _first calculates a multiplied pulse period T _N-1 of the multiplied pulse output based on the previous input pulse. The multiplied pulse period T _N-1 is
T _N-1 = (T _k-1 ) / N
Is calculated by

Then, counter control section 14 detects the next input pulse, and calculates the current input pulse period T _k. At this time, if the previous input pulse period T _k−1 and the current input pulse period T _k are equal, the multiplication pulse based on the previous input pulse is multiplied in the output period corresponding to the current input pulse period T _k. Only the multiplication number N (four in this example) is output in the pulse period T _N−1 .

  FIG. 4 is an explanatory diagram showing an output relationship between the input pulse and the multiplied pulse when the input pulse period of the input pulse train signal is changed so as to be shortened.

As shown in FIG. 4, when the next input pulse is detected before the output of the multiplied pulse based on the previous input pulse is completed, the current input pulse period T _k becomes the previous input pulse period T _{k−. Shorter} than ₁ . In that case, the counter control unit 14 first detects the number of multiplied pulses output based on the previous input pulse until the output period of the multiplied pulse based on the current input pulse is started. That is, the counter control unit 14 detects the number of multiplied pulses output based on the previous input pulse until the next input pulse is detected.

  Next, the counter control unit 14 subtracts the detected number of multiplied pulses from the multiplied number N, and adds the value to the multiplied number N to calculate the multiplied pulse change number. In other words, the number of multiplication pulse changes when the input pulse period changes so as to be shortened is obtained by subtracting the number of pulses already output from the number of pulses to be output based on the previous input pulse, and setting that value as the current input pulse. Based on the number of pulses to be output based on this.

Next, the counter control unit 14 changes the multiplication pulse period _TN so that the multiplication pulse of the number of multiplication pulse changes is output during the output period of the multiplication pulse based on the current input pulse. Assuming that the number of multiplication pulses based on the previous input pulse output before the start of the output period of the multiplication pulse based on the current input pulse is b, the multiplication pulse period T _N to be changed is
T _N = T _k / (2N−b)
Is calculated by

As shown in FIG. 4, when the multiplication number N is 4 and the already output pulse number b is 3, the multiplication pulse change number is 5, and during the output period of the multiplication pulse based on the current input pulse, 5 Two multiplied pulses are output. The multiplied pulse period T _{N at} this time is T _k / 5.

As described above, in the frequency converter 1, when the current input pulse cycle _Tk is shorter than the previous input pulse cycle _Tk-1 , the number of multiplied pulses in the output period of the multiplied pulse based on the current input pulse. And the multiplication pulse period _TN is changed. Thereby, it can prevent that the multiplication pulse of a multiplication pulse train signal delays with respect to the input pulse of an input pulse train signal. As a result, the output pulse train signal converted from the multiplied pulse train signal can be prevented from being affected by the fluctuation of the input pulse period for a long time.

  FIG. 5 is an explanatory diagram showing an output relationship between the input pulse and the multiplied pulse when the input pulse period of the input pulse train signal changes so as to become longer.

As shown in FIG. 5, when the current input pulse period T _k becomes longer than the previous input pulse period T _k−1 , the next input pulse is output even if the output of the multiplied pulse based on the previous input pulse is completed. Is not detected. For this reason, the multiplied pulses are not continuously output, and the response of the output pulse train signal to the input pulse train signal is deteriorated.

Therefore, the counter control unit 14 performs the multiplication based on the previous input pulse from the completion of the output of the multiplied pulse based on the previous input pulse until the output period of the multiplied pulse based on the current input pulse is started. A multiplied pulse is output at a pulse period _TN-1 . That is, the counter control unit 14 controls the multiplied pulse output counter 13 and outputs a multiplied pulse at a multiplied pulse period T _N−1 until the next input pulse is detected.

  Thereafter, when the next input pulse is detected, the output period of the multiplied pulse based on the current input pulse is started. At this time, the counter control unit 14 calculates the number of multiplied pulses output from the completion of the output of the multiplied pulse based on the previous input pulse to the start of the output period of the multiplied pulse based on the current input pulse. To detect.

  Next, the counter control unit 14 subtracts the detected multiplied pulse number from the multiplied number N to calculate the multiplied pulse change number. In other words, the number of multiplication pulse changes when the input pulse period is changed to be longer is the number of extra multiplication pulses output until the start of the output period of the multiplication pulse based on the current input pulse. This is obtained by subtracting the number of multiplied pulses to be output based on the pulse.

Next, the counter control unit 14 changes the multiplication pulse period _TN so that the multiplication pulse of the number of multiplication pulse changes is output during the output period of the multiplication pulse based on the current input pulse. If the number of multiplication pulses output from the completion of the output of the multiplication pulse based on the previous input pulse to the start of the output period of the multiplication pulse based on the current input pulse is c, the multiplication pulse cycle to be changed _TN is
T _N = T _k / (N−c)
Is calculated by

As shown in FIG. 5, when the multiplication number N is 4, and the multiplication pulse number c output until the output period of the multiplication pulse based on the current input pulse is 1, the multiplication pulse change number Becomes 3, and three multiplied pulses are output during the output period of the multiplied pulse based on the current input pulse. The multiplied pulse period T _{N at} this time is T _k / 3.

Thus, in the frequency converter 1, when the current input pulse cycle _Tk is longer than the previous input pulse cycle _Tk-1 , the number of multiplied pulses in the output period of the multiplied pulse based on the current input pulse. And the multiplication pulse period _TN is changed. Thereby, the multiplied pulse of the multiplied pulse train signal can be continuously output, and the output pulse train signal can be quickly responded to the input pulse train signal.

For example, even if the multiplication pulse of the multiplication number N is output in the multiplication pulse period T _N−1 after the output of the multiplication pulse based on the previous input pulse is completed, the next input pulse is not detected. The output period of the multiplied pulse based on the input pulse may not be started. In that case, the counter control unit 14 determines that the input pulse of the input pulse train signal is in a stopped state, and controls the multiplied pulse output counter 13 to stop the generation of the multiplied pulse of the multiplied pulse train signal. Thereafter, when an input pulse is detected, the counter control unit 14 controls the multiplied pulse output counter 13 to restart generation of the multiplied pulse of the multiplied pulse train signal.

Also, the time Ta (see FIGS. 4 and 5) from the completion of the output of the last multiplied pulse based on the previous input pulse to the start of the output period of the multiplied pulse based on the current input pulse is multiplied. It may be shorter than the pulse period _TN-1 . In that case, the counter control unit 14 controls the start time of the output period of the multiplied pulse based on the current input pulse via the multiplied pulse output counter 13. That is, the counter control unit 14 delays the start of the output period of the multiplied pulse output based on the current input pulse so that the interval of the multiplied pulse output is not too short.

The time Td for delaying the start of the output period is
Td = _TN-1− Ta
Calculated by
By the start of the output period is delayed by the time Td, the output period of the multiplied pulse is output based on the present input pulse (corresponding to the input pulse period T _k) is changed to the output period Te. This output period Te is calculated by the following equation.
Te = T _k −Td
= _Tk + Ta- _TN-1

When the output period of the multiplied pulse output based on the current input pulse is changed to the output period Te, the counter control unit 14 determines the frequency of the multiplied pulse output based on the current input pulse based on the output period Te. The multiplied pulse period _TN is determined.

[Effect of the embodiment]
According to the frequency converter 1 of the embodiment described above, first, the multiplier 2 is used to multiply the input pulse train signal to convert it into a multiplied pulse train signal. Then, by dividing the multiplied pulse train signal by the frequency divider 3, an output pulse train signal having a different frequency is obtained while maintaining a predetermined relationship with the frequency of the input pulse train signal. Therefore, the frequency conversion count R including the decimal point can be set only by changing the multiplication number N and the frequency division number m without requiring a special switching operation or the like.

According to the frequency converter 1 of the above-described embodiment, the measurement of the input pulse period by the input period measurement counter 12 and the measurement of the multiplied pulse period by the multiplied pulse output counter 13 are counted using the same reference clock. . Therefore, the multiplied pulse period _TN can be calculated regardless of the value of the frequency f0 of the reference clock, and highly accurate frequency conversion can be performed without using an expensive and highly accurate reference clock oscillator or a complicated circuit. it can.

According to the frequency converter 1 of the above-described embodiment, when the current input pulse period T _k changes with respect to the previous input pulse period T _k−1 , the number of multiplied pulses output based on the previous input pulse and Change the number of multiplication pulses to be output based on the current input pulse. And the multiplication pulse period _TN of the multiplication pulse output based on this input pulse is changed. Therefore, even if the input pulse period of the input pulse train signal changes, the output pulse train signal can be made to respond quickly and smoothly to the change.

  According to the frequency converter 1 of the above-described embodiment, when the frequency-divided pulse train signal is frequency-divided by the frequency dividing number m by the frequency divider 3, the output is inverted every time m / 2 pulses are counted. As a result, if the input pulse period is constant, the waveform of the output pulse train can be set to 50% duty ratio.

[Modification of Embodiment]
The present invention is not limited to the embodiment described above and shown in the drawings, and various modifications can be made without departing from the scope of the invention. In the above-described embodiment, the setting of the multiplication number N and the frequency division number m is individually set by the setting unit 4. However, the frequency conversion count R may be set by the setting unit 4. In that case, the CPU (counter control unit 14) determines the multiplication number N and the frequency division number m from the frequency conversion count R, and sets these values in the multiplication pulse output counter 13 and the frequency divider 3.

  In the present embodiment, the setting unit is provided as hardware. However, the value of the built-in nonvolatile memory may be rewritten using the communication function of the CPU (counter control unit 14).

  In this embodiment, the frequency divider is configured as independent hardware. However, the output pulse train signal is obtained by counting the number of multiplied pulses of the multiplied pulse train signal with a counter or software built in the CPU (counter control unit 14). May be generated.

It is a block diagram which shows the structure of 1st Embodiment of the frequency converter of this invention. It is explanatory drawing explaining the conversion from the input pulse train signal performed by 1st Embodiment of the frequency converter of this invention to the output pulse train signal. It is explanatory drawing which shows the output relationship of the input pulse and multiplication pulse in case the period of the input pulse which concerns on 1st Embodiment of the frequency converter of this invention is constant. It is explanatory drawing which shows the output relationship of an input pulse and a multiplication pulse when the period of the input pulse which concerns on 1st Embodiment of the frequency converter of this invention becomes short. It is explanatory drawing which shows the output relationship of an input pulse and a multiplication pulse when the period of the input pulse which concerns on 1st Embodiment of the frequency converter of this invention becomes long.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Frequency converter, 2 ... Multiplier, 3 ... Frequency divider, 4 ... Setting part, 11 ... Reference clock oscillator, 12 ... Counter for input period measurement, 13 ... Counter for multiplication pulse output, 14 ... Counter control part

Claims (8)

A multiplier that multiplies the input pulse train signal by an arbitrary multiplication number and converts it to a multiplied pulse train signal;
A frequency converter comprising: a frequency divider that divides the multiplied pulse train signal converted by the multiplier by an arbitrary frequency division number and converts the divided signal to an output pulse train signal. The multiplier is
An input period measuring counter for measuring an input pulse period of the input pulse train signal;
A counter control unit that calculates the multiplied pulse period by dividing the input pulse period measured by the input period measuring counter by the multiplication number;
The frequency converter according to claim 1, further comprising: a multiplied pulse output counter that generates a multiplied pulse for each multiplied pulse period calculated by the counter control unit and outputs a multiplied pulse train signal. The multiplier has a reference clock oscillator that outputs a reference clock having a predetermined frequency,
3. The frequency converter according to claim 2, wherein the input period measuring counter and the multiplied pulse output counter measure the input pulse period and the multiplied pulse period by counting the reference clock, respectively. . The output period in which the multiplied pulse based on the input pulse is output corresponds to the next input pulse cycle,
When the current input pulse period is shorter than the previous input pulse period, the counter control unit outputs based on the previous input pulse until the output period of the multiplied pulse based on the current input pulse is started. The number of multiplied pulses is subtracted from the multiplied number, and the value is added to the multiplied number to calculate a multiplied pulse change number. The frequency converter according to claim 2, wherein the multiplied pulse period is changed so as to be generated. The output period in which the multiplied pulse based on the input pulse is output corresponds to the next input pulse cycle,
When the current input pulse period is longer than the previous input pulse period, the counter control unit outputs the multiplied pulse based on the current input pulse after the output of the multiplied pulse based on the previous input pulse is completed. Before the period starts, a multiplied pulse is output with a multiplied pulse period based on the previous input pulse, and the number of multiplied pulses is calculated by subtracting the output number of multiplied pulses from the number of multiplied pulses. 3. The frequency converter according to claim 2, wherein the multiplication pulse period is changed so that the number of multiplication pulses is generated by the number of times of the multiplication pulse change during the output period of the multiplication pulse based on the frequency. Even if the output of the multiplication pulse based on the previous input pulse is completed, the output of the multiplication pulse based on the current input pulse is output even if the multiplication pulse of the multiplication number is output in the multiplication pulse cycle based on the previous input pulse. If the period is not started, the counter control unit determines that the input pulse is in a stopped state, and controls the multiplied pulse output counter to stop generation of the multiplied pulse of the multiplied pulse train signal. Item 6. The frequency converter according to Item 5. When the current input pulse period changes with respect to the previous input pulse period, the counter control unit performs the multiplication pulse based on the current input pulse after the output of the last multiplied pulse based on the previous input pulse is completed. The start time of the output period of the multiplied pulse based on the current input pulse is controlled so that the time until the start of the output period is equal to or greater than the multiplied pulse period calculated based on the previous input pulse. 6. The frequency converter according to claim 4 or 5, wherein: 2. The frequency converter according to claim 1, wherein the dividing period inverts the output every time the number of multiplied pulses of the multiplied pulse train signal reaches a value obtained by dividing the divided number by two.

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