JP7263859B2 - D/A converter, audio equipment, electronic musical instrument and D/A conversion method - Google Patents

Description

The present invention relates to a D/A conversion device, audio equipment, electronic musical instrument, and D/A conversion method.

For example, in the D/A converter provided in the output stage of an electronic musical instrument, the pulse width of the signal output obtained by delta-sigma conversion of oversampled digital value audio data is requantized by an analog integrator in the latter stage. It is removed and converted to a voltage signal for D/A conversion by a low-pass filter. The accuracy of the voltage signal in the direction of the time axis is directly linked to the conversion accuracy, so high accuracy is required.

The D/A conversion section generally has a configuration clock generator that uses a PLL (phase locked loop) circuit and a crystal oscillator, and the jitter components of these PLL circuits and the crystal oscillator are regarded as noise for the reasons described above. It becomes a factor that degrades the sound quality.

Jitter is known to have many components that fluctuate at a constant rate with respect to the cycle of the oscillation frequency. The time of the maximum value of the jitter component does not change due to the nature of digital circuits even if the oscillation frequency is divided. Therefore, if the frequency division ratio is increased and the speed is decreased, the jitter ratio of the clock will be decreased and the signal noise will be reduced. This means that by setting the pulse to a long period, the proportion of the constant jitter component is reduced and the noise component is relatively reduced.

On the other hand, however, when digital audio data is subjected to delta-sigma conversion, it is necessary to raise the operating frequency in order to further enhance the noise shaping effect.

Due to such conflicting requirements, it is difficult to determine how many times the sampling frequency Fs of the digital audio data should be set for the operating frequency when performing the ΔΣ conversion.

Techniques have been proposed for obtaining high-precision analog output that is less affected by noise and jitter in this type of DA converter using oversampling and noise shaping. (For example, Patent Document 1)

JP-A-05-037382

Techniques, including the techniques described in the above-mentioned patent documents, have been sought that can reliably reduce noise in analog signals obtained during D/A conversion.

The present invention has been made in view of the above-mentioned circumstances, and its object is to effectively utilize the output signal obtained by ΔΣ conversion and reduce noise without lowering the effect of noise shaping. It is an object of the present invention to provide a possible D/A conversion device, audio equipment, electronic musical instrument, and D/A conversion method.

One aspect of the present invention is a ΔΣ calculation circuit that performs ΔΣ calculation on data that is sequentially input, and a detection circuit that detects whether or not specific values are consecutive based on calculation results output from the ΔΣ calculation circuit. and, when the detection circuit detects that the specific value is discontinuous, a PWM signal is generated in a first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific value is continuous. a PWM signal generation circuit for generating a PWM signal in a cycle longer than the first PWM cycle and determined from among a plurality of cycles according to the degree of continuity of the specific value; Prepare.

According to the present invention, it is possible to effectively utilize an output signal obtained by ΔΣ conversion and reduce noise without lowering the effect of noise shaping.

1 is a block diagram showing the overall configuration of an electronic musical instrument using a D/A converter according to an embodiment of the invention; FIG. 4 is a timing chart showing waveform examples of a clock and a PWM signal according to the same embodiment; 4 is a timing chart showing waveforms of PWM signals output by an output unit 15C according to the embodiment; FIG. 2 is a block diagram showing the functional configuration of an arithmetic circuit included in the ΔΣ modulator according to the embodiment; The figure which shows the noise shaping frequency characteristic which graphed e (noise) which concerns on the same embodiment. FIG. 4 is a block diagram showing a configuration realized by a specific hardware circuit of the ΔΣ modulator according to the embodiment; FIG. 5 is a diagram showing the content of arithmetic processing in the ΔΣ modulator according to the embodiment in association with the count value of the m counter; FIG. 2 is a block diagram showing a specific circuit configuration of a shift register section according to the same embodiment; FIG. 2 is a block diagram showing a specific hardware circuit configuration of an output section and a D flip-flop according to the embodiment;

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of an electronic musical instrument using a D/A converter (DAC) according to this embodiment. In the figure, an operation signal from an operation unit 11 composed of, for example, a keyboard is input to the CPU 12 of the LSI chip CH1. The CPU 12 communicates with a ROM 13 storing operating programs and standard data for this electronic musical instrument, a tone generator 14 generating digital audio data corresponding to the contents of operations, and a DAC 15 via a bus B1 within the LSI chip CH1. Connected.

Furthermore, a crystal oscillator (Xtal) 16 and a PLL 17 are provided in the LSI chip CH1. The crystal oscillator 16 applies a constant voltage to the crystal oscillator CU1 externally attached to the LSI chip CH1 to oscillate the clock clk-xtal, which is the first clock that serves as a reference, to each circuit in the LSI chip CH1. and the PLL 17.

The PLL 17 receives the clock clk-xtal, oscillates the clock clk-pll, which is a second clock with a higher frequency, and supplies it to each circuit in the LSI chip CH1.

The CPU 12 transmits parameters such as pitch and volume to the sound source section 14 according to the operation signal received from the operation section 11 . The sound source section 14 receiving this outputs the corresponding digital audio data to the DAC 15 .

The DAC 15 has a ΔΣ modulator 15A, a shift register section 15B, an output section 15C, and a D flip-flop (DF/F) 15D.

The delta-sigma modulator 15A receives the digital audio data input from the sound source section 14, performs delta-sigma modulation based on the clock clk-pll from the PLL 17, and outputs quantized data, which is the calculation result, to the shift register section 15B.

The shift register unit 15B delays the quantized data from the ΔΣ modulator 15A by eight clocks clk-pll by an internal shift register and outputs the same data, such as duty cycle, to the output unit 15C. It is determined whether or not data with a ratio of 50[%] are continuous, and the determination results are combined and sent to the output unit 15C.

The output section 15C generates a balanced PWM signal according to the input quantized data and the determination result, and outputs it to the D flip-flop 15D.

The D flip-flop 15D waveform-shapes the balanced PWM signal output from the output section 15C based on the clock clk-pll from the PLL 17, and then outputs it to the low-pass filter 18 outside the LSI chip CH1.

The low-pass filter 18 uses, for example, a serial RC circuit as shown, converts the given PWM signal into an analog audio signal, and outputs it to an amplifier (amp) 19 . As for the amplifier 19, it is desirable to use a differential amplifier, as will be described later. When a differential amplifier is used as the amplifier 19, two series RC circuits are actually provided for balanced signals.

A loudspeaker 20 is driven by an analog audio signal amplified by an appropriate amplification factor in the amplifier 19 to emit sound.

FIG. 2 is a diagram illustrating the relationship between the clock clk-pll (FIG. 2(A)) oscillated by the PLL 17 and the PWM signal (FIGS. 2(B) to 2(D)) generated by the output section 15C. be.

It is assumed that the output section 15C operates so as to output a PWM signal with eight clocks of the clock clk-pll as one period of calculation.

PWM signals generated by the output section 15C are illustrated in FIGS. 2(B) to 2(D).

FIG. 2(B) shows a case where the "H" section of the PWM signal has a time width of 8 periods of the clock clk-pll.

Similarly, FIGS. 2(C) and 2(D) show the case where the "H" section of the PWM signal has a time width of 6 cycles and 4 cycles of the clock clk-pll.

As shown in these figures, the minimum change width of the PWM signal is temporally symmetric with respect to one period of the clock clk-pll as a unit for both the rising timing and the falling timing. Five levels of signal levels can be represented by eight clocks per period.

When the duty ratio of the PWM signal is 50[%], the content expressed as the audio signal is "0", ie, silence.

For example, if the ΔΣ modulator 15A operates at an oversampling frequency that is 32 times the sampling frequency Fs of the sound source, the output section 15C that converts the output of the ΔΣ modulator 15A into PWM has a frequency of 1/32 of the sampling frequency Fs. ”, the period of the output PWM signal can be extended.

FIG. 3 is a timing chart showing waveforms of the clock clk-pll and the PWM signal output from the output section 15C.

As shown in FIG. 3A, it is assumed that the ΔΣ modulator 15A operates with eight cycles of the clock clk-pll output from the PLL 17 as one basic operation cycle as shown in FIG. 3B.

Further, when the digital audio data input from the sound source unit 14 to the DAC 15 is temporally continuous and has content "0" indicating silence, it is detected based on the coincidence determination signal from the shift register unit 15B. As a result, the output unit 15C outputs 16 cycles of the clock clk-pll that is twice the basic cycle as shown in FIG. 3(C), and the clock clk- A PWM signal for 32 cycles of pll and 64 cycles of clock clk-pll, which is eight times the basic cycle as shown in FIG. 3(E), is output.

With reference to FIG. 4, a block diagram showing the functional configuration of the arithmetic circuit of the ΔΣ modulator 15A will be described.
In the figure, the ΔΣ modulator 15A includes a subtractor (−) 41, adders (+) 42, 44, 46, 47, 51, delay devices (Z ^-1 ) 43, 48, 52, 54, multipliers 45, 49 , 50 and a quantizer 53 .

The digital audio data input from the sound source section 14 is subtracted by the output of the delay device 54 that delays the output of the quantizer 53 in the subtractor 41 , and the difference is output to the adder 42 . The adder 42 adds the output z 0 of the delay device 43 that delays its own output, and outputs the sum to the delay device 43 , the adder 44 and the multiplier 45 .

Multiplier 45 multiplies the output of adder 42 by multiplier k 0 and outputs the product to adder 46 . Adder 46 adds the output of multiplier 45 and the output of multiplier 49 and outputs the sum to adder 47 .

The adder 47 adds the output of the adder 46 and the output z 1 of the delay device 48 that delays its own output, and outputs the sum to the delay device 48 , the adder 44 and the multiplier 50 . Multiplier 50 multiplies the output of adder 47 by multiplier k 1 and outputs the product to adder 51 .

The adder 51 adds the output of the multiplier 50 and the output z2 of the delay device 52 that delays its own output, and outputs the sum to the delay device 52 , the adder 44 and the multiplier 49 . Multiplier 49 multiplies the output of adder 51 by multiplier a 0 and outputs the product to adder 46 .

The adder 44 adds the outputs of the adders 42, 47 and 51 and outputs the sum to the quantizer 53 for quantization. Then, the output of the quantizer 53 is output to the next-stage shift register section 15B as the output of the ΔΣ modulator 15A, and is output to the delay device 54 as well. The delay device 54 delays the output of the quantizer 53 and applies the output z3 to the subtractor 41 as a subtrahend to apply negative feedback to the input.

When e is quantization noise, the characteristic of quantization e in the output y of the quantizer 53 is as shown in the following equation.

FIG. 5 is a graph showing the noise shaping frequency characteristics of e (noise) in the above formula. In the figure, the horizontal axis is the angular velocity, and the vertical axis is the noise signal level (quantization noise) [dB]. In the figure, if the required amount of noise shaping is -100 [dB], the audible band is in the range of about 0.06 (=1/16) of the angular velocity.

That is, the sampling rate Fsp of the noise shaper needs to be approximately 16 times the sampling frequency Fsd of the digital audio data.

FIG. 6 is a block diagram illustrating a case where the functional configuration of the arithmetic circuit shown in FIG. 4 is executed by a specific hardware circuit.
A clock clk-pll is input to the control unit 61 . The control unit 61 has an m counter (mcnt) 61A for counting the clock clk-pll inside, and controls the following circuits, specifically register latch enable, selector selection, and parameter selection. do

In addition to the control unit 61, the ΔΣ modulator 15A includes registers 62 and 63, selectors 64 to 66, a multiplier (MUL) 67, an adder (ADD) 68, a parameter constant generator 69, a quantizer 70, and a delay has registers 71A to 71D for

Digital audio data from the preceding tone generator 14 is input to the selector 66 . The selector 66 also receives the outputs of the selector 65 and the multiplier 67 , and outputs one value selected according to the control section 61 to the adder 68 .

The adder 68 also receives the value held in the register (AC) 62, and outputs the sum added according to the control unit 61 to the registers (z0 to z3) 71A to 71A to 71D and the selector 64.

The values held in the registers 71A-71D are input to the selector 65. FIG. The selector 65 selects one of the values held in the registers 71A to 71D under the control of the control section 61 and outputs the selected value to the selector 66 and the multiplier 67 .

The multiplier 67 multiplies the output of the selector 65 by one of the parameter constants k0, k1 and a0 supplied from the parameter constant generator 69 and outputs the product to the selector 66. FIG.

The selector 64 selects one of the output of the adder 68 and the output of the quantizer 70 (53) according to the control section 61 and causes the register (AC) 62 to hold it. The value held in register 62 is read out to quantizer 70 and adder 68 .

Then, the operation result of the ΔΣ operation unit 15B, which is output from the quantizer 70, is sent to the selector 64, while it is held in a register (DR) 63. 15B.

FIG. 7 is a diagram showing the content of arithmetic processing in the ΔΣ modulator 15A executed by the hardware circuit of FIG. The m counter 61A is a basic counter that controls the operation of the ΔΣ modulator 15A, and can take eight count values from "0" to "7".

The m-counter 61A is reset to "0" at each PWM cycle, then counts up by "+1" by the clock clk-pll, and after reaching the highest value "7", until it is reset, Holds the count value "7".
While the count value of the m-counter 61A is "7", the reset operation waits.

A brief description will be given of the calculation contents by the controller 61 in the ΔΣ modulator 15A corresponding to the count values "0" to "7" of the m counter 61A.

When the 0:m counter 61A is reset to "0", the delay value z3 held in the register 71D is selected by the selector 65, and the selection result of the selector 65 and the input data from the tone generator section 14 are sequentially selected by the selector 66. Let Each selection result is added by the adder 68 and the sum output is selected by the selector 64 and held in the register 62 .

In addition, the value held in register 62 is read out and output to quantizer 70 for quantization processing, and the output is output via register 63 to shift register section 15B in the next stage.

1: The selector 65 selects the delay value z0 held by the register 71A, and the selector 66 selects the selection result of the selector 65. The adder 68 adds the selection result of the selector 66 and the value held in the register 62, and the sum output is held in the register 71A.

In addition, the output of quantizer 70 is held in register 71D via selector 64, register 62 and adder 68. FIG.
2: The selector 65 selects the delay value z2 held by the register 71C, the parameter constant generator 69 outputs the parameter constant a0, and the multiplier 67 multiplies these two values. The obtained product is held in register 62 via selector 66 , adder 68 and selector 64 .

3: The selector 65 selects the delay value z0 held by the register 71A, the parameter constant generator 69 outputs the parameter constant k0, and the multiplier 67 multiplies these two values. Selector 66 selects the resulting product, and the value held in register 62 is read out and output to adder 68 . An adder 68 adds these two values, and the sum is again held in the register 62 via a selector 64 .

4: The selectors 65 and 66 select the delay value z1 held by the register 71B and output it to the adder 68, and the value held in the register 62 is read and output to the adder 68. The adder 68 adds these two values, and the sum is stored again in the register 71B.

5: The selector 65 selects the delay value z1 held by the register 71B, the parameter constant generator 69 outputs the parameter constant k1, and the multiplier 67 multiplies these two values. The obtained product is held in register 62 via selector 66 , adder 68 and selector 64 .

6: The delay value z2 held by the register 71C is selected by the selectors 65 and 66 and output to the adder 68, and the value held in the register 62 is read and output to the adder 68; The adder 68 adds these two values, and the sum is stored again in the register 71C.

7: The delay values z0 to z2 held by the registers 71A to 71C are sequentially selected by the selectors 65 and 66 and output to the adder 68 serially. Adder 68 adds these three values, and the sum is held in register 62 via selector 64 .

In this manner, the ΔΣ arithmetic processing is executed as described above according to the count value mcnt of the m counter 61A which is reset every PWM cycle and counts according to the clock clk-pll.

FIG. 8 is a block diagram showing a specific circuit configuration of the shift register section 15B that delays the output of the ΔΣ modulator 15A.

The shift register section 15B has a shift register composed of eight stages of 3-bit D flip-flops 81A-81H and 0 comparators 82-84. The output of the ΔΣ modulator 15A is output to the subsequent output section 15C via D flip-flops 81A-81H. A ΔΣ cycle clock is supplied from the ΔΣ modulator 15A to the D flip-flops 81A to 81H as an operation clock.

Each output of the eight stages of D flip-flops 81A to 81H forming the shift register is output to the 0 comparator . Furthermore, each output of the rear four stages of D flip-flops 81E to 81H is output to the 0 comparator 83. FIG. In addition, each output of the last two stages of D flip-flops 81 G and 81 H is output to the 0 comparator 84 .

The 0 comparator 82 outputs an 8-level match signal to the output section 15C when the outputs of the D flip-flops 81A to 81H are all "0". Similarly, the 0 comparator 83 outputs a quaternary match signal to the output section 15C when the outputs of the D flip-flops 81E to 81H are all "0". The 0 comparator 84 outputs a binary match signal to the output section 15C when the outputs of the D flip-flops 81G and 81H are both "0".

In the shift register section 15B, a delay of 8 PWM cycles is generated in the process of signal transmission by having the shift register composed of the above-described 8 stages of D flip-flops 81A to 81H.

However, in this embodiment, it is assumed that audio data oversampled by a factor of 32 is handled. , a delay of about 5.67 [μsec] (=1/(44.1×10 ³ ×(32/8))) occurs, which is a very small amount of time that does not affect human perception. Therefore, no problem occurs in practice.

FIG. 9 is a block diagram showing a specific hardware circuit configuration of the output section 15C and the D flip-flop 15D.

The output unit 15C includes an n counter 91 that counts according to the clock clk-xtal, decoders 92A to 92H that decode the count value of the n counter 91, a first selector 93, a second selector 94, a third selector 95, and a fourth selector. It has a selector 96 .

Based on the count value of the n counter 91, the decoders 92A to 92E have pulse widths of 0 [%], 25 [%], 50 [%], 75 [%] and 100 [%] in normal PWM cycles. A pulse signal is output to the first selector 93 .

Based on the count value of the n-counter 91 , the decoder 92</b>F outputs to the second selector 94 a pulse signal having a cycle twice the normal PWM cycle and a pulse width of 50[%].

Based on the count value of the n-counter 91, the decoder 92G outputs to the third selector 95 a pulse signal having a cycle four times the normal PWM cycle and a pulse width of 50[%].

Based on the count value of the n-counter 91, the decoder 92H outputs to the fourth selector 96 a pulse signal having a cycle eight times the normal PWM cycle and a pulse width of 50[%].

The first selector 93 selects one of the pulse signals output from the decoders 92A to 92E and outputs it to the second selector 94 according to the FIFO signal given at the latch timing.

The second selector 94 selects a pulse signal with a double cycle pulse width of 50[%] output from the decoder 92F when there is a binary match signal from the preceding shift register section 15B, When there is no match signal, the normal period pulse signal output from the first selector 93 is selected and output to the third selector 95 .

The third selector 95 selects a pulse signal with a quadruple cycle pulse width of 50[%] output from the decoder 92G when there is a quaternary match signal from the shift register section 15B in the previous stage. If there is no match signal, the pulse signal selected by the second selector 94 is selected and output to the fourth selector 96 .

The fourth selector 96 selects the 8-fold period pulse signal with a pulse width of 50[%] output from the decoder 92H when there is an 8-level match signal from the shift register section 15B in the previous stage. If there is no match signal, the third selector 95 selects the pulse signal selected and outputs the non-inverted signal to the D flip-flop 97 and the inverted signal to the D flip-flop 98 .

The D flip-flops 97 and 98 are arranged in two stages to obtain a balanced output to form the D flip-flop 15D. and

In the configuration of the shift register section 15B and the output section 15C described above, first, in the shift register section 15B that delays the output of the ΔΣ modulator 15A by 8 cycles of the normal PWM cycle, the 0 comparators 82 to 84 output a specific signal , here, whether or not "0" indicating silence continues eight times, four times, or two times is detected, and a match signal is output to the DAC 15 when a match is detected.

In the output unit 15C, when silence does not continue as a result of the ΔΣ calculation, the first selector 93 selects one of the signals of the decoders 92A to 92E according to the normal PWM period, and the second selector 94 and the third selector 95, operates to output to the D flip-flop 15D via the fourth selector 96;

On the other hand, if silence continues as a result of the ΔΣ calculation, the shift register section 15B outputs a binary match signal from the 0 comparator 84 and a 4-level match signal from the 0 comparator 83 according to the degree of continuity. , 0 comparator 82 outputs an 8-level match signal.

In the output unit 15C, the selectors 93 to 96 are configured so as to preferentially select when the period of continuous silence is longer. A PWM signal with a duty ratio of 50% for two, four, or eight cycles of the normal PWM cycle shown in FIGS. A corresponding signal is selected and output to the D flip-flop 15D.

In the D flip-flop 15D, waveform shaping is performed in the process of latching the selected output of the sound source section 14 by the clock clk-pll, and the output is output as balanced positive and negative outputs.

The outputs of these D flip-flops 15D are output to amplifier 19 as analog audio signals via low-pass filters 18, respectively. The amplifier 19 is composed of a differential amplifier as described above, amplifies the analog audio signal with a given amplification factor according to the difference between the normal signal and the inverted signal, and causes the speaker 20 to emit sound.

Many of the noise components superimposed on the signal in a series of digital processing and the wiring transmission line are similarly superimposed on the normal signal and the inverted signal, and by configuring the amplifier 19 with a differential amplifier, only the difference between the signals is amplified. By doing so, in-phase noise components can be canceled and removed.

As described in detail above, according to the present embodiment, the output signal obtained by the ΔΣ conversion is effectively utilized, and when predetermined ΔΣ conversion results are consecutive, noise can be reduced without lowering the effect of noise shaping. becomes possible.

Further, in the present embodiment, when predetermined ΔΣ conversion results are continuous, a plurality of cycles, for example, 2 cycles, 4 cycles, and 8 cycles of PWM signals are generated according to the degree of continuity. Therefore, it is possible to efficiently reduce noise by adapting to the content of the signal.

More specifically, with respect to the standard PWM cycle, it is about -3 [dB] when using a PWM signal of 2 cycles, about -6 [dB] when using a PWM signal of 4 cycles, and about -6 [dB] when using a PWM signal of 8 cycles. It should be noted that a noise reduction effect of about -9 [dB] was obtained by experiment when the PWM signal was used.

It should be noted that the present invention is not limited to the above-described embodiments, and can be variously modified in the implementation stage without departing from the gist of the invention. Moreover, each embodiment may be implemented in combination as much as possible, and in that case, the combined effect can be obtained. Furthermore, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriate combinations of a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, the problems described in the column of problems to be solved by the invention can be solved, and the effects described in the column of effects of the invention is obtained, the configuration from which this constituent element is deleted can be extracted as an invention.

The invention described in the original claims of the present application is appended below.
[Claim 1]
a delta-sigma calculation circuit that performs a delta-sigma calculation on sequentially input data;
a detection circuit that detects whether or not specific values are continuous based on the calculation result of the ΔΣ calculation circuit;
When the detection circuit detects that the specific value is discontinuous, the PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific value is continuous. a PWM signal generating circuit that generates a PWM signal with a period longer than the first PWM period;
A D/A conversion device comprising:
[Claim 2]
The PWM signal generation circuit generates a PWM signal in a second PWM period that is twice as long as the first PWM period when detecting that the specific value continues twice.
The D/A conversion device according to claim 1.
[Claim 3]
The PWM signal generation circuit generates a PWM signal in a third PWM period that is four times as long as the first PWM period when detecting that the specific value continues four times.
3. The D/A converter according to claim 1 or 2.
[Claim 4]
The PWM signal generation circuit generates a PWM signal in a fourth PWM period eight times as long as the first PWM period when detecting that the specific value continues eight times.
4. The D/A conversion device according to claim 1.
[Claim 5]
The specific value is a value indicating 0,
5. The D/A converter according to claim 1.
[Claim 6]
a D/A conversion device according to any one of claims 1 to 5;
a speaker that produces sound based on the PWM signal generated by the D/A conversion device;
Acoustic equipment with
[Claim 7]
a D/A conversion device according to any one of claims 1 to 5;
A control for specifying the pitch,
a speaker that produces sound based on the PWM signal generated by the D/A conversion device in response to a user operation on the operator;
electronic musical instrument.
[Claim 8]
to the computer of the electronic musical instrument,
ΔΣ operation is performed on sequentially input data,
Detecting whether or not specific values are continuous based on the result of the ΔΣ calculation,
When it is detected that the specific value is discontinuous, a PWM signal is generated in a first PWM cycle indicating a ΔΣ calculation cycle, and when it is detected that the specific value is continuous by the detection, the first PWM signal is generated. generating a PWM signal with a period longer than the PWM period of
D/A conversion method.

11 operation unit,
12 CPU,
13 ROM,
14... sound source section,
15 DACs,
15A...ΔΣ modulator,
15B... shift register section,
15C... output part (PWM),
15D...D flip-flop (DF/F),
16... crystal oscillator (Xtal),
17 PLL,
18 ... low-pass filter,
19... amplifier (amp.),
20... speaker,
41 ... Subtractor (-),
42, 44, 46, 47, 51...adders (+),
43, 48, 52, 54... delay device (Z ^-1 ),
45, 49, 50...multipliers,
53 Quantizer,
61 ... control unit,
61A...m counter (mcnt),
62... register (AC),
63... register (DR),
64 to 66 selectors,
67 Multiplier (MUL),
68 Adder (ADD),
69 ... parameter constant generator,
70 Quantizer,
71A to 71D... registers,
81A to 81H...D flip-flops (DF/F),
82-84...0 comparators,
91...n counter,
92A to 92H Decoders,
93... first selector,
94... second selector,
95 ... third selector,
96 ... fourth selector,
97, 98...D flip-flops,
B1... bus,
CH1... LSI chip,
CU1... Crystal oscillator.

Claims (8)

a delta-sigma calculation circuit that performs a delta-sigma calculation on sequentially input data;
a detection circuit that detects whether or not specific values are consecutive based on the calculation results output from the ΔΣ calculation circuit;
When the detection circuit detects that the specific value is discontinuous, the PWM signal is generated in the first PWM cycle indicating the ΔΣ calculation cycle, and the detection circuit detects that the specific value is continuous. a PWM signal generating circuit that generates a PWM signal in a cycle longer than the first PWM cycle and determined from among a plurality of cycles according to the degree of continuity of the specific value;
A D/A conversion device comprising: The PWM signal generation circuit generates a PWM signal in a second PWM period that is twice as long as the first PWM period when detecting that the specific value continues twice.
The D/A conversion device according to claim 1. The PWM signal generation circuit generates a PWM signal in a third PWM period that is four times as long as the first PWM period when detecting that the specific value continues four times.
3. The D/A converter according to claim 1 or 2. The PWM signal generation circuit generates a PWM signal in a fourth PWM period eight times as long as the first PWM period when detecting that the specific value continues eight times.
4. The D/A conversion device according to claim 1. The specific value is a value indicating 0,
5. The D/A converter according to claim 1. a D/A conversion device according to any one of claims 1 to 5;
a speaker that produces sound based on the PWM signal generated by the D/A converter;
Acoustic equipment with a D/A conversion device according to any one of claims 1 to 5;
A control for specifying the pitch,
a speaker that produces sound based on the PWM signal generated by the D/A conversion device in response to a user operation on the operator;
electronic musical instrument. to the computer of the electronic musical instrument,
ΔΣ operation is performed on sequentially input data,
detecting whether or not the specific values output from the results of the ΔΣ calculation are continuous;
When it is detected that the specific value is discontinuous, a PWM signal is generated in a first PWM cycle indicating a ΔΣ calculation cycle, and when it is detected that the specific value is continuous by the detection, the first PWM signal is generated. generating a PWM signal with a period longer than the PWM period of and determined from among a plurality of periods according to the degree of continuity of the specific value;
D/A conversion method.

Images