JPH04115722A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce noise at non-signal by detecting the presence of a signal as an input of a noise shaper and stopping a dither function when no signal exists so as to clear the data in the noise shaper. CONSTITUTION:When a detection circuit 30 detects the absence of a digital signal based on an output A of a filter 10, a detection output NS goes to 1 and a control switch 32 is in off-control and a data in a noise shaper 16 is cleared. When the switch 32 is in the off-state, the addition of an AC waveform signal D is stopped by an adder 12, an output A1 of the adder 12 reaches a non-signal state and all the data in the noise shaper 16 are cleared. Thus, even when the noise shaper 16 makes feedback operation, the content of the register always keep the same zero state, the noise included in the output is minimized. When the circuit 30 detects the presence of the digital signal based on the output A of the filter 10, a detection output NS goes to 0, the switch 32 is turned on and the noise shaper 16 is acted normally.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a DA conversion device using oversampling technology and noise shaving (delta sigma modulation) technology, and particularly relates to a technology for preventing limit cycles in a noise shaver. It is something.

[Summary of the Invention] The present invention provides a circuit for adding a digital AC waveform signal to a human-powered digital signal of a noise shaper to prevent a limit cycle in the noise shaper. The presence of the signal is detected, and when there is no signal, the addition of the AC waveform signal is stopped and the data in the noise shaver is cleared, thereby reducing noise when there is no signal.

[Prior Art] Conventionally, as a DA conversion device using oversampling technology and noise shaving technology, the one illustrated in FIG. 5 has been proposed.

In FIG. 5, lO is a digital filter that oversamples the multi-bit digital manual DI;
12 is an adder that receives the multi-bit digital signal A from the filter 10 as one input; 14 is an adder that supplies a digital AC waveform signal to the adder 12 as the other input; dither 16 is an addition unit for the adder 12; A noise shaper (delta-sigma modulator) that transmits a digital signal B with a reduced number of bits by delta-sigma modulating (differential-integral processing) the multi-bit digital signal A1 as an output; 18 is the digital signal B from the noise shaper 16; 20 is a clock generator that generates a system clock signal φ5 having a frequency fs, 22
is a low-pass filter (
LPF).

- The circuit section indicated by the dot-dashed line IC is configured as a monolithic or hybrid integrated circuit and is arranged in one package, and 20A is the clock generator 20.
This is a crystal resonator that is externally attached to the In some cases, the digital filter 10 and its related parts (the part surrounded by broken lines) are also integrated into an integrated circuit.

The digital human DI is - for example 16 for each sample.
Waveform data containing bit (1 word) data,
The data transmission frequency is 44.1 Hz. Further, the frequency of the system clock signal φ8 is 16.9 MHz, and the data sending frequency from the digital filter 10 to the noise shaper 16 is normally fs/2 (for example, 8.45 MHz).
MHz).

The noise shaper 16 is provided to lower the oversampling frequency in oversampling frequency conversion. When a primary or secondary noise shaper is used as the noise shaper 16, pulse density modulation (pit stream) is used as the noise shaper output B.
An output is obtained, and when a third-order or higher-order noise shaper is used, a pulse width modulated output is obtained as output B.

In the noise shaper 16, the digital signal is converted into a representation with a lower number of bits, but the error caused by such conversion becomes noise, and while the high frequency region becomes louder, the noise within the audible frequency band of interest is not satisfied. becomes low enough. That is, FIG. 6 shows the noise shaper 1
6 shows the power spectrum of the ideal output of No. 6, in which the noise power due to noise shaving is maximum in the high frequency region near f*/2. Furthermore, the monochromatic sharp power component P in the low frequency region is obtained when a sine wave is given to the human-powered digital signal component, and the power component Pb is due to the system clock signal φ. .

The noise shaper output B has various noises added to the ideal state due to fluctuations during digital processing, so if the output B is directly converted into an analog output by the LPF 22, errors will occur due to noise components. Therefore, the noise shaper output B is waveform-shaped by the waveform shaping circuit 18 based on the system clock signal φ9 and then supplied to the LPF 22 to reduce errors caused by noise components.

Adder 12 and dither 14 are provided to prevent limit cycles from occurring in noise shaper 16. The noise shaper 16 is composed of, for example, a first-order delta-sigma modulator as shown in FIG.
As the process is repeated, the output data is negatively fed back to the input side, and the contents of the register in the integrator change accordingly. When a digital signal corresponding to a DC level is input as a noise shaver human power, the contents of the register change at a repetition frequency corresponding to the DC level, and an AC appears at the output. This AC is called a limit cycle or idling pattern. be. The frequency of the limit cycle is lower as the DC level is smaller, and a very small DC level may fall into the audible frequency band. The limit cycle is DA
This is detrimental to the conversion since it adds unnecessary oscillations to the output.

In the circuit shown in Figure 5, in order to prevent limit cycles,
The adder 12 dithers the digital signal A.
The AC waveform signal from 14 is added to disturb the DC component, thereby preventing the energy of the limit cycle from concentrating on one frequency. As an AC waveform signal, the frequency is -12 to -2 at a frequency of about 200 to 600 KHz.
It is common to use a square wave signal with a level of about 0 dB.

[Problems to be Solved by the Invention] According to the conventional limit cycle prevention technology described above, an AC waveform signal is applied to the adder 12 even when there is no input signal, and this signal is output as the addition output A1. The signal is supplied to the noise shaver 16. Therefore, the noise in the output of the noise shaper 16 increases, and the S/N when there is no signal increases.
It was difficult to obtain a ratio of 120 dB or more.

An object of the present invention is to reduce noise when there is no signal in an oversampling type DA converter as described above.

[Means for solving the problem] The present invention provides an oversampling type D as described above.
The A converter includes a detection means for detecting the presence or absence of a digital signal to which an AC waveform signal for limit cycle prevention should be added, and a detection means for detecting the presence or absence of a digital signal to which an AC waveform signal for limit cycle prevention is added, and detecting the presence or absence of the AC waveform signal in response to the detection output of the detection means indicating no signal. and control means for stopping the addition and clearing the data in the noise shaver, and restarting the addition of the AC waveform signal in response to the detection output of the detection means indicating the presence of a signal. This is a characteristic feature.

In such a configuration, the control means gradually decreases the amplitude value of the AC waveform signal when stopping the addition of the AC waveform signal, and decreases the amplitude value of the AC waveform signal when restarting the addition of the AC waveform signal. It may be configured to gradually increase the value.

[Operation] According to the configuration of the present invention, when the digital signal becomes a no-signal state, the control means stops adding the AC waveform signal and clears the data in the noise shaper based on the detection output from the detection means. . Therefore, even if a feedback operation is performed within the noise shaper, the contents of the register will always be in the zero state, and the noise will be minimal.

Thereafter, when the digital signal becomes a signal state, the control means resumes addition of the AC waveform signal in accordance with the detection output from the detection means. Therefore, even if a digital signal corresponding to a DC level is input manually, a limit cycle will not occur.

In addition, as described above, if the amplitude value of the AC waveform signal is gradually changed and controlled when the addition of the AC waveform signal is stopped and restarted, it is possible to avoid noise generation due to the on/off of the dither operation, and to reduce the Noise reduction can be achieved.

[Embodiment] FIG. 1 shows a limit cycle prevention circuit according to an embodiment of the present invention, and the same parts as in FIG. 5 are given the same reference numerals and detailed explanations are omitted.

The circuit shown in Figure 's1 is characterized by the provision of a no-signal detection circuit 30 that receives the output A of the digital filter IO as an input, and a control switch 32 provided in the path of the AC waveform signal. The control switch 32 and the noise shaper 16 are controlled according to the NS.

When the detection circuit 30 detects the absence of a digital signal based on the output A of the filter 10, the detection output NS becomes "1", and accordingly, the control switch 32 is turned off and the data in the noise shaver 16 is cleared. be done.

The noise shaper 16 consists of a first-order delta-sigma modulator, as shown in FIG. Second
In the figure, 16A is an adder that uses the output of adder 12 as one input, 16B is an integrator that uses the output of adder 16A as input, and 16C determines whether the output of integrator 16B is positive or negative and performs 1-bit quantization. The quantizer 16D is a delay element that delays the output (noise shaper output) of the quantizer 16C by one sampling time and supplies it to the adder 18A as the other input. Here, the adder 16A and the integrator 16B each include a register of a predetermined number of bits, and the delay element 16D is constituted by a D flip-flop or the like having a data holding function. Therefore, in order to clear the data in the noise shaper 16, it is sufficient to clear the register of the adder 16A, the register of the integrator 16B, the D flip-flop of the delay element 16D, etc. in response to the detection output NS="1".

When the control switch 32 is turned off, the adder 12 stops adding the AC waveform signal, so the output A+ of the adder 12 (that is, the noise shaper's input) becomes a no-signal state. At this time, all data in the noise shaver 16 is cleared as described above. Therefore, even if the noise shaper 16 performs a feedback operation, only zero information is returned, and the contents of the register always remain in the same zero state. That is, the noise shaper 16 is in a state equivalent to not operating internally, and the noise included in the output is minimal, so the S/N ratio when there is no signal is the best.

When the detection circuit 30 detects the presence of a digital signal based on the output A of the filter IO, the detection output NS becomes "0", and accordingly the control switch 32 is turned on and the noise shaper 16 is enabled to operate normally. As a result,
Since the digital signal input to the noise shaper is mixed with the AC waveform signal from the dither 14 by the adder 12, a limit cycle does not occur in the noise shaper 16 even when a digital signal corresponding to the DC level arrives. .

In the circuit shown in FIG. 1, instead of providing the control switch 32, the operation of the dither 14 may be controlled to be turned off or turned on depending on whether the detection output NS is "1" or "0".

FIG. 3 shows a limit cycle prevention circuit according to another embodiment of the present invention, which differs from that of FIG. The structure is different from that shown in FIG.

When the detection circuit 30 detects the absence of a digital signal based on the output A of the filter 10, for example at the timing tl in FIG. Give a down count command to. Therefore, the counter 42 is 1J
Down counting of the pulses CP from the pulse generator 44 of No. 1 is started from the timing of tl. The counter 42 is a 6-bit one in which the most significant bit is a sign bit (+="0"), and the counted value is r as shown in FIG.
ollllll'' to ro OOO00J. Note that all data in the noise shaver 16 is cleared in response to the detection output NS-"1", as described in FIGS. 1 and 2.

When the counted value of the counter 42 reaches the minimum value rooooooOJ at timing t2 in FIG. 4, for example, the counting control circuit 40 detects this and gives a counting stop command to the counter 42. Therefore, the counter 42 stops with a count value of zero.

Incidentally, while the counter 42 is counting down, the count output CNT is supplied to the sign inverting circuit 50 or the OR circuit 52 via the control switch 46. Here, control switch 4
Reference numeral 6 indicates a contact point a or b which is switched in accordance with 1" or 0" of the dither pulse DP generated from the second pulse generator 48 at a period corresponding to the dither frequency, and the contact point a is switched to The count output CNT is supplied to the OR circuit 50 as it is, and the count output CNT is supplied to the OR circuit 52 via the contact and the sign inversion circuit 50 with the sign inverted (rl
0OOOOJ~rl 11111J). Therefore, the output of the OR circuit 52 is:
! As shown in the interval between t and t2 in Figure S4, a digital AC waveform signal DS whose value gradually decreases from the maximum positive and negative values ±M to the minimum value 0 is obtained, and this signal D
S is supplied to adder 12. Gradually decreasing the amplitude value of the AC waveform signal DS in this way reduces noise when the dither function is turned off, compared to the case where it decreases rapidly as shown in FIG.

When the detection circuit 30 detects the presence of a digital signal based on the output A of the filter IO at the timing t in FIG. Give up count command. Therefore, the counter 42 starts counting up the pulse CP from the timing t3, and the count value is ro
It changes from OOOOOJ to rollllllJ.

When the counted value of the counter 42 reaches the maximum value ro11111J at timing t4 in FIG. 4, for example, the counting control circuit 40 detects this and gives a counting stop command to the counter 42. Therefore, the counter 42 stops at the maximum count value.

During up counting of the counter 42 as described above, the count output CNT is switched and supplied to the sign inverting circuit 50 or the OR circuit 52 by the control switch 46 as in the case of down counting, and the output of the sign inverting circuit 50 is also supplied to the OR circuit. 52. Therefore, the output of the OR circuit 52 is a digital AC waveform signal DS whose value gradually increases from 0 to the maximum positive/negative value ±M as shown in the interval t to t4 in FIG. is obtained, and this signal DS is supplied to the adder 12. Gradually increasing the amplitude value of the AC waveform signal DS in this way reduces noise when the dither function is turned on, compared to the case where it increases rapidly as shown in FIG.

In FIG. 4, before tl or after t4, a normal dither function is obtained by the AC waveform signal DS having a constant amplitude corresponding to the maximum count value of the counter 42. Also, t2
In the interval from t3 to t3, the level of the signal DS is zero corresponding to the minimum count value of the counter 42, and the dither function is in a stopped state. Note that the counter 42 does not necessarily have to detect the minimum value or the maximum value and stop it, but can set an appropriate upper limit value or lower limit value corresponding to the desired maximum or minimum amplitude level of the signal DS, and set the appropriate upper limit value or lower limit value. It may also be possible to detect the value and stop the process.

In the circuit of FIG. 3, pulse generators 44 and 48 are
The clock signal φS from the clock generator 20 shown in FIG. 5 may be divided by a frequency dividing circuit to generate pulses.

[Effects of the Invention] As described above, according to the present invention, the presence or absence of a digital signal as an input to the noise shaper is detected, and when there is no signal, the dither function is stopped and the data in the noise shaper is cleared. As a result, it is possible to significantly reduce the noise contained in the output of the noise shaper when there is no signal, and to improve the S/N ratio to 120 dB or more when there is no signal.

Furthermore, if the amplitude value of the AC waveform signal for limit cycle prevention is gradually changed and controlled when the dither function is turned on/off, the noise accompanying the on/off operation can be reduced, making it possible to reduce the noise in the − layer. You can also get the following effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a limit cycle prevention circuit according to an embodiment of the invention, FIG. 2 is a circuit diagram showing an example of the configuration of a noise shaper 16, and FIG. 3 is a circuit diagram showing another embodiment of the invention. 4 is a waveform diagram showing changes in the value of the dither output DS, FIG. 5 is a block diagram showing a conventional DA converter, and FIG. 6 is a noise shaper. 7 is a graph showing the power spectrum of output B. 10...Digital filter, 12...Adder, 1
4゜14A...Dither-16...Noise shaper,
18... Waveform shaping circuit, 20... Clock generator,
22...Low pass filter, 30...No signal detection circuit, 32.46...Control switch, 40...Counting control circuit, 42...Up/down counter, 50...Sign inversion circuit.

Claims (1)

[Claims] 1. (a) A noise shaver that transmits a digital signal with a reduced number of bits by performing delta-sigma modulation on an oversampled multi-bit digital input; (b) Limits in this noise shaver summing means for adding an alternating current waveform signal in digital form to a digital signal as an input of the noise shaver to prevent cycles; (c) converting the digital signal from the noise shaver into an analog output corresponding to the digital input; (d) a detection means for detecting the presence or absence of a digital signal to which the AC waveform signal should be added, and (e) a detection output of the detection means indicating the absence of a signal; Control that responds to stop the addition of the AC waveform signals, clears the data in the noise shaver, and resumes the addition of the AC waveform signals in response to the detection output of the detection means indicating the presence of a signal. What is claimed is: 1. A DA conversion device comprising: means. 2. The control means gradually decreases the amplitude value of the AC waveform signal when stopping the addition of the AC waveform signal, and gradually decreases the amplitude value of the AC waveform signal when restarting the addition of the AC waveform signal. 2. The DA conversion device according to claim 1, wherein the DA conversion device is configured to increase the number of signals.