JP6371646B2 - Feedback type pulse width modulator - Google Patents

Description

  The present invention relates to a feedback type pulse width modulator, and more particularly to improvement of its resolution.

  Feedback type pulse width A / D converters are widely used in various measuring instruments as high-precision A / D converters.

  4A and 4B are block diagrams showing an example of a conventional feedback type pulse width modulation device. FIG. 4A is a detailed configuration diagram, and FIG. 4B is a schematic configuration diagram of FIG. In FIG. 4, the feedback type pulse width modulation apparatus generally includes a clock generation that outputs a feedback type pulse width modulator (hereinafter also referred to as PWM) 10, a counter 20, a digital filter 30, and a clock pulse fCLK having a predetermined frequency. And a carrier wave generator 50 for outputting a predetermined rectangular wave EC.

  FIG. 4 is a block diagram showing an example of a conventional feedback pulse width modulator. An input signal is input to one input terminal of the adder 1, and an output signal of the comparator 3 is input as a feedback signal to the other input terminal via the level converter 5, and an integration connected to the output terminal. The value obtained by subtracting the feedback signal from the input signal is output to the device 2.

  The integrator 2 integrates a value obtained by subtracting the feedback signal from the input signal, and inputs the integration result to one input terminal of the comparator 3. The output terminal of the triangular wave generator 4 is connected to the other input terminal of the comparator 3.

  The comparator 3 compares the output value of the integrator 2 with the triangular wave output from the triangular wave generator 4 to obtain a binarized output signal. The frequency of the binarized output signal matches the frequency of the triangular wave output from the triangular wave generator 4. However, the output level of the integrator 2 is in the range from the minimum value to the maximum value of the triangular wave.

  The duty ratio of the binarized signal output from the comparator 3 changes according to the output value of the integrator 2. The correspondence relationship between the duty ratio of the output signal of the comparator 3 and the output value of the integrator 2 is substantially linear. Hereinafter, the output signal of the comparator 3 is also referred to as a pulse width modulation (PWM) signal.

  The PWM signal output from the comparator 3 is converted to a predetermined level by the level converter 5 and input to the adder 1 as a feedback signal. The level converter 5 outputs the upper limit value of the input range when the PWM signal is “logic 1”, and outputs the lower limit value of the input range when it is “logic 0”. The average value of the feedback signal is a value between the lower limit value and the upper limit value of the input range because the feedback signal linearly corresponds to the duty ratio (0 to 100%) of the PWM signal.

  As described above, since the feedback signal is subtracted from the input signal, a negative feedback path is configured as the entire circuit of FIG.

  In such a configuration, if the feedback system is stable and the error of the level converter 5 can be ignored, errors such as the offset, amplitude, and nonlinearity of the triangular wave output from the triangular wave generator 4 and the comparator 3 Errors such as the offset and the rise / fall delay time difference are corrected by the negative feedback effect.

  Further, at the time of transition of the feedback signal, an error is likely to occur due to fluctuation of the amplitude of the feedback signal due to the mixing of noise accompanying switching, but the pulse density modulation (binary ΔΣ modulation) having the same configuration as the pulse width modulation (PWM) is used. Compared to the frequency of switching can be reduced, it is easy to improve accuracy.

The stable operation of the feedback system will be described with reference to the timing chart of FIG.
Since the PWM signal shown in (c) outputted from the comparator 3 is fed back to the adder 1 on the input side, the output signal of the integrator 2 fluctuates as shown by a one-dot chain line in (b).

  When the slope of the output signal of the integrator 2 shown in (b) is smaller than the slope of the triangular wave shown in (a), a normal PWM signal is obtained as shown in (c). .

  On the other hand, when the slope of the output signal of the integrator 2 shown in (b) is larger than the slope of the triangular wave shown in (a), the feedback system oscillates and a PWM signal cannot be obtained. The output signal of the integrator 2 has the maximum slope on the rising side when the input of the integrator 2 is maximum.

  This is the case when the input signal is slightly below the upper limit of the input range and the PWM signal is logic 0, that is, the feedback signal is the lower limit of the input range.

When the maximum input of the integrator 2 is obtained,
(Integrator input) = (Input signal)-(Feedback signal)
Because
(Maximum integrator input) = (Upper limit of input range)-(Lower limit of input range)
(Maximum integrator input) = (Input span)
It becomes.

The slope at this time, that is, (the maximum slope) is 1 / T _i (transfer function is 1 / (sT _i )).
(Maximum slope of integrator output) = (Input span) / _Ti
become.
For stable PWM operation (minimum triangular wave slope) is
(Minimum slope of triangle wave) = (Input span) / _Ti
It is.
The conditions for stable operation when the output of the integrator 2 is on the falling side are the same as those on the rising side, except that the slope is negative.

If the carrier frequency of the PWM signal is f _pwm , its period T _PWM is
T _PWM = 1 / f _PWM
It becomes.
When the rise time and fall time of the triangular wave are set equal to 0.5 × T _PWM and the (amplitude _pp minimum value of the triangular wave) is calculated,
(Triangular wave amplitude _pp minimum value) = 0.5 x (input span) x (T _PWM / _Ti )
become.

Here, with respect to the amplitude of the aforementioned triangular wave, an approximate value f _t of “gain crossing frequency” at which | path gain | is 1 is obtained in order to examine the stability of the feedback path.

When the input signal of the comparator 3 is a direct current without pulsation, when the input of the comparator 3 changes by (amplitude _{pp of the} triangular wave), the duty ratio of the PWM signal changes from 0 to 100%, and the level converter 5 The direct current component of () changes by (input span).

From this, the gain from the input of the comparator 3 to the output of the level converter 5 can be approximated,
(Gain from comparator input to level converter output) = (Input span) / (Triangle wave amplitude _pp )
It becomes.

In particular, when the amplitude of the triangle wave is (minimum amplitude _{pp of the} triangle wave), it does not depend on (input span),
(Gain from comparator input to level converter output) = 2 x (T _i / T _PWM )
It becomes.
Using this gain and the integrator transfer function 1 / (sT _i ),
(Circular transfer function) = 2 × (T _i / T _PWM ) × 1 / (sT _i )
= 2f _PWM / s
become.

The round frequency response is s = j2πf.
(Circular frequency response) = f _PWM / (jπf)
It can be expressed as.
When the gain crossover frequency f _t is obtained from this equation,
f _t = f _PWM / π
become.
Since this gain crossover frequency f _t is somewhat lower than 1/2 of f _PWM , the response of the feedback path can be approximated as a first-order lag system and is stable.

If the amplitude of the triangular wave is larger than the above (the triangular wave amplitude _pp minimum value), the path gain is lowered and stable PWM modulation is possible, but the follow-up to input changes is degraded.

  Since the triangular wave used in FIG. 5 is obtained by integrating the rectangular wave, if there is no circuit error, the triangular wave generator 4 shown in FIG. 6 (A) is replaced with the rectangular wave generator 6 as shown in FIG. 6 (B). And an integrator 7.

Here, in order to simplify the explanation, the characteristics of the two integrators 2 and 7 are the same, and the condition of stable operation is that (slope of triangular wave) is larger than (slope of integrator output) as in FIG. Then, (the minimum amplitude of the square wave) is
(Minimum amplitude of rectangular wave) = ± (input span)
It becomes.

  FIG. 7 is a block diagram showing another example of a conventional feedback type pulse width modulator, and the same reference numerals are given to portions common to FIGS. In the configuration of FIG. 7, the rectangular wave output of the rectangular wave generator 6 is input to the adder 1, added to the input signal and supplied to the integrator 2, so that two integrators required in FIG. 6B are required. Are combined into one. The phase of the triangular wave is reversed, but the response characteristics are not affected.

  As described above, if the amplitude of the rectangular wave is larger than ± (input span), the operation is stable, but if the amplitude is large, the path gain is lowered and the response is deteriorated.

The condition corresponding to the case of (amplitude _pp minimum value of triangular wave) in the configuration of FIG. 4, that is, the condition that operates stably over the entire range of the input signal and has good responsiveness,
(Minimum amplitude of rectangular wave) = ± (input span)
This is the case.
The gain crossover frequency f _{t at} that time is the same as in FIG.
f _t = f _PWM / π
It is.

As shown in FIG. 7, combining the two integrators into one provides the following advantages.
1) The number of parts can be reduced.
2) As shown in FIG. 6 (B), when a triangular wave is generated by using two integrators 2 and 7 to integrate a square wave, integration occurs if there is a DC component (error) at the input of the integrator. Although the value increases (diverges) with time and deviates from the operating range of the comparator 3, this DC error is also fed back together with the signal by integrating the integrators into one. No DC voltage is applied.

  FIG. 8 is another example of the configuration of the conventional feedback type pulse width modulator. FIG. 8A is a circuit diagram, and FIG. 8B is a block diagram thereof. ing. In FIG. 8A, the input voltage Ex is converted into a current Ex / Rx by a resistor Rx. This current is input to and integrated with an addition integrator formed by an operational amplifier OP1 and a capacitor C1.

  Since the potential of the node connected to the inverting input terminal of the operational amplifier OP1 is almost 0 V, and the total current flowing into this node is 0, the charging voltage of the capacitor C1 is the current flowing from a path other than the capacitor C1. The sum of is integrated. Although the output voltage of the operational amplifier OP1 has an inverted polarity, the essence of the operation is not affected if it is inverted again in any block in the path so that the feedback path becomes a negative feedback in one cycle.

  The output of the integrator 2 is compared with 0V by the comparator 3 and becomes a binary PWM signal. However, the polarity is reversed.

  The PWM signal is input to the flip-flop FF and outputs a PWM signal having a pulse width that is an integral multiple of the clock pulse generated by the clock generator 8 and functions as a PWM modulator.

  Although the gate circuit AG obtains the logical product of the PWM signal and the clock pulse and converts it into a burst signal, the gate circuit AG does not affect the operation of the PWM modulator.

  The level converter 5 is configured as a current output type by switches SW1, SW2, resistors R1, R2 and voltage sources + Es, -Es. When the Q output of the flip-flop FF is logic 1, the switch SW1 is turned on. When the logic is 0, the switch SW2 is driven to be turned on.

The output current of the level converter 5 is as follows.
When Q output of flip-flop FF is logic 0: -Es / R1
When Q output of flip-flop FF is logic 1: + Es / R2

  The output of the level converter 5 is fed back to the node to which the inverting input terminal of the operational amplifier OP1 is connected, and a negative feedback path is configured.

  A rectangular wave with a voltage level of ± Ec generated by dividing the clock pulse is converted into a current of ± Ec / Rc via resistor Rc and injected into the node connected to the inverting input terminal of operational amplifier OP1 By doing so, the frequency of the PWM signal is synchronized with the frequency of the rectangular wave.

  The amplitude of this rectangular wave current needs to be larger than ± (input current span), that is, ± (Es / R1 + Es / R2), as in FIG. Here, the capacitor C2 connected in series with the resistor Rc is an element for removing a DC component, and does not affect the essence of the operation.

  When the current is input, the upper limit of the input range is + Es / R1, and the lower limit is -Es / R2, so the input current span is Es / R1 + Es / R2.

The current output amplitude of the rectangular wave generator 6 is as follows.
(Current output amplitude of rectangular wave generator) = ± (Input current span)
= ± (Es / R1 + Es / R2)

FIG. 8B is configured in substantially the same manner as FIG. 7 and operates in substantially the same manner as FIG. 7, but differs in the following points.
a) A clock generator 8 is added.
b) A frequency divider 9 that divides the clock pulse of the clock generator 8 is used as a rectangular wave generator.
c) A flip-flop FF is inserted between the comparator 3 and the level converter 5, and the transition timing of the PWM pulse is quantized (discretized) by the clock pulse of the clock generator 8.

  By applying such a configuration to the A / D converter and quantizing the PWM pulse transition timing with the counter clock of the subsequent stage, the feedback amount is quantized and matches the count value. The quantization error generated in one cycle remains accumulated in the integrator and is carried over to the next PWM cycle.

  When the accumulated quantization error becomes an amount corresponding to one count, the pulse width is increased by one clock, and the corresponding amount is removed from the accumulated quantization error.

  In general, the feedback PWM modulator has a delay of about 5 to 10 cycles until the output is settled with respect to a change in input. Therefore, it is necessary to increase the carrier frequency in order to improve the response.

  On the other hand, by accumulating the pulse width of the PWM signal whose pulse width is quantized over a plurality of periods, both high resolution and improved responsiveness can be achieved.

  The quantization noise is low at 6 dB / oct because the quantization is performed after the integrator as in the case of the first-order Δ-Σ modulator in which the comparison operation and the D / A block are multi-valued. It has the characteristic of first-order noise shaping that attenuates the band.

  FIG. 9 is a block diagram showing an example of the Δ-Σ modulation circuit, and the same reference numerals are given to the portions common to FIG. In FIG. 9, a pulse obtained by binarizing the value of the integrator 2 is output from the comparator 3, and the output signal of the comparator 3 is sent as a feedback signal to the adder 1 via the delay circuit 10 and the D / A converter 11. Entered. Note that the comparator 3 is set such that the output pulse is set to 1 and 0 so that the integral value does not diverge, and the output average value of the D / A converter 11 cancels the input signal.

  Thus, the circuit of FIG. 9 operates as a pulse density (frequency) modulator because the density of output pulses (ratio of 1 pulse) changes according to the input signal.

  Here, the spectrum of the quantization noise included in the pulse train of the output of the Δ-Σ modulator will be considered. A block that generates quantization noise is considered a comparison block that is binarized.

  If this quantization noise is considered as white noise and converted to the input level, it will be divided by the gain of the integrator in the previous stage of the comparison block due to the nature of the negative feedback system, so the spectrum will attenuate at about 6 dB / oct. . This is a characteristic of primary noise shaping.

  When an A / D converter is configured using this Δ-Σ modulator, the quantization noise biased to the high frequency region is removed by a digital filter provided in the subsequent stage, so that the resolution corresponding to the bandwidth of the filter can be obtained. Can be obtained.

  FIG. 10 is a block diagram showing an example of a second-order Δ-Σ modulation circuit, in which an adder 12 and an integrator 13 are further connected in cascade before the Δ-Σ modulation circuit shown in FIG. When the integrators are simply cascaded in two stages, the phase is delayed by 180 ° and the system becomes unstable. In FIG. 10, the path is obtained by adding the output of the D / A converter 11 to the integrator 2 in the subsequent stage. A zero point is inserted into the transfer function of one round, and the system is stabilized by returning the phase in the high frequency range.

  Since the quantization noise spectrum in the configuration of FIG. 10 is two-stage integrated at the front stage of the comparator 3, focusing on the quantization noise, the characteristic of secondary noise shaping that attenuates at 12 db / oct in the low frequency range Become.

  As a result, when the passband widths of the A / D converters are the same, the two-stage integration configuration can have higher resolution than the case of one integrator. In the case of the same resolution, this two-stage integration configuration can broaden the bandwidth and can respond to input changes at high speed.

JP-A-57-49866

  Patent Document 1 discloses an invention relating to a feedback type pulse width modulator and a digital voltmeter using the same.

  However, according to the circuit configuration of FIG. 8, the quantization noise of the modulator has a primary noise shaping characteristic. However, when the input is a direct current, a long-period and highly periodic noise is generated. . For example, when the quantization error carried over in one PWM cycle is 1/100 of the clock pulse, the output pulse width is increased by the width of the clock pulse once in 100 cycles.

This digital voltmeter A / D converter using a PWM modulator integrates the pulse width over a plurality of periods using a counter provided in the latter stage, but (measurement time), (clock period), and span (Resolution) relationship normalized by
(Resolution) = (Clock period) / (Measurement time)
become.

  For example, in order to obtain a resolution of 0.1 ppm with a measurement time of 10 ms, it is necessary to use a clock with a period of 1 ns, but this requires a faster clock than the higher-order Δ-Σ method, It is disadvantageous in cost.

  In addition, when a capacitor is used for the integrator, the DC voltage component of the capacitor changes according to the input, so that the response characteristic deteriorates due to the influence of the dielectric absorption characteristic of the capacitor, causing an error.

  According to the circuit configuration of FIG. 9, since the quantization noise of the modulator is a primary noise shaping characteristic like the PWM of FIG. 8, it is difficult to achieve high performance.

  Further, since the output pulse of 1, 0 is determined every clock cycle, the frequency of the feedback signal changes more frequently than PWM, and the error tends to increase.

  According to the circuit configuration of FIG. 10, since the characteristics of the secondary noise shaping are obtained, the clock frequency can be lowered as compared with the primary ΔΣ system, but the feedback signal changes more frequently than the PWM, and the error Tends to grow.

  If the number of integration stages is increased and the higher-order Δ-Σ method is used, a sufficient S / N ratio (resolution) can be obtained at a low clock frequency, but not only the circuit scale increases but also the input signal changes suddenly. Sometimes the integrator is saturated and the stability of the feedback path is easily lost.

  The present invention solves these problems, and an object of the present invention is to provide a feedback type pulse width modulator that can shorten the conversion time while maintaining a predetermined resolution and can improve the resolution if the conversion time is the same. Is to provide.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
An amplifier that is cascade-connected to the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path ,
The amplifier is arranged in front of the integrator, and a rectangular wave signal system for adding a rectangular wave signal to the input signal of the integrator is provided, and a pulse width signal is compared with the output signal of the integrator with a predetermined value. It is characterized by converting into.

The invention according to claim 2
In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
An amplifier that is cascade-connected to the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path,
The output signal of the integrator is compared with a triangular wave signal and converted into a pulse width signal.

The invention described in claim 3
In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
An amplifier is provided in front of the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path.

  According to the present invention, it is possible to provide a feedback type pulse width modulator in which low frequency components of quantization noise are reduced.

It is a block diagram which shows one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram which shows an example of the conventional feedback type pulse width modulator. 5 is a timing chart for explaining the operation of FIG. 4. It is a block diagram of the principal part of the conventional feedback type pulse width modulator. It is a block diagram which shows the other example of the conventional feedback type pulse width modulator. It is a block diagram which shows the other example of the conventional feedback type pulse width modulator. It is a block diagram which shows an example of a delta-sigma modulation circuit. It is a block diagram which shows an example of a secondary Δ-Σ modulation circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which parts common to FIG. 7 are given the same reference numerals, (A) is a circuit diagram, and (B) is a block diagram thereof. is there.

  The configuration of FIG. 1 is similar to the secondary Δ-Σ modulation circuit shown in FIG. In particular, the Δ-Σ modulator has the same configuration as the case where a small-amplitude AC signal called a “dither signal” is added to the signal in order to disperse the spectrum of quantization noise. Is a large amplitude that determines the frequency of the output signal and is not a “dither signal”.

  Since the modulator according to the present invention obtains a PWM signal having a rectangular wave frequency by injecting a rectangular wave having a large amplitude, it is different from a Δ-Σ modulator that outputs a pulse density of a binary pulse. is there.

  When the modulator according to the present invention is interpreted as a ΔΣ modulator using a multilevel quantizer, the basic period of operation is the period of the injected rectangular wave (carrier wave). The modulator does not perform sampling at that period, and is different from the operation of a conventional Δ-Σ modulator that assumes sampling at every basic period.

  The input voltage Ei is input to the inverting input terminal of the operational amplifier OP1 via the resistor Ri, and the reference voltage ± Vref is also input to the inverting input terminal SW via the changeover switch SW3 that is switched by the resistor Rfb and the Q output of the flip-flop FF. ing. A capacitor C1 is connected between the inverting input terminal and the output terminal of the operational amplifier OP1, and the non-inverting input terminal is connected to a common potential point.

  The inverting input terminal of the operational amplifier OP3 is connected to the output terminal of the operational amplifier OP1 through a parallel circuit of a series circuit of a capacitor C3 and a resistor R3 and a resistor R4, and is switched by the output of the resistor R5 and the frequency divider 9 A reference voltage ± Vref is also input via the driven changeover switch SW4. A capacitor C4 is connected between the inverting input terminal and the output terminal of the operational amplifier OP3, and the non-inverting input terminal is connected to a common potential point.

  The output terminal of the operational amplifier OP3 is connected to the inverting input terminal of the comparator 3, the non-inverting input terminal is connected to the common potential point, and the output terminal is connected to the D terminal of the flip-flop FF.

  The clock signal generated by the clock generator 8 is input to the clock terminal CK of the flip-flop FF and also input to the frequency divider 9.

The modulator configured as shown in FIG. 1 operates as follows.
1) Subtract the feedback signal from the input signal Ei,
2) Amplify it with an amplifier 15 comprising an operational amplifier OP1,
3) Add the square wave generated by the square wave generator to the amplified signal,
4) Integrate the signal with the added square wave by integrator 2 consisting of operational amplifier OP3,

5) Compare the output of integrator 2 with a constant voltage (for example, 0V) and convert it into an asynchronous PWM signal of binary logic level,
6) The asynchronous PWM signal is synchronized with the clock by the flip-flop FF to obtain a PWM output signal.
7) The PWM output signal is further converted into a binary feedback signal of the same type (for example, current) as the input by the level conversion block.
8) As described in 1), the feedback signal and the input signal are subtracted from the input signal and input to the amplifier 15 at the next stage, so that a negative feedback path is configured.

  Here, if the gain of the amplifier 15 composed of the operational amplifier OP1 is 1, the operation is exactly the same as in FIG. When the gain of the amplifier 15 is increased k times (1 <k) regardless of the frequency, the operation becomes unstable because it is equivalent to the case where the amplitude of the feedback signal is increased k times.

  At this time, if the amplitude of the rectangular wave is increased by k times, the same characteristics as in the conventional example are obtained and the operation is stabilized, but there is no effect of reducing quantization noise.

The gain of the amplifier 15 for performing the stable pulse width modulation operation by reducing the quantization noise not only has a large value in the pass band of a PWM demodulator (not shown) provided in the subsequent stage, but also has a gain of 1 at the carrier frequency f _PWM . The gain of one round of the path must be 1 or less at / π.

  For this reason, the gain of the amplifier 15 must have a characteristic that decreases in a high frequency range, that is, an integral or a low-pass characteristic.

  Also, sufficient phase margin is required to stabilize the negative feedback, so at least the feedback signal has a zero point at the gain crossover frequency or lower frequency, and is generally proportional to the gain crossover frequency. It is necessary to become.

  The amplifier 15 shown in FIG. 1 has a main port for inputting the difference between the input signal and the feedback signal and a sub port for directly inputting the feedback signal. The sub port is used when a zero point is inserted only on the feedback side. use.

  Note that the zero point is a complex frequency that makes the value of the transfer function zero, and if the zero point is a negative real number, the value of the transfer function on the frequency axis (imaginary axis) will not be zero, And has the effect of giving a differential characteristic at a frequency higher than the frequency corresponding to the distance of the zero point.

  Here, in order to simplify the description, Ri = Rfb = R4 = R and the gain of the amplifier 15 is modified to be -1. That is, a resistor R is added in parallel with the capacitor C1, the capacitor C3 is matched with the capacitor C1, and the resistor R3 is set to 0Ω. This resistor R3 is a small resistor that is inserted in order to stabilize the load impedance of the operational amplifier in the high frequency range and is not necessary in principle.

  With this modification, the configuration is the same as that of the conventional PWM modulator shown in FIG. 7 except for the polarity inversion of the signal due to the insertion of the inverting amplifier.

  In the embodiment shown in FIG. 1, the rectangular wave generator 6 includes a frequency divider 9, a reference voltage ± Vref, switches SW3 and SW4 for controlling the reference voltage ± Vref, and a resistor R5, and a current output of ± Vref / R5. It is said.

  It is known that if the amplitude of the rectangular wave injected into the integrator 2 is double that of the feedback signal, a stable PWM modulation operation and good responsiveness can be obtained. Therefore, in this embodiment, the resistance value of the resistor R5 is set to ½ of the resistor Rfb, thereby making the rectangular wave current twice the feedback signal current.

When the gain crossover frequency f _t when the gain of the amplifier 15 is 1 and the amplitude of the rectangular wave is twice that of the feedback signal is _expressed by the carrier frequency f _PWM (frequency of the rectangular wave), f _t = f as in the conventional example. _PWM / π.

  By removing the resistor added in parallel to the capacitor C1 in order to obtain the original gain of the amplifier 15, if the frequency is higher than the zero point 1 / (2πC3R), it can be approximated to the proportional characteristic of the capacitance ratio C3 / C1. It is possible to approximate integral characteristics at lower frequencies. In the embodiment shown in FIG. 1, since C1 = C3 is particularly set for simplicity, the absolute value of the gain is 1 at a high frequency.

The zero point frequency is set in the vicinity of the gain crossover frequency f _t or lower. Here, C3 and C1 when the frequency of the zero point is matched with f _t are
1 / (2πC3R) ＝ f _PWM / π
Than,
C1 = C3 = 1 / (2Rf _PWM )
become.

  The value of the feedback capacitor C4 of the operational amplifier OP3 constituting the integrator 2 does not directly affect the characteristics of the PWM modulator, but normal operation of the integrator 2 and the comparator 3 in order to improve noise resistance. Set to increase the output within the range not exceeding the range.

  By determining the constants as described above, it is possible to obtain a PWM modulator that operates stably in most of the input range. Strictly speaking, the gain of the amplifier 15 at the zero point is +3 dB, and the phase is 45. Since it is delayed, it behaves somewhat like a vibration.

  In order to improve the stability, for example, the capacitance of the capacitors C1 and C3 may be increased to move the zero point to the low frequency side. This increases the phase margin.

  In addition, when the output signal repeats inversion without synchronizing with the carrier wave when a signal close to the upper limit or lower limit of the input range is input, the amplitude of the rectangular wave is increased or the capacitance ratio C3 / C1 is By making it smaller than 1, the operating range can be expanded.

  In this way, in the feedback type PWM modulator for quantizing the pulse width, the amplifier 15 and the integrator 2 are connected in cascade, so that the quantization noise becomes the spectrum similar to that of the secondary Δ-Σ modulator and the low frequency region. S / N ratio can be improved.

  Since the output of the amplifier 15 at the front stage has a DC component of 0 V, the amplifier 15 is hardly affected by the dielectric absorption characteristics of the capacitor, and the integrator 2 at the rear stage is affected by the dielectric absorption characteristics of the capacitor. Since the input conversion error becomes 1 / gain of the amplifier 15, it becomes a small value.

  For the same reason, the offset error of the integrator 2 in the subsequent stage and the error due to the DC component of the injected rectangular wave can be ignored.

The transfer function of the amplifier 15 used in FIG. 1 preferably has the following characteristics.
a) having at least one zero point at a frequency of about 1 / π of a rectangular wave or lower,
b) It has at least one pole at a frequency (or 0 Hz) lower than the zero point.
c) The gain from the feedback signal side at 1 / π of the frequency of the rectangular wave is approximately proportional.

  The amplitude of the rectangular wave is preferably approximately the magnitude obtained by multiplying (amplitude of the feedback signal) by (twice the magnification of the amplifier 15 at 1 / π of the rectangular wave frequency).

  FIG. 2 is a block diagram showing another embodiment of the present invention, which is applied to a discrete-time system, and the same reference numerals are given to parts common to FIG. In FIG. 2, a ± full scale input signal is input to one input terminal of the adder 16, and a ± full scale PWM output signal is connected to one input terminal via the level converter 5 at the other input terminal. Is input in reverse polarity.

The output signal of the adder 16 is input to one input terminal of the adder 17, and the output signal of the register function element 18 that stores the value of one calculation cycle before is input to the other input terminal with the same polarity as that of the one input terminal. Is fed back to form an integrator. The symbol z ⁻¹ of the register functional element 18 is obtained by z-converting the delay (T seconds) of the calculation cycle, and has a relationship of z ⁻¹ = e ^−sT with the Laplace transform. The output signal of the register function element 18 is input to the coefficient calculator 19.

The coefficient calculator 19 is
Coefficient value = (rectangular wave frequency) / (clock frequency)
Perform the operation. The clock frequency is the reciprocal of the calculation cycle. This coefficient value determines the zero point frequency together with the signal bypassing the integration. In this embodiment, the frequency of the zero point is approximately (rectangular wave frequency) / (2π), and there is a sufficient phase margin. The output signal of the coefficient calculator 19 is input to one input terminal of the adder 20.

  The output signal of the adder 16 is input to the other input terminal of the adder 20 with the same polarity as that of the one input terminal.

  The adder 21 has three input terminals. The output signal of the adder 20 is input to the first input terminal, and the output signal of the rectangular wave generator 6 is the first input terminal to the first input terminal. The input signal is input with the same polarity as the input terminal, and the output signal of the register functional element 22 is fed back to the third input terminal with the same polarity as the other input terminals.

  The output signal of the register function element 22 is input to the comparator 3.

  The comparator 3 compares the input with an arbitrary constant (for example, 0) and outputs a binarized PWM signal.

  In the circuit configuration of FIG. 2, if a numerical calculation is performed with the input as a digital value, a PWM signal corresponding to the input can be obtained using the digital circuit.

  After converting the level of this PWM signal, it is possible to use it as a D / A converter by removing the AC component using a low-pass filter.

  FIG. 3 is a block diagram showing another embodiment of the present invention, and the same reference numerals are given to the parts common to FIG. 3 differs from FIG. 1 in that a triangular wave generator 4 similar to FIG. 4 is provided instead of the rectangular wave injection of FIG.

  In FIG. 3, the output signal of the integrator 2 is input to one input terminal of the comparator 3, and the output signal of the triangular wave generator 4 is input to the other input terminal.

  As a result, the comparator 3 compares the input signal with the triangular wave output signal of the triangular wave generator 4 and can obtain a PWM signal from the flip-flop FF.

  Note that the order of the amplifier 15 and the integrator 2 shown in FIG. 3 may be interchanged.

The transfer function of the amplifier 15 used in FIG. 3 preferably has the following characteristics.
a) having at least one zero point at a frequency of about 1 / π of the three-dimensional wave or lower,
b) It has at least one pole at a frequency (or 0 Hz) lower than the zero point.
c) The gain from the feedback signal side at 1 / π of the frequency of the triangular wave is approximately proportional.

It is desirable that the amplitude of the triangular wave is approximately expressed by the following equation.
(Amplitude of triangle wave) = (Amplitude of feedback signal) x 0.5 x (T _PWM / T _i ) x A
T _i : 1 / (integral gain)
T _PWM : Triangular wave period
A: magnification of the amplifier 15 at 1 / π of the triangular wave frequency

  As described above, according to the present invention, a pulse width modulator in which quantization noise is reduced in a low frequency range can be realized. When applied to an A / D converter, high accuracy and high resolution can be achieved with a relatively short conversion time. A conversion output is obtained, which is suitable for a DC measuring instrument, a DC signal generator, and the like.

DESCRIPTION OF SYMBOLS 1, 14 Adder 2 Integrator 3 Comparator 4 Triangular wave generator 5 Level converter 6 Rectangular wave generator 8 Clock generator 15 Amplifier FF Flip-flop

Claims (3)

In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
An amplifier that is cascade-connected to the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path ,
The amplifier is arranged in front of the integrator, and a rectangular wave signal system for adding a rectangular wave signal to the input signal of the integrator is provided, and a pulse width signal is compared with the output signal of the integrator with a predetermined value. A feedback type pulse width modulator characterized by converting into a pulse width modulator. In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
An amplifier that is cascade-connected to the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path,
A feedback type pulse width modulator characterized in that an output signal of the integrator is compared with a triangular wave signal and converted into a pulse width signal. In a feedback type pulse width modulator comprising an integrator and a negative feedback path of an output signal, and configured to change the pulse width of a pulse signal having a predetermined period according to the magnitude of an analog input signal,
A feedback type pulse width modulation characterized in that an amplifier is provided in front of the integrator and amplifies a low frequency component of a difference between the analog input signal and an output signal fed back through the negative feedback path. vessel.

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