JPH07120950B2 - DA converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a DA converter using an oversampling technique and a noise shaping (delta sigma modulation) technique, and particularly to a technique for preventing a limit cycle in a noise shaper. It is a thing.

SUMMARY OF THE INVENTION The present invention is a circuit for adding a digital AC waveform signal to a digital signal as an input of a noise shaper to prevent a limit cycle in the noise shaper. The presence or absence of the signal is detected, and when there is no signal, the data in the noise shaper is cleared, and the amplitude value of the AC waveform signal is controlled to be gradually reduced to zero to reduce noise when there is no signal.

[Prior Art] Conventionally, as a DA converter using the oversampling technology and the noise shaping technology, the one illustrated in FIG. 5 has been proposed.

In FIG. 5, 10 is a multi-bit digital input DI
Is a digital filter for oversampling, 12 is an adder which receives the multi-bit digital signal A from the filter 10 as one input, and 14 is a dither which supplies the AC waveform signal D in digital form to the adder 12 as the other input, Reference numeral 16 is a noise shaper (delta sigma modulator) for transmitting a digital signal B having a reduced number of bits by performing delta sigma modulation (calculation processing) on the multi-bit digital signal A ₁ as the addition output of the adder 12, and 18 is A waveform shaping circuit for shaping the pulses forming the digital signal B from the noise shaper 16 according to the shaping clock signal, 20 is a clock generator for generating the system clock signal φ _S having the frequency f _S , and 22 is a circuit 18 With a low pass filter (LPF) that filters the pulse output C from the and converts it into an analog output AO corresponding to the input DI That.

The circuit part taken in by the one-dot chain line IC is configured as a monolithic or hybrid type integrated circuit and arranged in one package, and 20A is a crystal oscillator externally attached to the clock generator 20. . In some cases, the digital circuit 10 and its related portion (the portion surrounded by the broken line) are integrated into a circuit.

Digital input DI is a waveform data including data of 16 bits for each sample as an example (one word), the data sending frequency is 44.1KH _Z. The frequency of the system clock signal phi _S is 16.9MH _Z, data sending frequency from the digital filter 10 to the noise shaper 16 is generally f _S / 2 (e.g. 8.45MH _Z).

The noise shaper 16 is provided to reduce the oversampling frequency in the oversampling DA conversion. When a primary or secondary noise shaper is used as the noise shaper 16, a pulse density modulation (bit stream) output is obtained as the noise shaper output B, and as a noise B shaper output as the output B when a tertiary or higher-order noise shaper is used. A pulse width modulated output is obtained.

In the noise shaper 16, the digital signal is converted into a representation with a reduced number of bits. The error caused by such conversion becomes noise, which becomes larger in the higher frequency region, while the noise in the audible frequency band of interest is satisfactory. It will be low. That is, FIG. 6 shows the power spectrum of the ideal output of the noise shaper 16, and the noise power due to noise shaping is maximum in the high frequency region near f _S / 2. Further, the monochromatic sharp power component P _a in the low frequency region is obtained when the input digital signal component is given as a sine wave, and the power component P _b
Is due to the system clock signal φ _S.

Since various noises are added to the ideal state of the noise shaper output B due to fluctuations when it is subjected to digital processing, if the output B is directly converted into an analog output by the LPF 22, an error occurs due to the noise component. Therefore, the noise shaper output B is supplied to the system clock signal φ _S by the waveform shaping circuit 18.
By shaping the waveform based on the above, and then supplying it to the LPF22, the error due to the noise component is reduced.

The adder 12 and the dither 14 are provided to prevent a limit cycle from occurring in the noise shaper 16. The noise shaper 16 is composed of, for example, a first-order delta-sigma modulator as shown in FIG. 2, but the output data becomes negative on the input side as the system clock signal φ _S repeats “1” and “0”. It is fed back, and the contents of the register in the integrator are changed accordingly. When a digital signal corresponding to the DC level is input as the noise shaper input, the contents of the register change at the repetition frequency according to the DC level and AC appears at the output. This AC is called the limit cycle or idling pattern. is there. The frequency of the limit cycle is lower as the DC level is smaller, and may enter the audible frequency band at a minute DC level. Limit cycles are detrimental to DA conversions because they add unwanted oscillations to the output.

In the circuit of FIG. 5, in order to prevent the limit cycle,
The dither 14 is applied to the digital signal A in the adder 12.
The AC waveform signal D from is added to disturb the DC component,
This prevents the energy of the limit cycle from being concentrated in one frequency. The AC waveform signal D, to use a level square wave signal of -12 to-20 dB level at a frequency of 200～600KH _Z position is common.

[Problems to be Solved by the Invention] According to the above-described conventional limit cycle prevention technique, the AC waveform signal D is applied to the adder 12 even when the input signal is no signal.
And the signal D is supplied to the noise shaper 16 as the addition output A ₁ . Therefore, the noise shaper 16
The noise of the output of the is increased, and the S / N ratio when there is no signal is 120
It was difficult to get more than dB.

An object of the present invention is to reduce noise when there is no signal in the above-described oversampling DA converter.

[Means for Solving the Problems] A DA converter according to the present invention includes: (a) a noise shaper for transmitting a digital signal having a reduced number of bits by delta-sigma modulating an oversampled multi-bit digital input. (B) signal generating means for generating a digital AC waveform signal for preventing the limit cycle of the noise shaper, and (c) adding means for adding the AC waveform signal from the signal generating means to the digital input. (D) detection means for detecting the presence or absence of the digital input, and (e) in response to the detection output of the detection means indicating no input, clearing the data in the noise shaper and the AC waveform. After starting the decrease of the amplitude value of the signal, the amplitude value is gradually decreased to zero to maintain the state of zero amplitude value. Control means for starting the increase of the amplitude value of the AC waveform signal in response to the detection output of the detection means indicating that there is an input, and for gradually increasing the amplitude value to a predetermined value; and (f) the noise. Conversion means for converting a digital signal from the shaper into an analog output corresponding to the digital input.

[Operation] According to the configuration of the present invention, when there is no digital input, the control means clears the data in the noise shaper based on the detection output from the detection means and gradually reduces the amplitude value of the AC waveform signal to zero. Control to decrease. Therefore, even if the feedback operation is performed in the noise shaper, the register contents are always in the zero state, and the noise becomes extremely small.

After that, when the digital input is enabled, the control means gradually increases the amplitude value of the AC waveform signal to a predetermined value according to the detection output from the detection means. Therefore, no limit cycle occurs even if a digital input corresponding to the DC level is input.

Further, in the present invention, the amplitude value is gradually decreased when the amplitude value of the AC waveform signal is set to zero, and the amplitude value is gradually increased when the amplitude value of the AC waveform signal is set to the predetermined value. As compared with the case where the dither operation is simply turned on / off, the noise accompanying the operation change can be reduced, and the noise can be further reduced.

[Embodiment] FIG. 1 shows a limit cycle prevention circuit for explaining an embodiment of the present invention. The same parts as those in FIG. 5 are designated by the same reference numerals and detailed description thereof will be omitted. .

The circuit of FIG. 1 is characterized in that a signalless detection circuit 30 having the output A of the digital filter 10 as an input is provided, a control switch 32 is provided in the path of the AC waveform signal D, and the detection output from the detection circuit 30 is provided. The control switch 32 and the noise shaper 16 are controlled according to NS.

When the detection circuit 30 detects the absence of a digital signal based on the output A of the filter 10, the detection output NS becomes "1", the control switch 32 is off-controlled and the data in the noise shaper 16 is cleared accordingly. It

The noise shaper 16 is composed of, for example, a first-order delta-sigma modulator as shown in FIG. In FIG. 2, 16A is an adder having the output of the adder 12 as one input, 1
6B is an integrator whose input is the output of the adder 16A, and 16C is an integrator.
The quantizer that determines whether the output of 16B is positive or negative and performs 1-bit quantization, 16D delays the output of the quantizer 16C (noise shaper output) by one sampling time, and then the adder 16
A delay element that feeds A as the other input. Here, the adder 16A and the integrator 16B each include a register having a predetermined number of bits, and the delay element 16D is configured by a D flip-flop or the like having a data holding function.
Therefore, in order to clear the data in the noise shaper 16, the register of the adder 16A depending on the detection output NS = "1",
The register of the integrator 16B, the D flip-flop of the delay element 16D, etc. may be cleared.

When the control switch 32 is turned off, the addition of the AC waveform signal D is stopped in the adder 12, so the output A _{1 of the} adder 12
(That is, the noise shaper input) has no signal.
At this time, all the data in the noise shaper 16 is cleared as described above. Therefore, even if the noise shaper 16 performs the feedback operation, only the zero information is returned, and the register contents always keep the same zero state. That is, the noise shaper 16 is in a state equivalent to the inside not operating,
Since the noise included in the output is extremely small, the S /
The N ratio is the best.

When the detection circuit 30 detects the presence of a digital signal based on the output A of the filter 10, the detection output NS becomes "0", the control switch 32 is ON-controlled accordingly, and the noise shaper 16 can operate normally. As a result, the AC waveform signal D from the dither 14 is mixed with the digital signal as the noise shaper input by the adder 12, so that the noise shaper 16 has a limit cycle even if a digital signal corresponding to the DC level arrives. Does not occur.

In the circuit of FIG. 1, instead of providing the control switch 32, the operation of the dither 14 may be controlled to be turned off or on in accordance with the detection output NS “1” or “0”, respectively.

FIG. 3 shows a limit cycle prevention circuit according to an embodiment of the present invention. This circuit is different from that of FIG. 1 in that it has a dither 14A whose output gradually falls and gradually rises. Other points are the same as those in FIG. 1.

Based on the output A of the filter 10, the detection circuit 30 detects, for example, the fourth
When the absence of a digital signal is detected at the timing of t _{1 in} the figure, the detection output NS becomes “1”, and in response to this, the counting control circuit 40 gives the down / up counter 42 a down counting command. Therefore, the counter 42 has the first pulse generator 44.
The down counting of the pulse CP from is started from the timing of t ₁ . The counter 42 is, for example, a 6-bit whose most significant bit is a sign bit (+ = "0"), and the count value changes from "011111" to "000000" as shown in FIG. . It should be noted that all the data in the noise shaper 16 is cleared in accordance with the detection output NS = "1", as in the case described with reference to FIGS. 1 and 2.

When the count value of the counter 42 reaches the minimum value "000000" at the timing of t ₂ in FIG. 4, for example, the count control circuit 40 detects this and gives a count stop command to the counter 42. Therefore, the counter 42 stops in the state where the count value is zero.

By the way, while the counter 42 is counting down, the count output CN
T is supplied to the sign inversion circuit 50 or the OR circuit 52 via the control switch 46. Here, the control switch 46 switches to the contact a or b according to "1" or "0" of the dither pulse DP generated from the second pulse generator 48 at a cycle corresponding to the dither frequency. Then, the count output CNT is supplied as it is to the OR circuit 50 through the contact a and the sign output of the count output CNT (“100000” to “111111”) is supplied to the OR circuit 52 through the contact b and the sign inversion circuit 50. It is supposed to do. Therefore, as the output of the OR circuit 52, as shown in the section from t ₁ to t _{2 in} FIG. 4, the alternating current is of a digital type in which the value gradually decreases from the positive / negative maximum value ± M toward the minimum value 0. A waveform signal DS is obtained, and this signal DS is supplied to the adder 12. When the amplitude value of the AC waveform signal DS is gradually decreased in this way, noise when the dither function is turned off is reduced as compared with the case where the amplitude value is sharply decreased as shown in FIG.

Based on the output A of the filter 10, the detection circuit 30 detects, for example, the fourth
When the presence of a digital signal is detected at the timing of t _{3 in} the figure, the detection output NS becomes “0”, and in response to this, the counting control circuit 40 gives an up-counting command to the counter 42. Therefore, the counter 42 starts counting up the pulse CP at the timing of t ₃ , and the count value is changed from “000000” to “01111”.
Change toward 1 ”.

When the count value of the counter 42 reaches the maximum value "011111" in the timing of, for example, FIG. 4 of t _4, giving a count stop command to the counter 42 the count control circuit 40 detects this. Therefore, the counter 42 stops at the maximum count value.

While the counter 42 is counting up, the count output
The CNT is switched and supplied by the control switch 46 to the sign inverting circuit 50 or the OR circuit 52 as in the case of down counting, and the output of the sign inverting circuit 50 is also supplied to the OR circuit 52. Therefore,
The output of the OR circuit 52, the AC waveform signal DS in digital form, such as values as shown in the fourth diagram of t ₃ ~t ₄ sections gradually increases toward the positive and negative maximum value ± M 0 The obtained signal DS is supplied to the adder 12. When the amplitude value of the AC waveform signal DS is gradually increased in this manner, noise when the dither function is turned on is reduced as compared with the case where the amplitude value is rapidly increased as shown in FIG.

In FIG. ₄ , the counter 42 is provided before t ₁ or after t _4.
The normal dither function can be obtained by the AC waveform signal DS having a constant amplitude corresponding to the maximum count value of. Further, the interval of t ₂ ~t _3, the level of the signal DS corresponding to the minimum count value of the counter 42 is zero, the dither function is stopped. In addition,
The counter 42 does not necessarily need to detect and stop the minimum value or the maximum value, but sets an appropriate upper limit value or lower limit value corresponding to the desired maximum or minimum amplitude level of the signal DS, and sets the set value. You may make it detect and stop.

In the circuit of FIG. 3, the pulse generators 44 and 48 are
The clock signal φ _S from the clock generator 20 in the figure may be divided to generate a pulse.

As described above, according to the present invention, the presence or absence of the digital signal as the input of the noise shaper is detected, and when there is no signal, the dither function is stopped and the data in the noise shaper is cleared. Therefore, the noise included in the noise shaper output can be significantly reduced when there is no signal, and the S / N ratio when there is no signal can be improved to 120 dB or more.

In addition, the amplitude value of the AC waveform signal for limit cycle prevention is gradually changed and controlled when the dither function is turned on / off, so noise due to on / off can be reduced, and noise can be further reduced. There are also possible effects.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a limit cycle prevention circuit for explaining an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the noise shaper 16, and FIG. FIG. 4 is a circuit diagram showing a limit cycle prevention circuit according to an embodiment, FIG. 4 is a waveform diagram showing changes in the value of the dither output DS, FIG. 5 is a block diagram showing a conventional DA converter, and FIG. It is a graph which shows the power spectrum of shaper output B. 10 ... Digital filter, 12 ... Adder, 14,14A ...
Dither, 16 …… Noise shaper, 18 …… Wave shaping circuit, 20 …… Clock generator, 22 …… Low pass filter,
30 ... No signal detection circuit, 32,46 ... Control switch, 40 ...
… Counting control circuit, 42… Up / down counter, 50…
... Sign inversion circuit.

Front page continuation (72) Inventor Juro Hoshi 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Stock Company (72) Inventor Tatsuya Kishii 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Stock Company (72) Invention Person Kuniaki Morita 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Yamaha Stock Company (56) Reference JP-A-2-25116 (JP, A)

Claims (1)

[Claims] 1. A noise shaper for transmitting a digital signal having a reduced number of bits by delta-sigma modulating an oversampled multi-bit digital input, and (b) preventing a limit cycle in this noise shaper. Signal generating means for generating an AC waveform signal of a digital format for: (c) adding means for adding the AC waveform signal from the signal generating means to the digital input; and (d) detecting the presence or absence of the digital input. (E) in response to the detection output of the detection means indicating no input, after clearing the data in the noise shaper and starting the decrease of the amplitude value of the AC waveform signal, The amplitude value is gradually decreased to zero to maintain the zero amplitude value, and the detection output of the detection means indicates that there is an input. In response, control means for starting the increase of the amplitude value of the AC waveform signal and thereafter gradually increasing the amplitude value to a predetermined value, (f) a digital signal from the noise shaper that corresponds to the digital input A DA converter equipped with a conversion means for converting the output.