CN103873017A - Device and method for improving pulse edge time resolution - Google Patents
Device and method for improving pulse edge time resolution Download PDFInfo
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- CN103873017A CN103873017A CN201210529760.2A CN201210529760A CN103873017A CN 103873017 A CN103873017 A CN 103873017A CN 201210529760 A CN201210529760 A CN 201210529760A CN 103873017 A CN103873017 A CN 103873017A
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Abstract
The invention relates to a device and method for improving a pulse edge time resolution. The device comprises a pulse parameter processing unit used for processing and acquiring the frequency control character, time threshold value, ascent stage amplitude coefficient and decline stage amplitude coefficient and a pulse generation unit. The pulse generation unit includes a pulse period accumulation module used for generating a phase code; a comparison module used for comparing the phase code with the time threshold value to generate a pulse mark; a rising edge multiplication module used for multiplying the phase code by the ascent stage amplitude coefficient; a falling edge subtraction module used for subtracting the phase code from a decline stage time threshold value; a falling edge multiplication module used for multiplying a result output by the falling edge subtraction module by the decline stage amplitude coefficient; and a selection module used for judging a result generated by the rising edge multiplication module, a result generated by a falling edge multiplication module, an amplitude maximum value of a pulse signal or a pulse amplitude minimum value in output within a period of time according to the pulse mark and thereby generating a pulse signal.
Description
Technical field
The present invention relates to pulse technique field, particularly a kind of device and method that improves porch temporal resolution.
Background technology
Pulse signal generator is a kind of signal generator, produces frequency, pulse duration and amplitude and is adjustable pulse signal.Pulse signal generator of a great variety, performance is different, is widely used in the dynamic characteristic test of impulse circuit, digital circuit.
Along with being punched in fast the extensive use of the aspect such as switching characteristic of oscillographic transient response, time domain reflection technology, components and parts along the pulse, people not only pay close attention to the characteristics such as the frequency, amplitude, width of pulse signal, also more and more pay attention to the characteristic of porch time.The porch time comprises rising edge of a pulse time and pulse trailing edge time, rising edge of a pulse timing definition is that pulse amplitude rose to for 90% threshold value duration from 10% threshold value, and the pulse trailing edge time is defined as pulse amplitude and dropped to for 10% threshold value duration from 90% threshold value.
In prior art, the method for control impuls edge time has two kinds, and the first is the wave table mode based on DDS technology (directly frequency synthesis), and the second is to adopt the analogue devices such as electric capacity, diode.
Signal generator a lot of low and middle-ends, based on DDS technology adopts the mode of wave table to generate the random waveform including pulse, its general principle is: processor is stored in the pulse sampling point of one-period in wave memorizer, then from wave memorizer, takes out pulse sampling point output in the mode of hop.
The defect having in this case: on the one hand, porch the limited time, in the storage depth of wave memorizer, is differentiated rate variance.In fact, the storage depth of wave memorizer is 1000 points for example, pulse frequency 10KHz, and the minimum value of porch time, resolution is 0.1uS.So poor resolution obviously cannot be applied to high speed test and measure.Increase the storage depth of wave memorizer, can improve the resolution of porch time, but cost is higher, and effect is limited; On the other hand, in the time that pulse frequency is lower, due to the sampling point of porch part very little, cause pulse signal to have larger dither cycle; Further, if the amendment edge time needs processor regenerate the pulse sampling point of one-period and be written in wave memorizer, this can consume a lot of processor resources, and system response time is long, and prompt sex change is poor.
Along with the development of technology, there is the regulation device of a kind of porch time.Its general principle is to arrange arbitrarily respectively the upper and lower edge time of utilizing capacitor charge and discharge and switch unit to realize paired pulses waveform.When electric capacity charge and discharge, there is following relational expression: CU=∫ Idt, the relational expression between the porch time of deriving and pulse amplitude, charging and discharging currents and the electric capacity being similar to is: T ≈ 2CU/I from this formula.Therefore, the size of change current source and electric capacity is the capable of regulating porch time.
As shown in Figure 1, be the structured flowchart of the porch regulation device of prior art.Impulse waveform input unit 101, for received pulse waveform generate shaping circuit produce soon along pulse waveform signal; Rising edge current source 102, for exporting the charging current of preset value; Trailing edge current source 103, for exporting the discharging current of preset value; Switch unit 104, charges to capacitor charge and discharge unit 105 along pulse waveform signal control rising edge current source 102 soon for basis, or controls trailing edge current source 103 capacitor charge and discharge unit 105 is discharged; Capacitor charge and discharge unit 105, for according to charging current and discharging current adjustment soon along porch time of pulse waveform signal; Waveform output unit 106, for exporting the pulse waveform signal after the porch time is adjusted.
The defect having in this case: in order to regulate and control the upper and lower edge time of high-speed pulse, due to the switch unit 104 by four rf diode composition high speeds, although the speed of rf diode is fast, operating frequency is high, thermal stability is poor.
For any control impuls edge time, Fig. 1 prior art has 2 kinds of methods: (a) capacitor charge and discharge unit 105 adopts multistage capacitance network, for the different edge time, need to switch the electric capacity of different scale values, control comparatively complexity, and can only be used for the extensive control of edge time; (b) way of conventional a kind of output current of revising rising edge current source 102, trailing edge current source 103 is to control the output current of current source by amendment reference voltage, and reference voltage is adjusted by digital to analog converter by controller.Therefore, adopting the regulation device control impuls edge time of Fig. 1 analogue device composition is more complicated, and cost is higher, very flexible.
Summary of the invention
The object of the invention is for the problems referred to above, a kind of device and method that improves porch temporal resolution is provided, can improve the resolution of porch time, reduce the shake of pulse signal.
For achieving the above object, the invention provides a kind of device that improves porch temporal resolution, this device comprises:
Pulse parameter processing unit, processes and obtains frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient for paired pulses parameter;
Pulse generate unit, for the Information generation pulse signal obtaining according to described pulse parameter processing unit.
Optionally, in an embodiment of the present invention, described pulse generate unit comprises pulse period accumulation module, rising edge multiplier module, trailing edge subtraction block, trailing edge multiplier module, comparison module and selection module;
Described pulse period accumulation module, for the clock pulse T in described pulse generate unit
swhen rising edge, accumulate once frequency control word and produce code mutually;
Described comparison module, for comparing to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively by described phase code;
Described rising edge multiplier module, for described phase code and described ascent stage range coefficient are multiplied each other, and transfers to described selection module by result;
Described trailing edge subtraction block, for described decline stage time threshold and described phase code are subtracted each other, and transfers to described trailing edge multiplier module by result;
Described trailing edge multiplier module, for result and the described decline stage range coefficient of the described trailing edge subtraction block output of obtaining are multiplied each other, and transfers to described selection module by result;
Described selection module, judge the result of exporting the generation of rising edge multiplier module in the time period, the result that trailing edge multiplier module produces, amplitude maximum or the pulse amplitude minimum value of pulse signal for the pulse mark producing according to described comparison module, thereby produce pulse signal.
Optionally, in an embodiment of the present invention, described pulse signal comprises ascent stage, high level stage, decline stage and low level stage.
Optionally, in an embodiment of the present invention, described pulse parameter comprises pulse period, rising time, positive pulsewidth time, trailing edge time, negative pulsewidth time; Wherein, the 50% threshold value duration of the amplitude that is pulse signal of described positive pulsewidth time from 50% threshold value of ascent stage to the decline stage; The 50% threshold value duration of the amplitude that the described negative pulsewidth time is pulse signal from 50% threshold value of decline stage to ascent stage.
Optionally, in an embodiment of the present invention, described pulse parameter processing unit comprises FREQUENCY CONTROL word modules, time threshold module and range coefficient module;
Described FREQUENCY CONTROL word modules, for obtaining frequency control word according to the pulse period;
Described time threshold module, for obtaining ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period;
Described range coefficient module, for obtaining ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
Optionally, in an embodiment of the present invention, described FREQUENCY CONTROL word modules obtains frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
Optionally, in an embodiment of the present invention, described time threshold module is obtained ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described time threshold module is obtained high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described time threshold module is obtained decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described range coefficient module is obtained ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
Optionally, in an embodiment of the present invention, described range coefficient module is obtained decline stage range coefficient according to following formula;
A
f＝A/(K
f–K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
Optionally, in an embodiment of the present invention, described ascent stage range coefficient A
rdata bit width be N+M position, wherein, high N position is ascent stage range coefficient A
rinteger part, low M position is ascent stage range coefficient A
rfractional part.
Optionally, in an embodiment of the present invention, described decline stage range coefficient A
fdata bit width be N+M position, wherein, high N position is decline stage range coefficient A
finteger part, low M position is decline stage range coefficient A
ffractional part.
For achieving the above object, the present invention also provides a kind of method that improves porch temporal resolution, and the method comprises:
Paired pulses parameter is processed and is obtained frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient;
According to described frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient production burst signal.
Optionally, in an embodiment of the present invention, the described step according to described frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient production burst signal comprises:
At clock pulse T
swhen rising edge, accumulate once frequency control word and produce code mutually;
Described phase code is compared to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively;
Described phase code and described ascent stage range coefficient are multiplied each other and obtain the pulse envelope of ascent stage;
Described decline stage time threshold and described phase code are subtracted each other;
Difference between decline stage time threshold and described phase code and described decline stage range coefficient are multiplied each other and obtain the pulse envelope of decline stage;
The amplitude maximum or the pulse amplitude minimum value that judge the pulse envelope of exporting ascent stage in the time period, the pulse envelope of decline stage, pulse signal according to described pulse mark produce pulse signal.
Optionally, in an embodiment of the present invention, described pulse signal comprises ascent stage, high level stage, decline stage and low level stage.
Optionally, in an embodiment of the present invention, described pulse parameter comprises pulse period, rising time, positive pulsewidth time, trailing edge time, negative pulsewidth time; Wherein, the 50% threshold value duration of the amplitude that is pulse signal of described positive pulsewidth time from 50% threshold value of ascent stage to the decline stage; The 50% threshold value duration of the amplitude that the described negative pulsewidth time is pulse signal from 50% threshold value of decline stage to ascent stage.
Optionally, in an embodiment of the present invention, described paired pulses parameter is processed the step of obtaining frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient and is comprised:
Obtain frequency control word according to the pulse period;
Obtain ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period;
Obtain ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
Optionally, in an embodiment of the present invention, the described step of obtaining frequency control word according to the pulse period comprises:
Obtain frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
Optionally, in an embodiment of the present invention, the described step of obtaining ascent stage time threshold according to rising time and pulse period comprises:
Obtain ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, the step that positive pulsewidth time of described basis, trailing edge time, rising time and pulse period are obtained high level phases-time threshold value and decline stage time threshold comprises:
Obtain high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, the step that positive pulsewidth time of described basis, trailing edge time, rising time and pulse period are obtained high level phases-time threshold value and decline stage time threshold comprises:
Obtain decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, the described step of obtaining ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold comprises:
Obtain ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
Optionally, in an embodiment of the present invention, the described step of obtaining decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value comprises:
Obtain decline stage range coefficient according to following formula;
A
f＝A/(K
f-K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
Optionally, in an embodiment of the present invention, described ascent stage range coefficient A
rdata bit width be N+M position, wherein, high N position is ascent stage range coefficient A
rinteger part, low M position is ascent stage range coefficient A
rfractional part.
Optionally, in an embodiment of the present invention, described decline stage range coefficient A
fdata bit width be N+M position, wherein, high N position is decline stage range coefficient A
finteger part, low M position is decline stage range coefficient A
ffractional part.
Technique scheme has following beneficial effect: the basic framework of technical scheme provided by the invention based on processor+FPGA, without wave memorizer, do not want special porch control circuit yet, therefore simple in structure, realize easily, integrated level is high, cost is lower, and the parameter of pulse signal can be established flexibly, comprise rising edge of a pulse time, pulse trailing edge time, pulse period, the positive pulsewidth of pulse, the negative pulsewidth of pulse.And system response time is fast, prompt sex change is good.In addition, this technical scheme has the resolution of higher porch time, and does not have the dither cycle of low frequency pulse signal.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structured flowchart of the porch regulation device of prior art;
Fig. 2 is a kind of apparatus structure schematic diagram that improves porch temporal resolution that the present invention proposes;
Fig. 3 is the pulse generate cellular construction schematic diagram improving in the device of porch temporal resolution;
Fig. 4 is the pulse parameter processing unit structural representation improving in the device of porch temporal resolution;
Fig. 5 is a kind of method flow diagram that improves porch temporal resolution that the present invention proposes;
Fig. 6 is the structural representation of pulse generate unit in embodiment;
Fig. 7 is the structural representation that improves the device of porch temporal resolution in embodiment;
Fig. 8 is the flow chart that improves the method for porch temporal resolution in embodiment;
Fig. 9 is the schematic diagram that in embodiment, processor passes through waveform parameter acquisition time threshold value and range coefficient.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
From the time, the pulse signal of one-period can be divided into four-stage:
(1) ascent stage, pulse envelope rises;
(2) in the high level stage, pulse envelope maintains high level;
(3) decline stage, pulse envelope declines;
(4) in the low level stage, pulse envelope maintains low level.
As shown in Figure 2, a kind of apparatus structure schematic diagram that improves porch temporal resolution proposing for the present invention.This device comprises: pulse parameter processing unit 201 and pulse generate unit 202.Wherein, pulse parameter processing unit 201 is processed and is obtained frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient for paired pulses parameter; The Information generation pulse signal of pulse generate unit 202 for obtaining according to described pulse parameter processing unit.
As shown in Figure 3, be the pulse generate cellular construction schematic diagram in the device of raising porch temporal resolution.Described pulse generate unit 202 comprises pulse period accumulation module 2021, rising edge multiplier module 2022, trailing edge subtraction block 2023, trailing edge multiplier module 2024, comparison module 2025 and selects module 2026; Wherein, described pulse period accumulation module 2021 is for the clock pulse T in described pulse generate unit
swhen rising edge, accumulate once frequency control word and produce code mutually; Described comparison module 2025 is for comparing to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively by described phase code; Described rising edge multiplier module 2022 is for described phase code and described ascent stage range coefficient are multiplied each other, and result is transferred to described selection module; Described trailing edge subtraction block 2023 is for described decline stage time threshold and described phase code are subtracted each other, and result is transferred to described trailing edge multiplier module; Described trailing edge multiplier module 2024 multiplies each other for result and described decline stage range coefficient that the described trailing edge subtraction block of obtaining is exported, and result is transferred to described selection module; Described selection module 2026 judges the result of exporting the generation of rising edge multiplier module in the time period, the result that trailing edge multiplier module produces, amplitude maximum or the pulse amplitude minimum value of pulse signal for the pulse mark producing according to described comparison module, thereby produces pulse signal.
Alternatively, described pulse signal comprises ascent stage, high level stage, decline stage and low level stage.
Preferably, described pulse parameter comprises pulse period, rising time, positive pulsewidth time, trailing edge time, negative pulsewidth time; Wherein, the 50% threshold value duration of the amplitude that is pulse signal of described positive pulsewidth time from 50% threshold value of ascent stage to the decline stage; The 50% threshold value duration of the amplitude that the described negative pulsewidth time is pulse signal from 50% threshold value of decline stage to ascent stage.
As shown in Figure 4, be the pulse parameter processing unit structural representation in the device of raising porch temporal resolution.Described pulse parameter processing unit 201 comprises FREQUENCY CONTROL word modules 2011, time threshold module 2012 and range coefficient module 2013; Wherein, described FREQUENCY CONTROL word modules 2011 is for obtaining frequency control word according to the pulse period; Described time threshold module 2012 is for obtaining ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period; Described range coefficient module 2013 is for obtaining ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
Optionally, in an embodiment of the present invention, described FREQUENCY CONTROL word modules 2011 obtains frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
Described time threshold module 2012 is obtained ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described time threshold module 2012 is obtained high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described time threshold module 2012 is obtained decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Optionally, in an embodiment of the present invention, described range coefficient module 2013 is obtained ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
Optionally, in an embodiment of the present invention, described range coefficient module 2013 is obtained decline stage range coefficient according to following formula;
A
f＝A/(K
f–K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
More preferably, described ascent stage range coefficient A
rdata bit width be N+M position, wherein, high N position is ascent stage range coefficient A
rinteger part, low M position is ascent stage range coefficient A
rfractional part.
More preferably, described decline stage range coefficient A
fdata bit width be N+M position, wherein, high N position is decline stage range coefficient A
finteger part, low M position is decline stage range coefficient A
ffractional part.
As shown in Figure 5, a kind of method flow diagram that improves porch temporal resolution proposing for the present invention.The method comprises:
Step 501): paired pulses parameter is processed and is obtained frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient;
Step 502): according to described frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient production burst signal.
Wherein, step 501) specifically comprise:
Step 5011): at clock pulse T
swhen rising edge, accumulate once frequency control word and produce code mutually;
Step 5012): described phase code is compared to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively;
Step 5013): described phase code and described ascent stage range coefficient are multiplied each other and obtain the pulse envelope of ascent stage;
Step 5014): described decline stage time threshold and described phase code are subtracted each other;
Step 5015): the difference between decline stage time threshold and described phase code and described decline stage range coefficient are multiplied each other and obtain the pulse envelope of decline stage;
Step 5016): the amplitude maximum or the pulse amplitude minimum value that judge the pulse envelope of exporting ascent stage in the time period, the pulse envelope of decline stage, pulse signal according to described pulse mark produce pulse signal.
Wherein, step 502) specifically comprise:
Step 5021): obtain frequency control word according to the pulse period;
Wherein, obtain frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
Obtain high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Obtain decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Step 5022): obtain ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period;
Obtain ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
Step 5023): obtain ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
Obtain ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
Obtain decline stage range coefficient according to following formula;
A
f＝A/(K
f–K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
Embodiment 1:
The present embodiment utilizes pulse period accumulation device periodically to count, and comparator is by the ascent stage time threshold K of count results and processor setting
r, high level phases-time threshold k
h, decline stage time threshold K
fcompare, count results is divided into above-mentioned four-stage: the pulse envelope that produces ascent stage with rising edge multiplier, with trailing edge subtracter and the pulse envelope of trailing edge multiplier generation decline stage, the comparative result of exporting according to comparator with selector selects output corresponding to four-stage to produce pulse signal.
The present embodiment adopts FPGA to produce pulse signal as pulse generate unit, as shown in Figure 6, is the structural representation of pulse generate unit in embodiment.Comprise: processor interface 1, clock module 2, pulse period accumulation device 3, comparator 4, rising edge multiplier 5, trailing edge subtracter 6, trailing edge multiplier 7, selector 8.
(1) processor interface 1: be the communication interface of pulse generate unit and processor, the instruction that parsing processor issues, is then transmitted to inner other modules;
(2) clock module 2, for other module provides clock, the cycle is T
s;
(3) pulse period accumulation device 3, produces periodically counting output, and count results is called code mutually.At each clock pulse T
swhen rising edge arrives, just accumulate once frequency control word K
0produce code mutually.With N indicating impulse periodic accumulation device and K
0bit wide, mutually the data bit width of code is also N, the scope of phase code value is 0～2
n-1.Frequency control word K
0arranged by processor, the relation of it and pulse period T is as formula 1, and processor is according to formula 1 calculated rate control word K
0.
K
0=2
N*T
S/T （1）
(4) comparator 4, three time thresholds that the phase code that pulse period accumulation device 3 is produced and the bit wide of processor setting are N: ascent stage time threshold K
r, high level phases-time threshold k
h, decline stage time threshold K
fcompare respectively, produce the pulse flag bit of 2 bit bit wides.
As phase code≤K
r, pulse flag bit equals " 00 ", and indicating impulse is in ascent stage;
Work as K
r< is code≤K mutually
h, pulse flag bit equals " 01 ", and indicating impulse is in the high level stage;
Work as K
h< is code≤K mutually
f, pulse flag bit equals " 10 ", and indicating impulse is in the decline stage;
As phase code >K
f, pulse flag bit equals " 11 ", and indicating impulse is in the low level stage.
(5) rising edge multiplier 5, the ascent stage range coefficient A that the phase code that pulse period accumulation device 3 is produced and processor arrange
rmultiply each other, because code increases progressively mutually, therefore product also increases progressively, and the pulse envelope as ascent stage is given selector by product.
With the amplitude maximum of A indicating impulse signal, processor calculates A according to formula 2
r:
A
r=A/K
r （2）
Especially, in order to ensure the resolution of rising edge of a pulse time, A
rdata bit width be N+M position, the wherein A of high N bit representation
rinteger part, the A of low M bit representation
rfractional part.
(6) trailing edge subtracter 6, with decline stage time threshold K
fthe phase code producing with pulse period accumulation device 3 subtracts each other, and difference is given trailing edge multiplier;
(7) trailing edge multiplier 7, the decline stage range coefficient A that the difference that trailing edge subtracter 6 is produced and processor arrange
fmultiply each other, because difference is successively decreased, therefore product also successively decreases, and the pulse envelope as the decline stage is given selector by product.
Processor calculates A according to formula 3
f:
A
f＝A/(K
f–K
h)（3）
Especially, in order to ensure the resolution of pulse trailing edge time, A
fdata bit width be N+M position, the wherein A of high N bit representation
finteger part, the A of low M bit representation
ffractional part.
Therefore, the pulse envelope of ascent stage, the pulse envelope of decline stage produce respectively, and therefore rising edge of a pulse time, trailing edge time can arrange respectively.
(8) selector 8, the output that produces pulse signal according to the pulse flag bit of comparator 4.
When pulse flag bit equals " 00 ", select the product of rising edge multiplier 5, as the pulse envelope of ascent stage;
When pulse flag bit equals " 01 ", strobe pulse amplitude A, as the pulse envelope in high level stage;
When pulse flag bit equals " 10 ", select the product of trailing edge multiplier 7, as the pulse envelope of decline stage;
When pulse flag bit equals " 11 ", strobe pulse amplitude 0, as the pulse envelope in low level stage.
Pulse signal genration method provided by the present invention and the control method of porch time, mainly, in the inner realization of FPGA, be different from the pulse circuit for regulating and controlling that analogue device is realized, and also has very large difference with the wave table mode based on DDS technology.Because time threshold and range coefficient can be arranged by processor, therefore the parameter of the pulse signal of final output can arrange flexibly.The degree of depth that is limited to wave memorizer from the resolution of porch time in wave table mode is different, the present invention does not use wave memorizer, but used the large and integer part of data bit width and fractional part all can participate in the rising edge multiplier and the trailing edge multiplier that calculate, effectively improve the resolution of porch time; And the number of samples of pulse ascent stage, decline stage is not subject to the impact of low-frequency pulse, there is not low-frequency jitter problem.
As shown in Figure 7, for improving the structural representation of device of porch temporal resolution in embodiment.Comprise:
(1) GUI unit 701, by GUI(graphical user interface) unit accept user control, user arranges the parameter (comprising porch time, pulse period, pulse amplitude etc.) of pulse signal by GUI, these parameters are passed to processor by GUI;
(2) processor 302, accepts the parameter input of GUI, through calculating acquisition time threshold value and range coefficient, and occurs to FPGA703 by communication bus.
(3) FPGA703, is served as by FPGA, according to the pulse signal of the parameter generating digital of processor configuration.
Communication bus protocol between processor and pulse generate unit can be very flexible, and communication bus protocol can be standard, can be also self-defining.As previously mentioned, the instruction that the processor interface 1 meeting parsing processor of FPGA 703 inside issues, is then transmitted to inner other modules.
The pulse signal that FPGA 703 exports is digital form, and its bit wide equals next stage DAC(digital to analog converter) data bit width.
(4) DAC(digital to analog converter) 704: the pulse signal of the digital form that FPGA 703 is exported is converted to analog form;
(5) analog circuit 705: the pulse signal to analog form is further processed, comprises decay, amplification etc. in filtering, amplitude, final output pulse signal.
As shown in Figure 8, for improving the flow chart of method of porch temporal resolution in embodiment.The method comprises:
S801, user arranges pulse parameter by GUI unit.
S802, processor calculates time threshold and range coefficient according to pulse parameter, and gives pulse generate unit.Compared with wave table mode of the prior art, the calculating of the processor in the present invention is fairly simple, without long, complex calculations consuming time, can not take how many processor resources.If user has revised pulse parameter, processor only need recalculate result is occurred to pulse generate unit, and therefore system response time is fast.
S803, the pulse period accumulation device of FPGA inside produces code periodically mutually under clock according to frequency control word.Because be to produce pulse envelope by phase code, there is not the dither cycle problem of limited the caused low-frequency pulse of storage depth of wave memorizer.
S804, the rising edge multiplier of FPGA inside and trailing edge subtracter produce respectively the pulse envelope of ascent stage and the pulse envelope of decline stage.Because the range coefficient of integer and fractional part can participate in phase multiplication, and multiplier bit wide is larger, and therefore the resolution of porch time can be very high.
S805, the selector of FPGA inside produces the pulse signal of digital form according to the pulse flag bit of comparator output.
S806 exports the pulse signal of analog form after DAC and analog circuitry processes.
In above-described embodiment, the porch time that processor arranges user, positive pulsewidth time, negative pulsewidth time, the pulse period is converted to time threshold and range coefficient sends to pulse generate unit, by pulse generate unit according to the pulse signal of these parameter generating digital forms.Wherein the relation of pulse period and frequency control word is provided by formula 1.Fig. 4 has illustrated the relation between these parameters.
As shown in Figure 9, for processor in embodiment is by the schematic diagram of waveform parameter acquisition time threshold value and range coefficient.In Fig. 9, the first width figure has illustrated the amplitude of pulse period accumulation device output phase code and the relation of time, and the longitudinal axis is the amplitude of phase code, and transverse axis is time t; Fig. 9 the second width figure has illustrated the amplitude of pulse signal and the relation of time that FPGA produces, and the longitudinal axis is the amplitude of pulse signal, and transverse axis is time t.
Divide from time t, [0, t0] is pulse ascent stage, and [t0, t1] is the pulse high level stage, and [t1, t2] is the pulse decline stage, and [t2, T] is the pulses low stage.
The pulse parameter that user arranges is: pulse period T, rising time tr, positive pulsewidth time th, trailing edge time tf, negative pulsewidth time tL.Wherein, the 50% threshold value duration that the positive pulsewidth timing definition of pulse is pulse amplitude from 50% threshold value of ascent stage to the decline stage, the 50% threshold value duration that the negative pulsewidth timing definition of pulse is pulse amplitude from 50% threshold value of decline stage to ascent stage.According to Fig. 9, there is following relational expression:
T=th+tL；
tr=t0/1.25；
tf＝(t2-t1)/1.25；
th=t0/2+(t1-t0)+(t2-t1)/2=(t1+t2-t0)/2。
By above relational expression, derive following relational expression:
t0=1.25*tr；
t1=(2*th-1.25*tf+1.25*tr)*0.5；
t2=(2*th+1.25*tf+1.25*tr)*0.5。
Represent the maximum 2 of phase code with KI
n-1, can derive following formula:
K
r=(1.25*tr)*KI/T （4）
K
h=(2*th-1.25*tf+1.25*tr)*0.5*KI/T （5）
K
f=(2*th+1.25*tf+1.25*tr)*0.5*KI/T （6）
Processor calculates respectively three time thresholds according to formula 4, formula 5, formula 6 by pulse parameter: ascent stage time threshold K
r, high level phases-time threshold k
h, decline stage time threshold K
f; Calculate respectively two range coefficients according to formula 2, formula 3 by pulse parameter: ascent stage range coefficient A
r, decline stage range coefficient A
f.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range being not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (26)
1. a device that improves porch temporal resolution, is characterized in that, this device comprises:
Pulse parameter processing unit, processes and obtains frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient for paired pulses parameter;
Pulse generate unit, for the Information generation pulse signal obtaining according to described pulse parameter processing unit.
2. device according to claim 1, is characterized in that, described pulse generate unit comprises pulse period accumulation module, rising edge multiplier module, trailing edge subtraction block, trailing edge multiplier module, comparison module and selection module;
Described pulse period accumulation module, for the clock pulse T in described pulse generate unit
swhen rising edge, accumulate once frequency control word and produce code mutually;
Described comparison module, for comparing to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively by described phase code;
Described rising edge multiplier module, for described phase code and described ascent stage range coefficient are multiplied each other, and transfers to described selection module by result;
Described trailing edge subtraction block, for described decline stage time threshold and described phase code are subtracted each other, and transfers to described trailing edge multiplier module by result;
Described trailing edge multiplier module, for result and the described decline stage range coefficient of the described trailing edge subtraction block output of obtaining are multiplied each other, and transfers to described selection module by result;
Described selection module, judge the result of exporting the generation of rising edge multiplier module in the time period, the result that trailing edge multiplier module produces, amplitude maximum or the pulse amplitude minimum value of pulse signal for the pulse mark producing according to described comparison module, thereby produce pulse signal.
3. device according to claim 1 and 2, is characterized in that, described pulse signal comprises ascent stage, high level stage, decline stage and low level stage.
4. device according to claim 2, is characterized in that, described pulse parameter comprises pulse period, rising time, positive pulsewidth time, trailing edge time, negative pulsewidth time; Wherein, the 50% threshold value duration of the amplitude that is pulse signal of described positive pulsewidth time from 50% threshold value of ascent stage to the decline stage; The 50% threshold value duration of the amplitude that the described negative pulsewidth time is pulse signal from 50% threshold value of decline stage to ascent stage.
5. device according to claim 4, is characterized in that, described pulse parameter processing unit comprises FREQUENCY CONTROL word modules, time threshold module and range coefficient module;
Described FREQUENCY CONTROL word modules, for obtaining frequency control word according to the pulse period;
Described time threshold module, for obtaining ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period;
Described range coefficient module, for obtaining ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
6. device according to claim 5, is characterized in that, described FREQUENCY CONTROL word modules obtains frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
7. device according to claim 5, is characterized in that, described time threshold module is obtained ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
8. device according to claim 5, is characterized in that, described time threshold module is obtained high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
9. device according to claim 5, is characterized in that, described time threshold module is obtained decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
10. device according to claim 5, is characterized in that, described range coefficient module is obtained ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
11. devices according to claim 5, is characterized in that, described range coefficient module is obtained decline stage range coefficient according to following formula;
A
f＝A/(K
f–K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
12. according to the device described in claim 4 ~ 11, it is characterized in that, described ascent stage range coefficient A
rdata bit width be N+M position, wherein, high N position is ascent stage range coefficient A
rinteger part, low M position is ascent stage range coefficient A
rfractional part.
13. according to the device described in claim 4 ~ 11, it is characterized in that, described decline stage range coefficient A
fdata bit width be N+M position, wherein, high N position is decline stage range coefficient A
finteger part, low M position is decline stage range coefficient A
ffractional part.
14. 1 kinds are improved the method for porch temporal resolution, it is characterized in that, the method comprises:
Paired pulses parameter is processed and is obtained frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient;
According to described frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient production burst signal.
15. methods according to claim 14, it is characterized in that, the described step according to described frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient production burst signal comprises:
At clock pulse T
swhen rising edge, accumulate once frequency control word and produce code mutually;
Described phase code is compared to produce pulse mark with described ascent stage time threshold, high level phases-time threshold value, decline stage time threshold respectively;
Described phase code and described ascent stage range coefficient are multiplied each other and obtain the pulse envelope of ascent stage;
Described decline stage time threshold and described phase code are subtracted each other;
Difference between decline stage time threshold and described phase code and described decline stage range coefficient are multiplied each other and obtain the pulse envelope of decline stage;
The amplitude maximum or the pulse amplitude minimum value that judge the pulse envelope of exporting ascent stage in the time period, the pulse envelope of decline stage, pulse signal according to described pulse mark produce pulse signal.
16. according to the method described in claims 14 or 15, it is characterized in that, described pulse signal comprises ascent stage, high level stage, decline stage and low level stage.
17. methods according to claim 15, is characterized in that, described pulse parameter comprises pulse period, rising time, positive pulsewidth time, trailing edge time, negative pulsewidth time; Wherein, the 50% threshold value duration of the amplitude that is pulse signal of described positive pulsewidth time from 50% threshold value of ascent stage to the decline stage; The 50% threshold value duration of the amplitude that the described negative pulsewidth time is pulse signal from 50% threshold value of decline stage to ascent stage.
18. methods according to claim 17, it is characterized in that, described paired pulses parameter is processed the step of obtaining frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient and is comprised:
Obtain frequency control word according to the pulse period;
Obtain ascent stage time threshold according to rising time and pulse period; Obtain high level phases-time threshold value and decline stage time threshold according to positive pulsewidth time, trailing edge time, rising time and pulse period;
Obtain ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold; Obtain decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value.
19. methods according to claim 18, is characterized in that, the described step of obtaining frequency control word according to the pulse period comprises:
Obtain frequency control word according to following formula;
K
0＝2
N*T
s/T
Wherein, K
0for the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, T
sfor the clock cycle of described pulse generate unit; T is the pulse period.
20. methods according to claim 18, is characterized in that, the described step of obtaining ascent stage time threshold according to rising time and pulse period comprises:
Obtain ascent stage time threshold according to following formula;
K
r＝(1.25*tr)*KI/T
Wherein, K
rfor ascent stage time threshold, tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
21. methods according to claim 18, is characterized in that, the step that positive pulsewidth time of described basis, trailing edge time, rising time and pulse period are obtained high level phases-time threshold value and decline stage time threshold comprises:
Obtain high level phases-time threshold value according to following formula;
K
h＝(2*th-1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
hfor high level phases-time threshold value, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
22. methods according to claim 18, is characterized in that, the step that positive pulsewidth time of described basis, trailing edge time, rising time and pulse period are obtained high level phases-time threshold value and decline stage time threshold comprises:
Obtain decline stage time threshold according to following formula;
K
f＝(2*th+1.25*tf+1.25tr)*0.5*KI/T
Wherein, K
ffor decline stage time threshold, th is the positive pulsewidth time, and tf is the trailing edge time, and tr is rising time, and KI is the maximum of phase code, is 2
n-1, T is the pulse period.
23. methods according to claim 18, is characterized in that, the described step of obtaining ascent stage range coefficient according to the amplitude maximum of pulse signal and described ascent stage time threshold comprises:
Obtain ascent stage range coefficient according to following formula;
A
r=A/K
r
Wherein, A
rfor ascent stage range coefficient, the amplitude maximum that A is pulse signal, K
rfor ascent stage time threshold.
24. methods according to claim 18, is characterized in that, the described step of obtaining decline stage range coefficient according to the amplitude maximum of pulse signal, described ascent stage time threshold and high level phases-time threshold value comprises:
Obtain decline stage range coefficient according to following formula;
A
f＝A/(K
f–K
h)
Wherein, A
ffor decline stage range coefficient, the amplitude maximum that A is pulse signal, K
hfor high level phases-time threshold value, K
ffor decline stage time threshold.
25. according to the method described in claim 17 ~ 24, it is characterized in that, described ascent stage range coefficient A
rdata bit width be N+M position, wherein, high N position is ascent stage range coefficient A
rinteger part, low M position is ascent stage range coefficient A
rfractional part.
26. according to the method described in claim 17 ~ 24, it is characterized in that, described decline stage range coefficient A
fdata bit width be N+M position, wherein, high N position is decline stage range coefficient A
finteger part, low M position is decline stage range coefficient A
ffractional part.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634444A (en) * | 2015-12-24 | 2016-06-01 | 福建利利普光电科技有限公司 | Square wave generation method based on DDS signal generator |
| CN106896309A (en) * | 2015-12-17 | 2017-06-27 | 上海和辉光电有限公司 | Signal processing apparatus and method, signal offset detection system and method |
| CN107835000A (en) * | 2017-12-08 | 2018-03-23 | 成都前锋电子仪器有限责任公司 | A kind of output circuit for pulse pattern generator |
| CN108513618A (en) * | 2017-03-29 | 2018-09-07 | 深圳市大疆创新科技有限公司 | Pulse information measurement method and relevant apparatus, mobile platform |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010151891A2 (en) * | 2009-06-26 | 2010-12-29 | Qualcomm Incorporated | Predetermined duty cycle signal generator |
| CN102361445A (en) * | 2011-08-23 | 2012-02-22 | 中国空间技术研究院 | High-accuracy protocol pulse generator based on digital frequency synthesizer |
| CN102723931A (en) * | 2012-07-02 | 2012-10-10 | 优利德科技(成都)有限公司 | Wide-dynamic high-accuracy and edge time adjustable impulse wave producing method |
-
2012
- 2012-12-10 CN CN201210529760.2A patent/CN103873017B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010151891A2 (en) * | 2009-06-26 | 2010-12-29 | Qualcomm Incorporated | Predetermined duty cycle signal generator |
| CN102361445A (en) * | 2011-08-23 | 2012-02-22 | 中国空间技术研究院 | High-accuracy protocol pulse generator based on digital frequency synthesizer |
| CN102723931A (en) * | 2012-07-02 | 2012-10-10 | 优利德科技(成都)有限公司 | Wide-dynamic high-accuracy and edge time adjustable impulse wave producing method |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110474621A (en) * | 2014-08-22 | 2019-11-19 | 朗姆研究公司 | Subpulse during state |
| CN110474621B (en) * | 2014-08-22 | 2024-04-09 | 朗姆研究公司 | Sub-pulses during a state |
| CN106896309A (en) * | 2015-12-17 | 2017-06-27 | 上海和辉光电有限公司 | Signal processing apparatus and method, signal offset detection system and method |
| CN106896309B (en) * | 2015-12-17 | 2019-08-06 | 上海和辉光电有限公司 | Signal processing apparatus and method, signal offset detection system and method |
| CN105634444A (en) * | 2015-12-24 | 2016-06-01 | 福建利利普光电科技有限公司 | Square wave generation method based on DDS signal generator |
| CN108512531A (en) * | 2017-02-28 | 2018-09-07 | 长城汽车股份有限公司 | Impulse wave generating means, vehicle and method |
| CN108513618A (en) * | 2017-03-29 | 2018-09-07 | 深圳市大疆创新科技有限公司 | Pulse information measurement method and relevant apparatus, mobile platform |
| CN108513618B (en) * | 2017-03-29 | 2022-06-21 | 深圳市大疆创新科技有限公司 | Pulse information measuring method, related device and mobile platform |
| CN107835000A (en) * | 2017-12-08 | 2018-03-23 | 成都前锋电子仪器有限责任公司 | A kind of output circuit for pulse pattern generator |
| CN107835000B (en) * | 2017-12-08 | 2024-02-06 | 成都前锋电子仪器有限责任公司 | Output circuit for pulse code pattern generator |
| CN108988830A (en) * | 2018-08-03 | 2018-12-11 | 中国电子科技集团公司第二十四研究所 | A kind of pulse signal generation circuit of programmable edge time |
| CN108988830B (en) * | 2018-08-03 | 2022-05-03 | 中国电子科技集团公司第二十四研究所 | Pulse signal generating circuit capable of programming edge time |
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