CN106896309A - Signal processing apparatus and method, signal offset detection system and method - Google Patents
Signal processing apparatus and method, signal offset detection system and method Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The invention discloses a kind of signal processing apparatus and method, signal offset detection system and method, the signal processing apparatus include signal input module, for receiving a pulse signal；Signal processing module, for confirming level change location in the pulse signal, and level change location in the pulse signal adds an ignore-tag；Signal output module, for exporting the pulse signal after the signal processing module treatment.The present invention adds ignore-tag in the interference position of influence pulsed test signal result, so that when line-pulse signal skew test is entered, the logic level that test device can cancel at interference position compares, and overcomes the influence of level-shift at interference position, improves the accuracy of pulsed test signal.
Description
Technical field
The present invention relates to chip testing field, in particular to a kind of signal processing apparatus and method, letter
Number offset detection system and method.
Background technology
With the raising of IC complexity, also when the river rises the boat goes up therewith for the complexity of its test, some
The testing cost of device has even accounted for the major part of chip cost.Large scale integrated circuit may require that several
The test of the voltage, electric current and sequential of hundred times, and the functional test step of million times is ensureing device
It is complete correct.The test of such complexity is realized, cannot be completed by hand, therefore to use
ATE (ATE, Automated Test Equipment).
ATE is a kind of aggregate of the tester controlled by high-performance computer, is by tester and meter
The test device that calculation machine is combined, computer controls test hard by the instruction of testing results program
Part.The most basic requirement of test device can be rapidly and reliably to repeat consistent test result, i.e.,
Speed, reliability and stability.To keep correctness and uniformity, test device to need to carry out periodically
Verification, is used to ensure the precision of signal source and measuring unit.
When the logic level for carrying out signal is tested, because of test frequency (clock) left and right of test device
Drift, cause with actual measurement IC comparings when, often signal logic high (high) and
Logic low (low) change edge is sometimes " 0 " and is sometimes " 1 ", due to being patrolled in test signal
Collect the uncertain of level change edge logic level so that the result of test can be very unstable, it is impossible to accurate
Really whether test IC breaks down.
The content of the invention
For the problem that prior art is present, an object of the present invention is to provide a kind of being used for chip survey
The signal processing apparatus of the level interference position addition ignore-tag in the test signal used during examination and side
Method.
Another object of the present invention is to provide a kind of signal skew accurate signal offset detection of test result
System and method.
To achieve the above object, signal processing apparatus of the invention, including：
Signal input module, for receiving a pulse signal；
Signal processing module, for confirming level change location in the pulse signal, and in pulse letter
Number level change location add an ignore-tag；And
Signal output module, for exporting the pulse signal after the signal processing module treatment.
Further, the pulse test signal that the uses when pulse signal is by chip testing.
Further, the signal processing module includes：
Module is confirmed, for confirming level change location in the pulse signal；And
Mark module, the ignore-tag is added for the level change location in the pulse signal.
Further, the level change location be the pulse signal in from high level to low level position and
From low level to the position of high level.
Further, the confirmation module is used to confirm in the pulse signal from high level to low level first
Position and from low level to the second place of high level.
Signal processing method of the invention, comprises the following steps：
Receive a pulse signal；
Confirm level change location in the pulse signal, and level change location in the pulse signal adds
Plus an ignore-tag；And
The output pulse signal after treatment.
Further, the pulse test signal that the uses when pulse signal is by chip testing.
Further, the level change location be the pulse signal in from high level to low level first
Put and from low level to the second place of high level.
Further, level change location in the pulse signal is confirmed, and in the level change of the pulse signal
Changing the step of an ignore-tag is added in position includes：
Confirm first position described in the pulse signal and/or the second place, and at described first
Put and/or the second place adds the ignore-tag.
Signal offset detection system of the invention, for the signal testing of chip, including：
One signal processing apparatus, for receiving pulse test signal, and in the electricity of described pulse test signal
Flat change location adds an ignore-tag, and exports a pulse process signal；And
One test device, the actual measurement pulse letter for receiving the pulse process signal and chip output
Number, and the logic level of the correspondence position relatively in the pulse process signal and the actual measurement pulse signal is
It is no consistent；
Wherein, in the test device pulse process signal in addition to the level change location
3rd position is electric with the logic of the 4th position corresponding with the 3rd position in the actual measurement pulse signal
It is flat whether consistent.
Further, the level change location be the pulse signal in from high level to low level first
Put and from low level to the second place of high level.
Further, patrolling when the test device pulse process signal and the actual measurement pulse signal
When volume level is consistent, represent that the result of chip output is correct；When the test device pulse treatment
When the logic level of signal and the actual measurement pulse signal is inconsistent, the result mistake of chip output is represented.
Further, the signal processing apparatus include：
Signal input module, for receiving the pulse test signal；
Signal processing module, for confirming level change location in the pulse test signal, and in the arteries and veins
The level change location for rushing test signal adds the ignore-tag；And
Signal output module, the pulse process signal after being processed for output.
Further, the signal processing module includes：
Module is confirmed, for confirming level change location in the pulse test signal；
Mark module, the ignore-tag is added for the level change location in the pulse test signal.
Further, the test device includes：
Signal input module, for receiving the pulse process signal and the actual measurement pulse signal；
Signal reading module, the level for adding the ignore-tag in the pulse process signal for reading becomes
Change position；And
Signal comparison module, for receiving the result after being read through the signal reading module, and detects described
The ignore-tag of level change location described in pulse process signal, and relatively more described pulse treatment letter
Whether the 3rd position in number is consistent with the logic level of the 4th position in the actual measurement pulse signal.
Further, the ignore-tag of the signal comparison module in the pulse process signal is detected
When, cancel the logic level of the pulse process signal and the actual measurement pulse signal at the ignore-tag
Compare operation.
Signal bias detecting method of the invention, for the signal testing of chip, comprises the following steps：
Confirm level change location in pulse test signal, mark is ignored in level change location addition one
Note, and export pulse process signal；
The 3rd position compared in the pulse process signal in addition to the level change location is defeated with chip
Whether the logic level of fourth position corresponding with the 3rd position is consistent in the actual measurement pulse signal for going out；
Wherein, when the pulse process signal is consistent with the logic level of the actual measurement pulse signal, represent
The result of chip output is correct；
When the logic level of the pulse process signal and the actual measurement pulse signal is inconsistent, core is represented
The result mistake of piece output.
The present invention adds ignore-tag in the interference position of influence pulsed test signal result so that carrying out arteries and veins
When rushing signal skew test, the logic level that test device can cancel at interference position compares, and overcomes interference
The influence of level-shift at position, improves the accuracy of pulsed test signal.
Brief description of the drawings
Accompanying drawing herein is merged in specification and constitutes the part of this specification, shows and meets the present invention
Embodiment, and together with specification be used for explain principle of the invention.
Fig. 1 is the schematic flow sheet of the signal processing method of one example embodiment of the present invention；
Figure 1A and Figure 1B are respectively the pulse after pulse test signal and signal transacting before signal transacting
The schematic diagram of process signal；
Fig. 2 is the structural representation of the signal processing apparatus of one example embodiment of the present invention；
Fig. 3 is the schematic flow sheet of the signal bias detecting method of one example embodiment of the present invention；
Fig. 4 is the structural representation of the signal offset detection system of one example embodiment of the present invention.
Specific embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following retouches
State when being related to accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.
Implementation method described in following exemplary embodiment does not represent all implementations consistent with the present invention
Mode.Conversely, they are only and phase in terms of some described in detail in such as appended claims, of the invention
The example of consistent apparatus and method.
Fig. 1 is the schematic flow sheet of the signal processing method according to an exemplary embodiment.
As shown in figure 1, signal processing method of the invention, comprises the following steps：
Step S11：Return pulse signal.The waveform of pulse signal is as shown in Figure 1A.In the present embodiment
The pulse test signal that pulse signal can be tested as the output signal of chip, and be redefined for and chip
Output signal it is normal when pulse signal type and waveform it is consistent.For example, when the output of test chip
When signal is the square-wave signal of reflecting voltage, pulse test signal is from the output signal identical electricity with chip
Pressure square-wave signal.The species of pulse test signal and waveform can with the type of the output signal of chip to be measured and
Waveform and change, such as pulse test signal can also be changed into therewith reflect electric current square-wave signal, certainly its
Waveform can also be common triangular wave, sawtooth waveforms etc., and the species and waveform of pulse signal are not limited thereto.
Step S12：Confirm level change location in pulse signal.Wherein, level change location is pulse letter
The level of logic level starts the position of change in number.For example, from high level to low electricity in pulse signal
First position between flat and from low level to the second place between high level.
Step S13：Ignore-tag is added in the level change location of pulse signal.For example, in pulse signal
In from high level to the first position addition ignore-tag and from low level between high level between low level
The second place addition ignore-tag.If if only had from high level between low level in pulse signal
First position, then only high level between low level position add ignore-tag., whereas if only
With from low level to the second place between high level, then only add in low level to the position between high level
Plus ignore-tag.Therefore, the position of addition ignore-tag can be according to the waveform situation of actual pulse signal
Depending on.The ignore-tag of addition is " X ", its can with device being tested when signal compares it is automatic cancel into
Row compares.
Step S14：The pulse exported after treatment to the signal input part of apparatus for testing chip processes letter
Number.The waveform of pulse process signal is as shown in Figure 1B.After one signal input part reception processing of test device
Pulse process signal, another signal input part of test device receives the actual measurement pulse signal of chip, passes through
Pulse process signal and actual measurement pulse signal are relatively carried out into the test of chip signal output, to judge chip
Whether break down.The follow-up signal of apparatus for testing chip compares testing process will launch in the implementation after
Introduce, do not do excessive explanation herein.
Above-mentioned signal processing method can be realized by software, naturally it is also possible to by known various hardware electricity
The combination on road realizes, the present invention is not with the difference of the implementation of signal processing method to limit.
Fig. 2 is the structural representation of the signal processing apparatus according to an exemplary embodiment.
As shown in Fig. 2 signal processing apparatus, including signal input module 21, the and of signal processing module 22
Signal output module 23.
Signal input module 21 is used for return pulse signal.Pulse signal can be as the output signal of chip
The pulse test signal of test, and pulse signal when being redefined for normal with the output signal of chip class
Type and waveform are consistent.For example, when the output signal of test chip is the square-wave signal of reflecting voltage, arteries and veins
Test signal is rushed from the output signal identical voltage square wave signal with chip.The species of pulse test signal
Can change, such as pulse test signal with the type of the output signal of chip to be measured and waveform with waveform
Can therewith be changed into reflecting the square-wave signal of electric current, certain its waveform can also be common triangular wave, sawtooth
Ripple etc., the species and waveform of pulse signal are not limited thereto.
Signal processing module 22 is used to confirm level change location in pulse signal, and in the electricity of pulse signal
Flat change location adds ignore-tag.Wherein, level change location is the level of logic level in pulse signal
Size starts the position of change.For example, in pulse signal from high level to the first position between low level and
From low level to the second place between high level.Signal processing module 22 is confirming level change location
Afterwards, the level change location in pulse signal adds ignore-tag.For example, from high level in pulse signal
To the first position addition ignore-tag between low level and from low level to the second place between high level
Addition ignore-tag.If if only had from high level to first between low level in pulse signal
Put, then only add ignore-tag in high level to the position between low level., whereas if only having from low
Level then only ignores mark to the second place between high level in low level to the position addition between high level
Note, depending on it can be according to actual conditions.The ignore-tag of addition is " X ", and it can be with device being tested
When signal compares, automatic cancellation is compared.
Level change location and the level change position in pulse signal in pulse signal are confirmed in the present embodiment
Put addition ignore-tag to be not limited to only be processed by a module, it is of course possible to which that infers can also
Two modules are split as to perform the operation for confirming and adding ignore-tag respectively.For example, as shown in Fig. 2
Signal processing module 22 can include validating that module 221 and mark module 222.Confirm that module 221 is used for
Confirm level change location in pulse signal.Mark module 222 is used for the level change location in pulse signal
Addition ignore-tag.
Signal output module 23 is used to export the pulse process signal after being processed through signal processing module 22.Arteries and veins
Rushing process signal can be output to test equipment, used as the ginseng that the actual measurement pulse signal exported with chip compares
Examine signal.
Fig. 3 is the schematic flow sheet of the signal bias detecting method according to an exemplary embodiment.
As shown in figure 3, the signal bias detecting method of one example embodiment of the present invention, for detecting core
Whether piece output signal is normal, comprises the following steps：
Step S31：Confirm level change location in pulse test signal.Wherein, level change location is arteries and veins
The level for rushing logic level in signal starts the position of change.For example, in pulse signal from high level extremely
First position between low level and from low level to the second place between high level.
Step S32：Ignore-tag is added in level change location.For example, from high level in pulse signal
To the first position addition ignore-tag between low level and from low level to the second place between high level
Addition ignore-tag.If if only had from high level to first between low level in pulse signal
Put, then only add ignore-tag in high level to the position between low level., whereas if only having from low
Level then only ignores mark to the second place between high level in low level to the position addition between high level
Note.Therefore, depending on the position of addition ignore-tag can be according to the waveform situation of actual pulse signal.Add
Plus ignore-tag be " X ", it can automatically be cancelled with device being tested and comparing.
Step S33：The pulse exported after treatment to the signal input part of apparatus for testing chip processes letter
Number.Pulse process signal after one signal input part reception processing of test device, another letter of test device
Number input receives the actual measurement pulse signal of chip, compares by by pulse process signal and actual measurement pulse signal
To carry out the test of chip signal output, to judge whether chip breaks down.
Step S34：The 3rd position compared in pulse process signal in addition to level change location is defeated with chip
Whether the logic level of fourth position corresponding with the 3rd position is consistent in the actual measurement pulse signal for going out.Its
In, the 3rd position outside level change location is high level and low level position in pulse process signal.
In theory when chip is output as normal, the waveform of pulse process signal is substantially identical to the actual measurement of chip output
The waveform of pulse signal.Chip is judged with the comparative result of actual measurement pulse signal according to pulse process signal
Whether break down.For example, when pulse process signal is consistent with the logic level of actual measurement pulse signal, table
Show that the result of chip output is correct, that is, chip is normal.Conversely, when pulse process signal and actual measurement pulse letter
Number logic level it is inconsistent when, represent the result mistake of chip output, that is, chip failure.
Fig. 4 is the structural representation of the signal offset detection system of one example embodiment of the present invention.
As shown in figure 4, the signal offset detection system of one embodiment of the invention, for the signal testing of chip,
Including：
Signal processing apparatus 4, mark is ignored in the level change location addition one of the pulse test signal for being received
Note, and export a pulse process signal.Wherein, level change location is the electricity of logic level in pulse signal
Flat size starts the position of change.For example, from high level to the first position between low level in pulse signal
And from low level to the second place between high level.
Test device 5, the actual measurement pulse signal for receiving pulse process signal and chip output, than
Whether the pulse process signal is consistent with the logic level of the correspondence position in the actual measurement pulse signal.
Wherein, test device 5 compares the 3rd position in pulse process signal in addition to level change location and actual measurement
Whether the logic level of fourth position corresponding with the 3rd position is consistent in pulse signal.Wherein, level becomes
It is high level and low level position in pulse process signal to change the 3rd position outside position.In theory in core
When piece is output as normal, the waveform of pulse process signal is substantially identical to the actual measurement pulse signal of chip output
Waveform.Judge whether chip occurs event with the comparative result of actual measurement pulse signal according to pulse process signal
Barrier.For example, when pulse process signal is consistent with the logic level of actual measurement pulse signal, representing chip output
Result it is correct, that is, chip is normal.Conversely, when pulse process signal and the logic electricity of actual measurement pulse signal
When flat inconsistent, the result mistake of chip output, that is, chip failure are represented.
Signal processing apparatus 4 include signal input module 41, signal processing module 42 and signal output module
43.Signal input module 41 is used to receive pulse test signal.Wherein, the waveform reason of pulse test signal
It is substantially the same by the waveform of the upper actual measurement pulse signal exported with chip.Signal processing module 42 is used to confirm
Level change location in pulse test signal, and it is described suddenly in the level change location addition of pulse test signal
Slightly mark.Wherein, level change location starts the position of change for the level of logic level in pulse signal
Put.For example, from high level to the first position between low level and from low level to high level in pulse signal
Between the second place.The pulse process signal that signal output module 43 is used for after output treatment.
Signal processing module 42 includes validating that module 421 and mark module 422.Confirm that module 421 is used for
Confirm level change location in pulse test signal.For example, from high level between low level in pulse signal
First position and from low level to the second place between high level.Signal processing module 42 is being confirmed
After level change location, ignore-tag is added in the level change location of pulse signal.For example, in pulse letter
In number from high level between low level first position addition ignore-tag and from low level to high level it
Between the second place addition ignore-tag.If if only having from high level to low level it in pulse signal
Between first position, then only high level between low level position add ignore-tag., whereas if
Only have from low level to the second place between high level, then only in low level to the position between high level
Addition ignore-tag, depending on it can be according to actual conditions.The ignore-tag of addition is " X ", and it can be with
Device being tested automatic cancellation when signal compares is compared operation.
Mark module 422 is used to add the ignore-tag in the level change location of pulse test signal.Example
Such as, in pulse signal from high level to the first position addition ignore-tag between low level and from low level
Ignore-tag is added to the second place between high level.If if only had from high level in pulse signal
To the first position between low level, then only ignore-tag is added in high level to the position between low level.
, whereas if only have from low level to the second place between high level, then only in low level to high level
Between position addition ignore-tag.Therefore, the position of addition ignore-tag can believe according to actual pulse
Number waveform situation depending on.The ignore-tag of addition is " X ", and it can automatically cancel ratio with device being tested
Relatively operate.
Test device 5 includes signal input module 51, signal reading module 52 and signal comparison module 53.
Signal input module 51 is used to receive pulse process signal and actual measurement pulse signal.Signal reading module 52
Add the level change location of ignore-tag in pulse process signal for reading, and will read result send to
Signal comparison module 53, compares the 3rd position in pulse process signal in addition to level change location and reality
Whether the logic level for surveying the 4th position corresponding with the 3rd position in pulse signal is consistent.Wherein, level
The 3rd position outside change location is high level and low level position in pulse process signal.Exist in theory
When chip is output as normal, the waveform of pulse process signal is substantially identical to the actual measurement pulse signal of chip output
Waveform.Judge whether chip occurs with the comparative result of actual measurement pulse signal according to pulse process signal
Failure.For example, when pulse process signal is consistent with the logic level of actual measurement pulse signal, representing that chip is defeated
The result for going out is correct, that is, chip is normal.Conversely, when pulse process signal and the logic of actual measurement pulse signal
When level is inconsistent, the result mistake of chip output, that is, chip failure are represented.Signal comparison module
53 in the ignore-tag of level change location in detecting pulse process signal, can be according to test device 5
Itself ignore the characteristic of X-shaped ignore-tag, cancel the pulse process signal at ignore-tag and institute
The logic level for stating actual measurement pulse signal compares operation.
The present invention adds ignore-tag by the level change location in pulse test signal, can make test
The pulse signal that device cancels addition ignore-tag position compares, and prevents due to level at level change location
Whether uncertainty, influence the comparative result of signal and cause chip to break down and judge inaccurate.The present invention by
Compare in the signal not entered at line level change location, improve the accuracy of chip testing result.
More than it is particularly shown and described the illustrative embodiments of the disclosure.It should be appreciated that this hair
It is bright to be not limited to detailed construction described herein, set-up mode or implementation method；On the contrary, it is intended to cover
Comprising various modifications in the spirit and scope of the appended claims and equivalence setting.
Claims (17)
1. a kind of signal processing apparatus, it is characterised in that including：
Signal input module, for receiving a pulse signal；
Signal processing module, for confirming level change location in the pulse signal, and in pulse letter
Number level change location add an ignore-tag；And
Signal output module, for exporting the pulse signal after the signal processing module treatment.
2. signal processing apparatus as claimed in claim 1, it is characterised in that the pulse signal is core
The pulse test signal used during built-in testing.
3. signal processing apparatus as claimed in claim 1, it is characterised in that the signal processing module
Including：
Module is confirmed, for confirming level change location in the pulse signal；And
Mark module, the ignore-tag is added for the level change location in the pulse signal.
4. signal processing apparatus described in claim 3, it is characterised in that the level change location is
From high level to low level position and from low level to the position of high level in the pulse signal.
5. signal processing apparatus as claimed in claim 4, it is characterised in that the confirmation module is used for
From high level to low level first position and from low level to high level is confirmed in the pulse signal
Two positions.
6. a kind of signal processing method, it is characterised in that comprise the following steps：
Receive a pulse signal；
Confirm level change location in the pulse signal, and level change location in the pulse signal adds
Plus an ignore-tag；And
The output pulse signal after treatment.
7. signal processing method as claimed in claim 6, it is characterised in that the pulse signal is core
The pulse test signal used during built-in testing.
8. signal processing method as claimed in claim 6, it is characterised in that the level change location
For in the pulse signal from high level to low level first position and from low level to the second of high level
Position.
9. signal processing method as claimed in claim 8, it is characterised in that confirm the pulse signal
Middle level change location, and wrapped the step of the level change location of the pulse signal adds an ignore-tag
Include：
Confirm first position described in the pulse signal and/or the second place, and at described first
Put and/or the second place adds the ignore-tag.
10. a kind of signal offset detection system, for the signal testing of chip, it is characterised in that including：
One signal processing apparatus, for receiving pulse test signal, and in the level of the pulse test signal
Change location adds an ignore-tag, and exports a pulse process signal；And
One test device, the actual measurement pulse letter for receiving the pulse process signal and chip output
Number, and the logic level of the correspondence position relatively in the pulse process signal and the actual measurement pulse signal is
It is no consistent；
Wherein, in the test device pulse process signal in addition to the level change location
3rd position is electric with the logic of the 4th position corresponding with the 3rd position in the actual measurement pulse signal
It is flat whether consistent.
11. signal offset detection systems as claimed in claim 10, it is characterised in that the level becomes
Change position be the pulse signal in from high level to low level first position and from low level to high level
The second place.
12. signal offset detection systems as claimed in claim 10, it is characterised in that when the test
When the device pulse process signal is consistent with the logic level of the actual measurement pulse signal, chip is represented
The result of output is correct；When the test device pulse process signal and the actual measurement pulse signal
Logic level it is inconsistent when, represent chip output result mistake.
13. signal offset detection systems as claimed in claim 10, it is characterised in that at the signal
Reason device includes：
Signal input module, for receiving the pulse test signal；
Signal processing module, for confirming level change location in the pulse test signal, and in the arteries and veins
The level change location for rushing test signal adds the ignore-tag；And
Signal output module, the pulse process signal after being processed for output.
14. signal processing apparatus as claimed in claim 13, it is characterised in that the signal transacting mould
Block includes：
Module is confirmed, for confirming level change location in the pulse test signal；
Mark module, the ignore-tag is added for the level change location in the pulse test signal.
15. signal offset detection systems as claimed in claim 10, it is characterised in that the test dress
Put including：
Signal input module, for receiving the pulse process signal and the actual measurement pulse signal；
Signal reading module, the level for adding the ignore-tag in the pulse process signal for reading becomes
Change position；And
Signal comparison module, for receiving the result after being read through the signal reading module, and detects described
The ignore-tag of level change location described in pulse process signal, and relatively more described pulse treatment letter
Whether the 3rd position in number is consistent with the logic level of the 4th position in the actual measurement pulse signal.
16. signal offset detection systems as claimed in claim 15, it is characterised in that the signal ratio
Compared with module in the ignore-tag in detecting the pulse process signal, cancel at the ignore-tag
The pulse process signal with it is described actual measurement pulse signal logic level compare operation.
A kind of 17. signal bias detecting methods, for the signal testing of chip, comprise the following steps：
Confirm level change location in pulse test signal, mark is ignored in level change location addition one
Note, and export pulse process signal；
The 3rd position compared in the pulse process signal in addition to the level change location is defeated with chip
Whether the logic level of fourth position corresponding with the 3rd position is consistent in the actual measurement pulse signal for going out；
Wherein,
When the pulse process signal is consistent with the logic level of the actual measurement pulse signal, represent that chip is defeated
The result for going out is correct；
When the pulse process signal is inconsistent with the logic level of the actual measurement pulse signal, chip is represented
The result mistake of output.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113358930A (en) * | 2021-08-09 | 2021-09-07 | 南京派格测控科技有限公司 | Harmonic wave test system, device and method based on signal deviation |
| CN116155667A (en) * | 2023-04-19 | 2023-05-23 | 深圳华龙讯达信息技术股份有限公司 | Anti-interference signal transmission processing system |
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