CN103873017B - A kind of device and method improving porch temporal resolution - Google Patents
A kind of device and method improving porch temporal resolution Download PDFInfo
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- CN103873017B CN103873017B CN201210529760.2A CN201210529760A CN103873017B CN 103873017 B CN103873017 B CN 103873017B CN 201210529760 A CN201210529760 A CN 201210529760A CN 103873017 B CN103873017 B CN 103873017B
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Abstract
The present invention relates to a kind of device and method improving porch temporal resolution, which includes：For carrying out the pulse parameter processing unit and pulse generation unit that processing obtains frequency control word, time threshold, ascent stage range coefficient and decline stage range coefficient to pulse parameter.Pulse generation unit includes：Pulse period accumulation module is for generating phase code；Comparison module is used to be compared to phase code and time threshold to generate pulse mark；Rising edge multiplier module is for phase code to be multiplied with ascent stage range coefficient；Failing edge subtraction block is for subtracting each other decline stage time threshold and phase code；Failing edge multiplier module is for the result that failing edge subtraction block exports to be multiplied with decline stage range coefficient；Selecting module is used to judge to export result, the result that failing edge multiplier module generates, the Amplitude maxima of pulse signal or the impulse amplitude minimum value that rising edge multiplier module generates in a period to generate pulse signal according to pulse mark.
Description
Technical field
The present invention relates to pulse technique field, more particularly to a kind of device improving porch temporal resolution and side
Method.
Background technology
Pulse signal generator is a kind of signal generator, and it is adjustable pulse to generate frequency, pulse width and amplitude
Signal.The type of pulse signal generator is various, different properties, be widely used in impulse circuit, digital circuit dynamic characteristic
Test.
With being quickly punched in the transient response of oscillograph, the switching characteristic etc. of time domain reflection technology, component along the pulse
Extensive use, people are not concerned only with the characteristics such as the frequency, amplitude, width of pulse signal, when increasingly paying attention to porch yet
Between characteristic.The porch time includes rising edge of a pulse time and pulse falling edge time, and rising edge of a pulse timing definition is
Impulse amplitude rose to for 90% threshold value duration from 10% threshold value, the pulse falling edge time be then defined as impulse amplitude from
90% threshold value dropped to for 10% threshold value duration.
In the prior art, there are two ways to controlling the porch time, the first is to be based on DDS technologies (direct frequency
Synthesis) wave table mode, be for second using analog devices such as capacitance, diodes.
Many low and middle-ends, the signal generator based on DDS technologies generated by the way of wave table including pulse
Random waveform, basic principle are：The pulse sampling point of a cycle is stored in wave memorizer by processor, then with jump point
Mode take out pulse sampling point from wave memorizer and export.
In this case the defect having：On the one hand, porch the limited time is divided in the storage depth of wave memorizer
Resolution is poor.Citing is got on very well, the storage depth of wave memorizer is 1000 points, pulse frequency 10KHz, then the porch time
Minimum value, i.e. resolution ratio are 0.1uS.So poor resolution ratio obviously can not be applied to high speed test and measure.Increase Waveform storage
The storage depth of device can improve the resolution ratio of porch time, but cost is higher, and effect is limited；On the other hand, work as arteries and veins
Rush frequency it is relatively low when, since the sampling point of porch part is very little, pulse signal is caused to have larger dither cycle；In addition, such as
Fruit will change edge time, then need processor to regenerate the pulse sampling point of a cycle and be written in wave memorizer,
This can consume many processor resources, and system response time is long, and agile is poor.
With the development of technology, there is a kind of regulation device of porch time.Its basic principle is to utilize capacitance
The upper and lower edge time of impulse waveform is arbitrarily arranged in charge and discharge and switch unit realization respectively.When capacitance charge and discharge
There is following relational expression：CU=∫ Idt, approximately derive porch time and impulse amplitude, charge and discharge from this formula
Relational expression between electric current and capacitance is：T≈2CU/I.Therefore, change current source and the size of capacitance can be adjusted porch
Time.
As shown in Figure 1, the structure diagram of the porch regulation device for the prior art.Impulse waveform input unit 101,
The fast along pulse waveform signal of shaping circuit generation is generated for receiving impulse waveform；Rising edge current source 102, it is pre- for exporting
If the charging current of value；Failing edge current source 103, the discharge current for exporting preset value；Switch unit 104 is used for basis
It charges soon to capacitor charge and discharge unit 105 along pulse waveform signal control rising edge current source 102, or control failing edge current source
103 pairs of capacitor charge and discharge units 105 discharge；Capacitor charge and discharge unit 105, it is fast for being adjusted according to charging current and discharge current
Along the porch time of pulse waveform signal；Waveform output unit 106, for export the porch time adjustment after pulse
Waveform signal.
In this case the defect having：In order to regulate and control the upper and lower edge time of high-speed pulse, due to four radio frequencies two
Pole pipe forms the switch unit 104 of high speed, although the speed of rf diode is fast, working frequency is high, thermal stability is poor.
In order to arbitrarily control the porch time, Fig. 1 prior arts have 2 kinds of methods：(a) capacitor charge and discharge unit 105 is adopted
With multistage capacitance network, for different edge times, need the capacitance for switching different scale values, control get up it is complex, and
It is only used for the extensive control of edge time；(b) a kind of common modification rising edge current source 102, failing edge current source 103
The way of output current is to control the output current of current source by changing reference voltage, and reference voltage is led to by controller
Digital analog converter is crossed to adjust.Therefore, it is to compare using the regulation device control porch time of Fig. 1 analog devices composition
Complicated, cost is higher, and flexibility is poor.
Invention content
Regarding the issue above, the present invention provides a kind of device improving porch temporal resolution and side
The resolution ratio of porch time can be improved in method, reduces the shake of pulse signal.
To achieve the above object, the present invention provides a kind of device improving porch temporal resolution, the device packets
It includes：
Pulse parameter processing unit obtains frequency control word, ascent stage time threshold for carrying out processing to pulse parameter
Value, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient；
Pulse generation unit, the information for being obtained according to the pulse parameter processing unit generate pulse signal.
Optionally, in an embodiment of the present invention, the pulse generation unit includes pulse period accumulation module, rising edge
Multiplier module, failing edge subtraction block, failing edge multiplier module, comparison module and selecting module；
The pulse period accumulation module, for the clock pulses T in the pulse generation unitSCumulative one when rising edge
Secondary frequencies control word generates phase code；
The comparison module, for by the phase code respectively with the ascent stage time threshold, high level phases-time
Threshold value, decline stage time threshold are compared to generate pulse mark；
The rising edge multiplier module, for the phase code to be multiplied with the ascent stage range coefficient, and by result
It is transmitted to the selecting module；
The failing edge subtraction block, for subtracting each other the decline stage time threshold and the phase code, and by result
It is transmitted to the failing edge multiplier module；
The failing edge multiplier module, the result of the failing edge subtraction block output for that will obtain and the decline
Stage range coefficient is multiplied, and transmits the result to the selecting module；
The selecting module, the pulse mark for being generated according to the comparison module, which judges to export in a period, to be risen
The Amplitude maxima or impulse amplitude of the result, the result that failing edge multiplier module generates, pulse signal that are generated along multiplier module
Minimum value, to generate pulse signal.
Optionally, in an embodiment of the present invention, the pulse signal includes ascent stage, high level stage, lower depression of order
Section and low level stage.
Optionally, in an embodiment of the present invention, the pulse parameter includes pulse period, rising time, positive pulsewidth
Time, failing edge time, negative pulse width time；Wherein, the positive pulse width time is the amplitude of pulse signal from ascent stage
50% threshold value to the decline stage 50% threshold value duration；The negative pulse width time is the amplitude of pulse signal from decline
50% threshold value in stage to ascent stage 50% threshold value duration.
Optionally, in an embodiment of the present invention, the pulse parameter processing unit includes FREQUENCY CONTROL word modules, time
Threshold module and range coefficient module；
The FREQUENCY CONTROL word modules, for obtaining frequency control word according to the pulse period；
The time threshold module, for obtaining ascent stage time threshold according to rising time and pulse period；Root
High level phases-time threshold value and decline stage are obtained according to positive pulse width time, failing edge time, rising time and pulse period
Time threshold；
The range coefficient module, for being obtained according to the Amplitude maxima and the ascent stage time threshold of pulse signal
Take ascent stage range coefficient；According to the Amplitude maxima of pulse signal, the ascent stage time threshold and high level stage
Time threshold obtains decline stage range coefficient.
Optionally, in an embodiment of the present invention, the FREQUENCY CONTROL word modules obtain frequency control word according to the following formula；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is given birth to for the pulse
At the clock cycle of unit；T is the pulse period.
Optionally, in an embodiment of the present invention, the time threshold module obtains ascent stage time threshold according to the following formula
Value；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are arteries and veins
Rush the period.
Optionally, in an embodiment of the present invention, the time threshold module obtains high level phases-time according to the following formula
Threshold value；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising edge
Time, KI are the maximum value of phase code, are 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, the time threshold module obtains time decline stage threshold according to the following formula
Value；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, when tr is rising edge
Between, KI is the maximum value of phase code, is 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, the range coefficient module obtains ascent stage amplitude system according to the following formula
Number；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold
Value.
Optionally, in an embodiment of the present invention, the range coefficient module obtains decline stage amplitude system according to the following formula
Number；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold
Value, KfFor decline stage time threshold.
Optionally, in an embodiment of the present invention, the ascent stage range coefficient ArData bit width be X+Y,
In, high X is ascent stage range coefficient ArInteger part, low Y be ascent stage range coefficient ArFractional part.
Optionally, in an embodiment of the present invention, the decline stage range coefficient AfData bit width be X+Y,
In, high X is decline stage range coefficient AfInteger part, low Y be decline stage range coefficient AfFractional part.
To achieve the above object, the present invention also provides a kind of method improving porch temporal resolution, this method
Including：
To pulse parameter carry out processing obtain frequency control word, ascent stage time threshold, high level phases-time threshold value,
Decline stage time threshold, ascent stage range coefficient and decline stage range coefficient；
According to the frequency control word, ascent stage time threshold, high level phases-time threshold value, time decline stage threshold
Value, ascent stage range coefficient and decline stage range coefficient generate pulse signal.
Optionally, in an embodiment of the present invention, described according to the frequency control word, ascent stage time threshold, height
Level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient generate pulse
The step of signal includes：
In clock pulses TSFrequency control word is accumulated once when rising edge to generate phase code；
By the phase code respectively with the ascent stage time threshold, high level phases-time threshold value, time decline stage
Threshold value is compared to generate pulse mark；
The phase code is multiplied with the ascent stage range coefficient and obtains the pulse envelope of ascent stage；
The decline stage time threshold and the phase code are subtracted each other；
Difference between decline stage time threshold and the phase code is multiplied acquisition with the decline stage range coefficient
The pulse envelope of decline stage；
Pulse envelope, the pulse packet of decline stage of output ascent stage in a period are judged according to the pulse mark
Network, the Amplitude maxima of pulse signal or impulse amplitude minimum value generate pulse signal.
Optionally, in an embodiment of the present invention, the pulse signal includes ascent stage, high level stage, lower depression of order
Section and low level stage.
Optionally, in an embodiment of the present invention, the pulse parameter includes pulse period, rising time, positive pulsewidth
Time, failing edge time, negative pulse width time；Wherein, the positive pulse width time is the amplitude of pulse signal from ascent stage
50% threshold value to the decline stage 50% threshold value duration；The negative pulse width time is the amplitude of pulse signal from decline
50% threshold value in stage to ascent stage 50% threshold value duration.
Optionally, in an embodiment of the present invention, described that processing acquisition frequency control word, raised bench are carried out to pulse parameter
Section time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage amplitude
The step of coefficient includes：
Frequency control word is obtained according to the pulse period；
Ascent stage time threshold is obtained according to rising time and pulse period；When according to positive pulse width time, failing edge
Between, rising time and pulse period obtain high level phases-time threshold value and decline stage time threshold；
Ascent stage range coefficient is obtained according to the Amplitude maxima of pulse signal and the ascent stage time threshold；Root
Decline stage width is obtained according to the Amplitude maxima of pulse signal, the ascent stage time threshold and high level phases-time threshold value
Spend coefficient.
Optionally, in an embodiment of the present invention, described the step of obtaining frequency control word according to the pulse period, includes：
Frequency control word is obtained according to the following formula；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is given birth to for the pulse
At the clock cycle of unit；T is the pulse period.
Optionally, in an embodiment of the present invention, described when obtaining ascent stage according to rising time and pulse period
Between threshold value the step of include：
Ascent stage time threshold is obtained according to the following formula；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are arteries and veins
Rush the period.
Optionally, in an embodiment of the present invention, the positive pulse width time of the basis, the failing edge time, rising time and
Pulse period obtains high level phases-time threshold value and the step of decline stage time threshold includes：
High level phases-time threshold value is obtained according to the following formula；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising edge
Time, KI are the maximum value of phase code, are 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, the positive pulse width time of the basis, the failing edge time, rising time and
Pulse period obtains high level phases-time threshold value and the step of decline stage time threshold includes：
Decline stage time threshold is obtained according to the following formula；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, when tr is rising edge
Between, KI is the maximum value of phase code, is 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, the Amplitude maxima according to pulse signal and the ascent stage
Time threshold obtain ascent stage range coefficient the step of include：
Ascent stage range coefficient is obtained according to the following formula；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold
Value.
Optionally, in an embodiment of the present invention, when Amplitude maxima, the ascent stage according to pulse signal
Between threshold value and high level phases-time threshold value the step of obtaining decline stage range coefficient include：
Decline stage range coefficient is obtained according to the following formula；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold
Value, KfFor decline stage time threshold.
Optionally, in an embodiment of the present invention, the ascent stage range coefficient ArData bit width be X+Y,
In, high X is ascent stage range coefficient ArInteger part, low Y be ascent stage range coefficient ArFractional part.
Optionally, in an embodiment of the present invention, the decline stage range coefficient AfData bit width be X+Y,
In, high X is decline stage range coefficient AfInteger part, low Y be decline stage range coefficient AfFractional part.
Above-mentioned technical proposal has the advantages that：Base of the technical solution provided by the invention based on processor+FPGA
This framework, is not necessarily to wave memorizer, porch control circuit that also should not be special, thus it is simple in structure, realize and be easy, be integrated
Degree is high, cost is relatively low, and the parameter of pulse signal can flexibly be set, including the rising edge of a pulse time, the pulse falling edge time,
Pulsewidth is born in pulse period, the positive pulsewidth of pulse, pulse.And system response time is fast, agile is good.In addition, the technical solution has
The resolution ratio of higher porch time, and there is no the dither cycles of low frequency pulse signal.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is the structure diagram of the porch regulation device of the prior art；
Fig. 2 is a kind of apparatus structure schematic diagram improving porch temporal resolution proposed by the present invention；
Fig. 3 is the pulse generation unit structural schematic diagram in the device for improve porch temporal resolution；
Fig. 4 is the pulse parameter processing unit structural schematic diagram in the device for improve porch temporal resolution；
Fig. 5 is a kind of method flow diagram improving porch temporal resolution proposed by the present invention；
Fig. 6 is the structural schematic diagram of pulse generation unit in embodiment；
Fig. 7 is the structural schematic diagram for the device that porch temporal resolution is improved in embodiment；
Fig. 8 is the flow chart for the method that porch temporal resolution is improved in embodiment；
Fig. 9 is the schematic diagram that processor obtains time threshold and range coefficient by waveform parameter in embodiment.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
From the time, the pulse signal of a cycle can be divided into four-stage：
(1) ascent stage, pulse envelope are to rise；
(2) high level stage, pulse envelope maintain high level；
(3) decline stage, pulse envelope are to decline；
(4) low level stage, pulse envelope maintain low level.
As shown in Fig. 2, for a kind of apparatus structure schematic diagram improving porch temporal resolution proposed by the present invention.It should
Device includes：Pulse parameter processing unit 201 and pulse generation unit 202.Wherein, pulse parameter processing unit 201 for pair
When pulse parameter carries out processing acquisition frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage
Between threshold value, ascent stage range coefficient and decline stage range coefficient；Pulse generation unit 202 is used for according to the pulse parameter
The information that processing unit obtains generates pulse signal.
As shown in figure 3, for the pulse generation unit structural schematic diagram in the device of raising porch temporal resolution.Institute
It includes pulse period accumulation module 2021, rising edge multiplier module 2022, failing edge subtraction block to state pulse generation unit 202
2023, failing edge multiplier module 2024, comparison module 2025 and selecting module 2026；Wherein, the pulse period accumulation module
2021 for the clock pulses T in the pulse generation unitSFrequency control word is accumulated once when rising edge to generate phase code；Institute
State comparison module 2025 for by the phase code respectively with the ascent stage time threshold, high level phases-time threshold value, under
Depression of order section time threshold is compared to generate pulse mark；The rising edge multiplier module 2022 is used for the phase code and institute
The multiplication of ascent stage range coefficient is stated, and transmits the result to the selecting module；The failing edge subtraction block 2023 is used for
The decline stage time threshold and the phase code are subtracted each other, and transmit the result to the failing edge multiplier module；Under described
Result and the decline stage amplitude system of the failing edge subtraction block output for being used to obtain along multiplier module 2024 drop
Number is multiplied, and transmits the result to the selecting module；What the selecting module 2026 was used to be generated according to the comparison module
Pulse mark judge the result that the result that output rising edge multiplier module generates in a period, failing edge multiplier module generate,
The Amplitude maxima or impulse amplitude minimum value of pulse signal, to generate pulse signal.
Optionally, the pulse signal includes ascent stage, high level stage, decline stage and low level stage.
Preferably, the pulse parameter includes pulse period, rising time, positive pulse width time, failing edge time, negative arteries and veins
The wide time；Wherein, the positive pulse width time is the amplitude of pulse signal from 50% threshold value of ascent stage to the decline stage
50% threshold value duration；The negative pulse width time is the amplitude of pulse signal from 50% threshold value of decline stage to rising
The 50% threshold value duration in stage.
As shown in figure 4, for the pulse parameter processing unit structural representation in the device of raising porch temporal resolution
Figure.The pulse parameter processing unit 201 includes FREQUENCY CONTROL word modules 2011, time threshold module 2012 and range coefficient mould
Block 2013；Wherein, the FREQUENCY CONTROL word modules 2011 are used to obtain frequency control word according to the pulse period；The time threshold
Module 2012 is used to obtain ascent stage time threshold according to rising time and pulse period；According to positive pulse width time, decline
High level phases-time threshold value and decline stage time threshold are obtained along time, rising time and pulse period；The amplitude
Coefficient module 2013 is used to obtain ascent stage width according to the Amplitude maxima of pulse signal and the ascent stage time threshold
Spend coefficient；It is obtained according to the Amplitude maxima of pulse signal, the ascent stage time threshold and high level phases-time threshold value
Decline stage range coefficient.
Optionally, in an embodiment of the present invention, the FREQUENCY CONTROL word modules 2011 obtain FREQUENCY CONTROL according to the following formula
Word；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is given birth to for the pulse
At the clock cycle of unit；T is the pulse period.
The time threshold module 2012 obtains ascent stage time threshold according to the following formula；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are arteries and veins
Rush the period.
Optionally, in an embodiment of the present invention, the time threshold module 2012 obtains the high level stage according to the following formula
Time threshold；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising edge
Time, KI are the maximum value of phase code, are 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, when the time threshold module 2012 obtains the decline stage according to the following formula
Between threshold value；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, when tr is rising edge
Between, KI is the maximum value of phase code, is 2N- 1, T are the pulse period.
Optionally, in an embodiment of the present invention, the range coefficient module 2013 obtains ascent stage width according to the following formula
Spend coefficient；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold
Value.
Optionally, in an embodiment of the present invention, the range coefficient module 2013 obtains decline stage width according to the following formula
Spend coefficient；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold
Value, KfFor decline stage time threshold.
It is highly preferred that the ascent stage range coefficient ArData bit width be X+Y, wherein high X be ascent stage
Range coefficient ArInteger part, low Y be ascent stage range coefficient ArFractional part.
It is highly preferred that the decline stage range coefficient AfData bit width be X+Y, wherein high X be the decline stage
Range coefficient AfInteger part, low Y be decline stage range coefficient AfFractional part.
As shown in figure 5, for a kind of method flow diagram improving porch temporal resolution proposed by the present invention.This method
Including：
Step 501)：Processing is carried out to pulse parameter and obtains frequency control word, ascent stage time threshold, high level stage
Time threshold, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient；
Step 502)：According to the frequency control word, ascent stage time threshold, high level phases-time threshold value, decline
Phases-time threshold value, ascent stage range coefficient and decline stage range coefficient generate pulse signal.
Wherein, step 501) specifically includes：
Step 5011)：In clock pulses TSFrequency control word is accumulated once when rising edge to generate phase code；
Step 5012)：By the phase code respectively with the ascent stage time threshold, high level phases-time threshold value, under
Depression of order section time threshold is compared to generate pulse mark；
Step 5013)：The phase code is multiplied with the ascent stage range coefficient and obtains the pulse envelope of ascent stage；
Step 5014)：The decline stage time threshold and the phase code are subtracted each other；
Step 5015)：By difference and the decline stage amplitude system between decline stage time threshold and the phase code
Number, which is multiplied, obtains the pulse envelope of decline stage；
Step 5016)：Pulse envelope, the lower depression of order of output ascent stage in a period are judged according to the pulse mark
The pulse envelope of section, the Amplitude maxima of pulse signal or impulse amplitude minimum value generate pulse signal.
Wherein, step 502) specifically includes：
Step 5021)：Frequency control word is obtained according to the pulse period；
Wherein, frequency control word is obtained according to the following formula；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is given birth to for the pulse
At the clock cycle of unit；T is the pulse period.
High level phases-time threshold value is obtained according to the following formula；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising edge
Time, KI are the maximum value of phase code, are 2N- 1, T are the pulse period.
Decline stage time threshold is obtained according to the following formula；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, when tr is rising edge
Between, KI is the maximum value of phase code, is 2N- 1, T are the pulse period.
Step 5022)：Ascent stage time threshold is obtained according to rising time and pulse period；When according to positive pulsewidth
Between, failing edge time, rising time and pulse period obtain high level phases-time threshold value and decline stage time threshold；
Ascent stage time threshold is obtained according to the following formula；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are arteries and veins
Rush the period.
Step 5023)：Ascent stage is obtained according to the Amplitude maxima of pulse signal and the ascent stage time threshold
Range coefficient；It is obtained according to the Amplitude maxima of pulse signal, the ascent stage time threshold and high level phases-time threshold value
Take decline stage range coefficient.
Ascent stage range coefficient is obtained according to the following formula；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold
Value.
Decline stage range coefficient is obtained according to the following formula；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold
Value, KfFor decline stage time threshold.
Embodiment 1:
The present embodiment is periodically counted using pulse period accumulation device, and count results and processor are arranged comparator
Ascent stage time threshold Kr, high level phases-time threshold kh, decline stage time threshold KfIt is compared, by count results
It is divided into the aforementioned four stage：The pulse envelope that ascent stage is generated with rising edge multiplier, with failing edge subtracter and failing edge
Multiplier generates the pulse envelope of decline stage, and the comparison result selection four-stage exported according to comparator with selector corresponds to
Output generate pulse signal.
The present embodiment generates pulse signal using FPGA as pulse generation unit, as shown in fig. 6, for pulse in embodiment
The structural schematic diagram of generation unit.Including：Processor interface 1, pulse period accumulation device 3, comparator 4, rises clock module 2
Along multiplier 5, failing edge subtracter 6, failing edge multiplier 7, selector 8.
(1) processor interface 1：It is pulse generation unit and the communication interface of processor, the instruction that dissection process device issues,
It is then forwarded to other internal modules；
(2) clock module 2 provide clock, period T for other modulesS；
(3) pulse period accumulation device 3, generates and periodically counts output, and count results are known as phase code.In each clock
Pulse TSWhen rising edge arrives, frequency control word K is just accumulated once0Generate phase code.Pulse period accumulation device and K are indicated with N0's
Bit wide, then the data bit width of phase code is also N, and the range of phase code value is 0~2N-1.Frequency control word K0Be arranged by processor, it with
The relationship of pulse period T such as formula 1, processor calculate frequency control word K according to formula 10。
K0=2N*TS/T (1)
(4) three times that the bit wide of comparator 4, the phase code that pulse period accumulation device 3 is generated and processor setting is N
Threshold value：Ascent stage time threshold Kr, high level phases-time threshold kh, decline stage time threshold KfIt is respectively compared, generates 2
The pulse flag bit of bit bit wide.
As phase code≤Kr, pulse flag bit be equal to " 00 ", indicate pulse be in ascent stage；
Work as Kr<Phase code≤Kh, pulse flag bit be equal to " 01 ", indicate pulse be in the high level stage；
Work as Kh<Phase code≤Kf, pulse flag bit be equal to " 10 ", indicate pulse be in the decline stage；
When phase code>Kf, pulse flag bit be equal to " 11 ", indicate pulse be in the low level stage.
(5) rising edge multiplier 5, the ascent stage width of the phase code that pulse period accumulation device 3 is generated and processor setting
Spend coefficient ArIt is multiplied, because phase code is incremental, therefore product is also incremental, and product is by the pulse envelope as ascent stage
Give selector.
Indicate that the Amplitude maxima of pulse signal, processor calculate A according to formula 2 with Ar：
Ar=A/Kr (2)
Particularly, in order to ensure the resolution ratio of rising edge of a pulse time, ArData bit width be X+Y, wherein high X table
The A shownrInteger part, it is low Y expression ArFractional part.
(6) failing edge subtracter 6, with decline stage time threshold KfThe phase code generated with pulse period accumulation device 3 subtracts each other,
Difference gives failing edge multiplier；
(7) failing edge multiplier 7, the decline stage amplitude of the difference that failing edge subtracter 6 is generated and processor setting
Coefficient AfIt is multiplied, because difference is successively decreased, therefore product is also to successively decrease, and product will be sent as the pulse envelope of decline stage
To selector.
Processor calculates A according to formula 3f：
Af=A/ (Kf–Kh) (3)
Particularly, in order to ensure the resolution ratio of pulse falling edge time, AfData bit width be X+Y, wherein high X table
The A shownfInteger part, it is low Y expression AfFractional part.
Therefore, the pulse envelope of ascent stage, the pulse envelope of decline stage generate respectively, therefore rising edge of a pulse
Time, failing edge time can be respectively set.
(8) selector 8 generate the output of pulse signal according to the pulse flag bit of comparator 4.
When pulse flag bit is equal to " 00 ", the product of selection rising edge multiplier 5, the pulse envelope as ascent stage；
When pulse flag bit is equal to " 01 ", strobe pulse amplitude A, the pulse envelope as the high level stage；
When pulse flag bit is equal to " 10 ", the product of selection failing edge multiplier 7, the pulse envelope as the decline stage；
When pulse flag bit is equal to " 11 ", strobe pulse amplitude 0, the pulse envelope as the low level stage.
Pulse signal production method provided by the present invention and the control method of porch time, mainly in FPGA
Portion realizes, is different from the pulse circuit for regulating and controlling of analog device realization, also has very big difference with the wave table mode based on DDS technologies.
Since time threshold and range coefficient can be arranged by processor, the parameter of the pulse signal of final output is can spirit
Setting living.Different in the depth of wave memorizer from the resolution limitations of porch time in wave table mode, the present invention does not have
Have and use wave memorizer, but has used data bit width larger and integer part and fractional part each may participate in the upper of calculating
It rises along multiplier and failing edge multiplier, effectively increases the resolution ratio of porch time；And pulse rising period, lower depression of order
The number of samples of section is not influenced by low-frequency pulse, and low-frequency jitter problem is not present.
As shown in fig. 7, the structural schematic diagram of the device to improve porch temporal resolution in embodiment.Including：
(1) GUI element 701 receive user's control by GUI (graphical user interface) unit, and arteries and veins is arranged by GUI in user
The parameter (including porch time, pulse period, impulse amplitude etc.) of signal is rushed, these parameters are passed to processing by GUI
Device；
(2) processor 302 receive the parameter input of GUI, obtain time threshold and range coefficient by calculating, and pass through
Communication bus occurs to FPGA703.
(3) FPGA703 is served as by FPGA, and digitized pulse signal is generated according to the parameter of processor configuration.
Communication bus protocol between processor and pulse generation unit can very flexibly, and communication bus protocol can be
Standard, can also be customized.As previously mentioned, what the meeting dissection process device of processor interface 1 inside FPGA 703 issued
Instruction is then forwarded to other internal modules.
The pulse signal that FPGA 703 is exported is digital form, and bit wide is equal to next stage DAC's (digital analog converter)
Data bit width.
(4) DAC (digital analog converter) 704：The pulse signal of the digital forms exported of FPGA 703 is converted into simulation shape
Formula；
(5) analog circuit 705：The pulse signal of analog form is further processed, including filtering, the decaying in amplitude,
Amplification etc., final output pulse signal.
As shown in figure 8, the flow chart of the method to improve porch temporal resolution in embodiment.This method includes：
Pulse parameter is arranged by GUI element in S801, user.
S802, processor calculate time threshold and range coefficient according to pulse parameter, and give pulse generation unit.With
Wave table mode in the prior art is compared, and the calculating of the processor in the present invention is fairly simple, without time-consuming longer, complicated
Operation, how many processor resource will not be occupied.If user has modified pulse parameter, processor, which need to only recalculate, again will
As a result occur to give pulse generation unit, therefore system response time is fast.
Pulse period accumulation device inside S803, FPGA generates periodic phase code according to frequency control word under clock.
Because being to generate pulse envelope by phase code, there is no the weeks of the limited caused low-frequency pulse of the storage depth of wave memorizer
Phase jitter problem.
Rising edge multiplier and failing edge subtracter inside S804, FPGA generate respectively ascent stage pulse envelope and
The pulse envelope of decline stage.Because integer and the range coefficient of fractional part can participate in multiplication operation, and multiplier position
Width is larger, therefore the resolution ratio of porch time can be very high.
The pulse that selector inside S805, FPGA generates digital form according to the pulse flag bit that comparator exports is believed
Number.
S806 exports the pulse signal of analog form after DAC and analog circuitry processes.
In above-described embodiment, processor is by the porch time of user setting, positive pulse width time, negative pulse width time, arteries and veins
It is that time threshold and range coefficient are sent to pulse generation unit to rush periodic conversion, is given birth to according to these parameters by pulse generation unit
At the pulse signal of digital form.Wherein the relationship of pulse period and frequency control word are provided by formula 1.Fig. 4 illustrates these
Relationship between parameter.
As shown in figure 9, the schematic diagram of time threshold and range coefficient is obtained by waveform parameter for processor in embodiment.
The first width figure illustrates that the relationship of the amplitude and time of pulse period accumulation device the output phase code, the longitudinal axis are the amplitudes of phase code in Fig. 9,
Horizontal axis is time t；Fig. 9 the second width figures illustrate that the amplitude of pulse signal caused by FPGA and the relationship of time, the longitudinal axis are arteries and veins
The amplitude of signal is rushed, horizontal axis is time t.
It is divided from time t, [0, t0] is pulse rising period, and [t0, t1] is the pulse high level stage, and [t1, t2] is arteries and veins
The decline stage is rushed, [t2, T] is the pulses low stage.
The pulse parameter of user setting is：Pulse period T, rising time tr, positive pulse width time th, failing edge time
Tf, negative pulse width time tL.Wherein, the positive pulse width time of pulse is defined as impulse amplitude from 50% threshold value of ascent stage to decline
The negative pulse width time of the 50% threshold value duration in stage, pulse are defined as 50% threshold value of the impulse amplitude from the decline stage
To 50% threshold value duration of ascent stage.According to Fig. 9, there is following relational expression：
T=th+tL；
Tr=t0/1.25；
Tf=(t2-t1)/1.25；
Th=t0/2+ (t1-t0)+(t2-t1)/2=(t1+t2-t0)/2.
By relation above formula, following relational expression is derived：
T0=1.25*tr；
T1=(2*th-1.25*tf+1.25*tr) * 0.5；
T2=(2*th+1.25*tf+1.25*tr) * 0.5.
The maximum value 2 of phase code is indicated with KIN- 1, it can derive following formula：
Kr=(1.25*tr) * KI/T (4)
Kh=(2*th-1.25*tf+1.25*tr) * 0.5*KI/T (5)
Kf=(2*th+1.25*tf+1.25*tr) * 0.5*KI/T (6)
Processor calculates separately out three time thresholds according to formula 4, formula 5, formula 6 by pulse parameter：Ascent stage
Time threshold Kr, high level phases-time threshold kh, decline stage time threshold Kf；According to formula 2, formula 3 by pulse parameter point
Two range coefficients are not calculated：Ascent stage range coefficient Ar, decline stage range coefficient Af。
Above-described specific implementation mode has carried out further the purpose of the present invention, technical solution and advantageous effect
It is described in detail, it should be understood that the foregoing is merely the specific implementation mode of the present invention, is not intended to limit the present invention
Protection domain, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (24)
1. a kind of device improving porch temporal resolution, which is characterized in that the device includes：
Pulse parameter processing unit obtains frequency control word, ascent stage time threshold, height for carrying out processing to pulse parameter
Level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and decline stage range coefficient；
Pulse generation unit, the information for being obtained according to the pulse parameter processing unit generate pulse signal, including：Pulse
Periodic accumulation module, rising edge multiplier module, failing edge subtraction block, failing edge multiplier module, comparison module and selecting module；
The pulse period accumulation module, for the clock pulses T in the pulse generation unitSFrequency is accumulated once when rising edge
Rate control word generates phase code；
The comparison module, for by the phase code respectively with the ascent stage time threshold, high level phases-time threshold value,
Decline stage time threshold is compared to generate pulse mark；
The rising edge multiplier module for the phase code to be multiplied with the ascent stage range coefficient, and result is transmitted
To the selecting module；
The failing edge subtraction block for subtracting each other the decline stage time threshold and the phase code, and result is transmitted
To the failing edge multiplier module；
The failing edge multiplier module, the result of the failing edge subtraction block output for that will obtain and the decline stage
Range coefficient is multiplied, and transmits the result to the selecting module；
The selecting module, the pulse mark for being generated according to the comparison module judge that rising edge is exported in a period to be multiplied
Result, the result that failing edge multiplier module generates, the Amplitude maxima of pulse signal or the impulse amplitude that method module generates are minimum
Value, to generate pulse signal.
2. the apparatus according to claim 1, which is characterized in that the pulse signal include ascent stage, the high level stage,
Decline stage and low level stage.
3. the apparatus according to claim 1, which is characterized in that the pulse parameter include the pulse period, rising time,
Positive pulse width time, failing edge time, negative pulse width time；Wherein, the positive pulse width time is the amplitude of pulse signal from raised bench
Section 50% threshold value to the decline stage 50% threshold value duration；The negative pulse width time be pulse signal amplitude from
50% threshold value of decline stage to ascent stage 50% threshold value duration.
4. device according to claim 3, which is characterized in that the pulse parameter processing unit includes FREQUENCY CONTROL type matrix
Block, time threshold module and range coefficient module；
The FREQUENCY CONTROL word modules, for obtaining frequency control word according to the pulse period；
The time threshold module, for obtaining ascent stage time threshold according to rising time and pulse period；According to just
Pulse width time, failing edge time, rising time and pulse period obtain high level phases-time threshold value and time decline stage
Threshold value；
The range coefficient module, for being obtained according to the Amplitude maxima of pulse signal and the ascent stage time threshold
Rise stage range coefficient；According to the Amplitude maxima of pulse signal, the ascent stage time threshold and high level phases-time
Threshold value obtains decline stage range coefficient.
5. device according to claim 4, which is characterized in that the FREQUENCY CONTROL word modules obtain frequency control according to the following formula
Word processed；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is generated for the pulse single
The clock cycle of member；T is the pulse period.
6. device according to claim 4, which is characterized in that the time threshold module obtains ascent stage according to the following formula
Time threshold；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are pulse week
Phase, N are the bit wide of pulse period accumulation module.
7. device according to claim 4, which is characterized in that the time threshold module obtains high level rank according to the following formula
Section time threshold；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising time,
KI is the maximum value of phase code, is 2N- 1, T are the pulse period, and N is the bit wide of pulse period accumulation module.
8. device according to claim 4, which is characterized in that the time threshold module obtains the decline stage according to the following formula
Time threshold；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, and tr is rising time, KI
It is 2 for the maximum value of phase codeN- 1, T are the pulse period, and N is the bit wide of pulse period accumulation module.
9. device according to claim 4, which is characterized in that the range coefficient module obtains ascent stage according to the following formula
Range coefficient；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold.
10. device according to claim 4, which is characterized in that the range coefficient module obtains lower depression of order according to the following formula
Section range coefficient；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold value,
KfFor decline stage time threshold.
11. the device according to any one of claim 3~10, which is characterized in that the ascent stage range coefficient Ar's
Data bit width is X+Y, wherein high X is ascent stage range coefficient ArInteger part, low Y be ascent stage amplitude
Coefficient ArFractional part.
12. the device according to any one of claim 3~10, which is characterized in that the decline stage range coefficient Af's
Data bit width is X+Y, wherein high X is decline stage range coefficient AfInteger part, low Y be decline stage amplitude
Coefficient AfFractional part.
13. a kind of method improving porch temporal resolution, which is characterized in that this method includes：
Processing is carried out to pulse parameter and obtains frequency control word, ascent stage time threshold, high level phases-time threshold value, decline
Phases-time threshold value, ascent stage range coefficient and decline stage range coefficient；
According to the frequency control word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold,
Ascent stage range coefficient and decline stage range coefficient generate pulse signal, including：
In clock pulses TSFrequency control word is accumulated once when rising edge to generate phase code；
By the phase code respectively with the ascent stage time threshold, high level phases-time threshold value, decline stage time threshold
It is compared to generate pulse mark；
The phase code is multiplied with the ascent stage range coefficient and obtains the pulse envelope of ascent stage；
The decline stage time threshold and the phase code are subtracted each other；
Difference between decline stage time threshold and the phase code is multiplied with the decline stage range coefficient acquisition decline
The pulse envelope in stage；
According to the pulse mark judge to export in a period pulse envelope of ascent stage, the pulse envelope of decline stage,
The Amplitude maxima of pulse signal or impulse amplitude minimum value generate pulse signal.
14. according to the method for claim 13, which is characterized in that the pulse signal includes ascent stage, high level rank
Section, decline stage and low level stage.
15. according to the method for claim 13, which is characterized in that when the pulse parameter includes pulse period, rising edge
Between, positive pulse width time, the failing edge time, negative pulse width time；Wherein, the positive pulse width time is the amplitude of pulse signal from rising
50% threshold value in stage to the decline stage 50% threshold value duration；The negative pulse width time is the amplitude of pulse signal
From 50% threshold value of decline stage to 50% threshold value duration of ascent stage.
16. according to the method for claim 15, which is characterized in that described to carry out processing acquisition FREQUENCY CONTROL to pulse parameter
Word, ascent stage time threshold, high level phases-time threshold value, decline stage time threshold, ascent stage range coefficient and under
The step of depression of order section range coefficient includes：
Frequency control word is obtained according to the pulse period；
Ascent stage time threshold is obtained according to rising time and pulse period；According to positive pulse width time, the failing edge time, on
It rises and obtains high level phases-time threshold value and decline stage time threshold along time and pulse period；
Ascent stage range coefficient is obtained according to the Amplitude maxima of pulse signal and the ascent stage time threshold；According to arteries and veins
The Amplitude maxima, the ascent stage time threshold and high level phases-time threshold value for rushing signal obtain decline stage amplitude system
Number.
17. according to the method for claim 16, which is characterized in that the step for obtaining frequency control word according to the pulse period
Suddenly include：
Frequency control word is obtained according to the following formula；
K0=2N*Ts/T
Wherein, K0For the frequency control word of pulse signal, N is the bit wide of pulse period accumulation module, TsIt is generated for the pulse single
The clock cycle of member；T is the pulse period.
18. according to the method for claim 16, which is characterized in that described to be obtained according to rising time and pulse period
Rise phases-time threshold value the step of include：
Ascent stage time threshold is obtained according to the following formula；
Kr=(1.25*tr) * KI/T
Wherein, KrFor ascent stage time threshold, tr is rising time, and KI is the maximum value of phase code, is 2N- 1, T are pulse week
Phase, N are the bit wide of pulse period accumulation module.
19. according to the method for claim 16, which is characterized in that the basis positive pulse width time, rises the failing edge time
Include along the step of time and pulse period acquisition high level phases-time threshold value and decline stage time threshold：
High level phases-time threshold value is obtained according to the following formula；
Kh=(2*th-1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KhFor high level phases-time threshold value, th is positive pulse width time, and tf is the failing edge time, and tr is rising time,
KI is the maximum value of phase code, is 2N- 1, T are the pulse period, and N is the bit wide of pulse period accumulation module.
20. according to the method for claim 16, which is characterized in that the basis positive pulse width time, rises the failing edge time
Include along the step of time and pulse period acquisition high level phases-time threshold value and decline stage time threshold：
Decline stage time threshold is obtained according to the following formula；
Kf=(2*th+1.25*tf+1.25tr) * 0.5*KI/T
Wherein, KfFor decline stage time threshold, th is positive pulse width time, and tf is the failing edge time, and tr is rising time, KI
It is 2 for the maximum value of phase codeN- 1, T are the pulse period, and N is the bit wide of pulse period accumulation module.
21. according to the method for claim 16, which is characterized in that the Amplitude maxima according to pulse signal and described
Ascent stage time threshold obtain ascent stage range coefficient the step of include：
Ascent stage range coefficient is obtained according to the following formula；
Ar=A/Kr
Wherein, ArFor ascent stage range coefficient, A is the Amplitude maxima of pulse signal, KrFor ascent stage time threshold.
22. according to the method for claim 16, which is characterized in that the Amplitude maxima according to pulse signal, described
Ascent stage time threshold and high level phases-time threshold value obtain the step of decline stage range coefficient and include：
Decline stage range coefficient is obtained according to the following formula；
Af=A/ (Kf–Kh)
Wherein, AfFor decline stage range coefficient, A is the Amplitude maxima of pulse signal, KhFor high level phases-time threshold value,
KfFor decline stage time threshold.
23. the method according to any one of claim 15~22, which is characterized in that the ascent stage range coefficient Ar
Data bit width be X+Y, wherein high X be ascent stage range coefficient ArInteger part, low Y be ascent stage width
Spend coefficient ArFractional part.
24. the method according to any one of claim 15~22, which is characterized in that the decline stage range coefficient Af
Data bit width be X+Y, wherein high X be decline stage range coefficient AfInteger part, low Y be decline stage width
Spend coefficient AfFractional part.
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