CN203858282U - Intermediate-frequency broadband digital peak detection circuit - Google Patents

Intermediate-frequency broadband digital peak detection circuit Download PDF

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Publication number
CN203858282U
CN203858282U CN201320879495.0U CN201320879495U CN203858282U CN 203858282 U CN203858282 U CN 203858282U CN 201320879495 U CN201320879495 U CN 201320879495U CN 203858282 U CN203858282 U CN 203858282U
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CN
China
Prior art keywords
signal
digital
scanning voltage
detection circuit
port
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Expired - Fee Related
Application number
CN201320879495.0U
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Chinese (zh)
Inventor
唐立军
彭艳云
贺慧勇
张春熹
郑隆浩
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Changsha University of Science and Technology
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Changsha University of Science and Technology
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Priority to CN201320879495.0U priority Critical patent/CN203858282U/en
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Publication of CN203858282U publication Critical patent/CN203858282U/en
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Abstract

The utility model discloses an intermediate-frequency broadband digital peak detection circuit comprising a signal conditioning circuit which enhances an input signal to be within a working range of a high-speed comparator; the high-speed comparator which is used for comparing size of the input signal through the signal conditioning circuit with scanning voltage generated by a DAC; a digital control unit which controls the DAC to generate scanning voltage approaching the input signal peak according to a binary searching successive comparison mode; and the DAC which is used for generating scanning voltage. The anti-phase input end of the high-speed comparator is connected with a signal from the signal conditioning circuit, and the in-phase input end of the high-speed comparator is connected with scanning voltage generated by the DAC. Problems that conventional peak detectors are low in speed, low in detection precision, complex in structure or high in cost in the detection process are solved by the intermediate-frequency broadband digital peak detection circuit so that the intermediate-frequency broadband digital peak detection circuit can be greatly applied to design of intermediate-frequency broadband circuits.

Description

A kind of intermediate frequency wideband digital peak detection circuit
Technical field
The utility model relates to a kind of infotech and the input of communicating by letter, particularly a kind of intermediate frequency wideband digital peak detection circuit.
Background technology
The input in the fields such as peak detection circuit is widely used in infotech and communicates by letter, analog signal processing.At present, peak value detects and is divided into the detection of hardware (simulation) peak value and digital peak detection.Simulated peak detecting device is a special hardware circuit, is mainly made up of sampling hold circuit and voltage comparator circuit.The charge-discharge circuit that the simplest simulated peak testing circuit is made up of diode and electric capacity, with the form storage signal peak value of voltage on electric capacity, its shortcoming is that speed is slower, can use frequency range narrower, the discharge process of electric capacity is larger on the impact of sampling precision.Digital peak value detector is mainly made up of ADC, and ADC will sample to signal continuously with high as far as possible sampling rate, until obtain signal peak, its shortcoming is that signal frequency is higher, and higher to the sample rate requirement of ADC, corresponding cost is also higher.The shortcoming of simulated peak detecting device and digital peak value detector (forming around ADC), is not all suitable in the circuit design in intermediate frequency broadband them.
Therefore, provide a kind of simple in structure, the response time is fast, sensing range is large, precision is high is applied to the digital peak testing circuit of intermediate frequency wideband circuit design, is one of these those skilled in the art problem that need address.
Summary of the invention
Technical problem to be solved in the utility model is, for prior art deficiency, a kind of intermediate frequency wideband digital peak detection circuit is provided, solution peak detctor is in the past in testing process, speed is slower, and accuracy of detection is not high, complex structure, problem that cost is high.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of intermediate frequency wideband digital peak detection circuit, comprise the signal conditioning circuit, comparer, the digital control unit that connect successively, described digital control unit accesses the input end of described comparer by analog-digital chip.
Described digital control unit adopts FPGA; The data-out port of described FPGA, clock signal port, enable signal port are connected with data-in port, clock signal port, the enable signal port of described analog-digital chip respectively; The output pulse signal of described comparer accesses the data-in port of described FPGA.
The inverting input of described comparer is connected with described signal conditioning circuit output port; The input end in the same way of described comparer receives the scanning voltage that described analog-digital chip produces.
Compared with prior art, the beneficial effect that the utility model has is: by comparer, by input signal, the signal after signal conditioning circuit conditioning directly compares with the scanning voltage being produced by digital control unit control DAC the utility model, both there is no the charge-discharge circuit that affects detection efficiency and working frequency range of diode and electric capacity composition, do not have expensive ADC chip input signal to be carried out to the link of high-speed sampling yet, this make digital peak testing circuit can be preferably, being operated in the design of intermediate frequency wideband circuit of lower cost; The utility model has solved peak detctor in the past in testing process, and speed is slower, and accuracy of detection is not high, complex structure, problem that cost is high.
Brief description of the drawings
Fig. 1 is the utility model structural representation;
Fig. 2 is the utility model one example structure schematic diagram;
Embodiment
As shown in Figure 1, the utility model one embodiment comprises the signal conditioning circuit, comparer, the digital control unit that connect successively, and described digital control unit accesses the input end of described comparer by analog-digital chip.
As shown in Figure 2, the utility model embodiment is wider than 100MHz by the ultra broadband electric current feedback operational amplifier U1(band connecting successively), the high-speed comparator U2(propagation delay time is greater than 10ns), high-speed digital-analog conversion chip U3(is greater than 1MHz switching time), FPGA and peripheral circuit form; Ultra broadband electric current feedback operational amplifier U1 is lifted to input signal in the working range of rail-to-rail high-speed comparator U2 of single power supply; The output of ultra broadband electric current feedback operational amplifier U1 is connected to the inverting input of high-speed comparator U2; FPGA generation DIN, SCLK, signal is to high-speed digital-analog conversion chip U3, and the scanning voltage that high-speed digital-analog conversion chip U3 produces is connected to the in-phase input end of high-speed comparator U2; The output of pulse signal that high-speed comparator U2 produces, to FPGA, detects the input signal peak information obtaining and exports from FPGA.
C2, the C3 of the present embodiment, C4, C5, C6, C7, C8, C9 are power supply filter capacitor, need the power pins near chip as far as possible, the tantalum electric capacity that wherein C2, C4, C6, C8 are 10uF, the chip ceramic capacitor that C3, C5, C7, C9 are 10nF.
Input signal is raised 2V by R1, the R3 of the present embodiment, R4, and the enlargement factor of ultra broadband electric current feedback operational amplifier U1 is that R6, R7 increase outside sluggishness to high-speed comparator, and R8 is the build-out resistor of 50 Ω.
Ultra broadband electric current feedback operational amplifier U1 conditioning signal is later connected to the inverting input of high-speed comparator, the scanning voltage that DAC U3 produces is connected to the in-phase input end of high-speed comparator, in the time that ultra broadband electric current feedback operational amplifier U1 conditioning signal is later higher than the scanning voltage of DAC generation, high-speed comparator can produce a pulse signal, and pulse width is the conditioning signal time period higher than this scanning voltage later.
The in-phase input end of high-speed comparator U2 connects a less feedback, increases the threshold region of high-speed comparator U2, increases to high-speed comparator U2 outside sluggish, facilitates the detection of pulse signal and reduces the susceptibility to noise.
FPGA receives after the pulse signal of high-speed comparator U2 generation, just can control DAC U3 and produce the scanning voltage of half that variable quantity is variable quantity last time, scanning voltage be increase or reducing whether produced pulse signal by the upper cycle decides, while having pulse signal, scanning voltage increases, and while thering is no pulse signal, scanning voltage reduces.
The retention time of the scanning voltage that DAC produces need be greater than the cycle length of input signal, to ensure that all magnitudes of voltage in one cycle of input signal all participate in the comparison of this scanning voltage.
Principle of work of the present utility model is: input signal Si n is raised 2V by ultra broadband electric current feedback operational amplifier U1, and its amplitude is in the working range of high-speed comparator U2, the sweep signal of the input signal after raising and high-speed digital-analog conversion chip U3 output is compared, when the scanning voltage of the peakedness ratio high-speed digital-analog conversion chip U3 output of the input signal after raising is high, high-speed comparator U2 produces a pulse signal, FPGA receives after this pulse signal, just can control high-speed digital-analog conversion chip U3 and produce the scanning voltage of half that variable quantity is variable quantity last time, scanning voltage be increase or reducing whether produced pulse signal by the upper cycle decides, while having pulse signal, (no matter having how many pulse signals in this cycle) scanning voltage is next time the value that current scanning voltage adds this variable quantity half, while thering is no pulse signal, scanning voltage is next time the value that current scanning voltage deducts this variable quantity half, the retention time of the scanning voltage that high-speed digital-analog conversion chip U3 produces need be greater than the cycle length of input signal, to ensure that all magnitudes of voltage in one cycle of input signal all participate in the comparison of this scanning voltage.

Claims (3)

1. an intermediate frequency wideband digital peak detection circuit, is characterized in that, comprises the signal conditioning circuit, comparer, the digital control unit that connect successively, and described digital control unit accesses the input end of described comparer by analog-digital chip.
2. intermediate frequency wideband digital peak detection circuit according to claim 1, is characterized in that, described digital control unit adopts FPGA; The data-out port of described FPGA, clock signal port, enable signal port are connected with data-in port, clock signal port, the enable signal port of described analog-digital chip respectively; The output pulse signal of described comparer accesses the data-in port of described FPGA.
3. intermediate frequency wideband digital peak detection circuit according to claim 2, is characterized in that, the inverting input of described comparer is connected with described signal conditioning circuit output port; The input end in the same way of described comparer receives the scanning voltage that described analog-digital chip produces.
CN201320879495.0U 2013-12-30 2013-12-30 Intermediate-frequency broadband digital peak detection circuit Expired - Fee Related CN203858282U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201320879495.0U CN203858282U (en) 2013-12-30 2013-12-30 Intermediate-frequency broadband digital peak detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201320879495.0U CN203858282U (en) 2013-12-30 2013-12-30 Intermediate-frequency broadband digital peak detection circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108549039A (en) * 2018-04-13 2018-09-18 同济大学 A kind of Switching Power Supply ripple measuring circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108549039A (en) * 2018-04-13 2018-09-18 同济大学 A kind of Switching Power Supply ripple measuring circuit

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