JP2009250808A - Frequency measurement device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a measurement device of frequency change, having improved frequency measuring resolution, without using a complicated circuit. <P>SOLUTION: This frequency measurement device is equipped with a short gate time counter part 20 for continuously counting a supplied pulse stream signal, in a short gate time, and outputting a series of count values existing in a pulse stream shape between two values, corresponding to the frequency of the pulse stream signal; and a low-pass filter 30 for removing high-frequency components from the series of counted values, and outputting a level signal, corresponding to the frequency of the supplied pulse stream signal. The short gate time counter part 20 outputs a series of counted values with n-bit (natural number) counter, having a bit number smaller than the bit number necessary for display of the maximum frequency of the pulse stream signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to frequency measurement, and more particularly, to a measurement method and a measurement apparatus capable of detecting a slight frequency change.

As a frequency measurement method, a direct counting method (Patent Document 1) that counts pulses passing within a predetermined gate time and a reciprocal method that accurately measures the pulse period and obtains the frequency from the reciprocal of the time are known. (Non-Patent Document 1). The direct counting method can be realized with a relatively small circuit, but it is necessary to take a long gate time in order to increase the frequency resolution (for example, the gate time necessary to obtain a resolution of 0.1 Hz is 10 seconds). The reciprocal method can overcome this drawback, but the circuit for accurately measuring the pulse interval is large compared to the direct count format.
JP-T 6-501554 Kazuya Katano, Series 14 How to use time measuring instruments, Introduction to correct usage of measuring instruments, Monthly "Transistor Technology", p. 331 (Feb. 1994)

  By using a QCM (Quartz Crystal Microbalance) method using a crystal resonator, a small amount of mass change on the surface of the resonator substrate can be converted into a frequency change. For example, various odor sensors can be formed by providing a material to which the odor component adheres on the surface of the vibrator substrate. The odor component is composed of a single substance or a plurality of substances. When the sample gas is applied to the odor sensor to attach an odor component and the mass of the vibrator surface is changed, the frequency changes. By preparing one or more types of sensors and observing this change, it is estimated that a specific odor component exists. There are about 350 types of olfactory cells in the human nose, and it is said that there are about 1000 types in the case of the dog's nose, and the brain recognizes the pattern of the proportion of odorous components attached to each olfactory cell. Identifying odors. In order to detect and identify odor components when learning from the olfaction of living organisms, it is necessary to use a large number of odor sensors (sensor arrays) and analyze the output patterns of each sensor with a computer to identify the odor component patterns. is necessary.

  However, in order to detect the frequency change of each odor sensor, a counter and a signal processing circuit for detecting the frequency change must be provided in the output of each sensor. Furthermore, even if the frequency of the crystal resonator (for example, 30 MHz) changes depending on the adhered substance, it is only about several Hz to several hundred Hz, and may be a change of 1 Hz or less. As described above, in the direct count method, it is necessary to take a considerably long gate time in order to increase the frequency resolution. As an error in measurement, in addition to a plus / minus one count error and an error due to fluctuation of the trigger level, when the gate time is increased, an error due to the oscillation stability of the crystal resonator is superimposed. Such a drawback can be compensated for by using a reciprocal counter, but the circuit of one counter is large, so that it is not suitable for a sensor array having a large number of sensors.

  Therefore, an object of the present invention is to provide a frequency change measuring apparatus with improved frequency measurement resolution without using a complicated circuit. Another object of the present invention is to provide a frequency measuring device that can configure a counter circuit used for frequency measurement as simply as possible.

  To achieve the above object, the frequency measuring apparatus of the present invention continuously counts the supplied pulse train signal in a short gate time and outputs a series of count values that behave in a pulse train corresponding to the frequency of the pulse train signal. A short gate time counter unit, and a low-pass filter that removes high frequency components from the series of count values and outputs a level signal corresponding to the frequency of the supplied pulse train signal, the short gate time counter unit, The series of count values is output by an n bit counter (n is a natural number of 2 or more) which is smaller than the number of bits necessary to display the maximum frequency of the pulse train signal.

  In such a configuration, first, the count value corresponding to the frequency behaves as a pulse train by sampling the pulse train signal to be measured by shortening the gate time (in a certain range on the time axis, a pulse train shape having one of two values). As a series of count values). At this time, the change in the density of the pulse train corresponding to the change in the measured frequency is measured. By passing this pulse train through a low-pass filter, a measured frequency signal is obtained from the pulse train. When the frequency change range of the frequency signal to be measured is within a certain range, there is no change in the upper bits of the full range counter, and a frequency change appears in the lower n bits. Therefore, frequency changes can be extracted by using an n-bit counter, and the full-range counter circuit can be replaced with a simple configuration.

  Preferably, n is 2 to 4 bits. By using a counter of 2 bits or more, it is possible to determine the occurrence of overflow (carrying) or underflow (carrying down) from a series of changes in the count value. For example, by using a 3-bit counter, it is possible to further reduce the occurrence of overflow (carry) and underflow (carry-down) than in the case of a 2-bit counter, and correct the count value and adjust the sampling frequency. The number of times can be reduced.

The frequency measuring device further divides the supplied pulse train signal by m (natural number) and supplies it to the short gate time counter unit, and a level signal output from the low-pass filter. and a multiplier for multiplying by m.
As a result, when the pulse train signal to be supplied has a high frequency, it is possible to configure the subsequent counter unit and subsequent circuits with relatively low-speed operation circuits by providing a high-speed divider in the previous stage. . This also reduces power consumption. Further, it is possible to change the apparent frequency of the pulse train signal supplied to the counter unit by making the frequency division ratio m variable.

  The frequency measuring device of the present invention also includes a short gate time counter unit that continuously counts a supplied pulse train signal in a short gate time and outputs a series of count values that behave in a pulse train corresponding to the frequency of the pulse train signal. And a low pass filter that obtains a level signal corresponding to the frequency of the supplied pulse train signal by removing high frequency components from the series of count values, and the short gate time counter section is supplied with the pulse train signal The 1-bit counter and the frequency of the pulse train signal are increased or decreased, and the corresponding increase / decrease direction of the count value output from the 1-bit counter is determined. Based on the determination result, the 1-bit counter And a polarity discrimination circuit for determining whether the count value is normal or reverse.

  When the frequency change of the pulse train signal to be measured is small, it is possible to more easily configure the short gate counter unit with a 1-bit counter. However, in this case, since it is unclear whether the counted values “0” and “1” mean large (true value) or complement, it is not possible to detect the pulse train signal by the polarity discrimination circuit. The meaning of the count value (true value or complementary value) can be determined by determining whether the count value has increased or decreased correspondingly.

  Whether the count value represents a true value or a complementary value is expressed as a function of the measured frequency and the sampling frequency (gate time), so these values are known or It can be known by making the measurement frequency known only by separately measuring it once. In this case, the polarity discrimination circuit can be omitted.

  Preferably, the upper p bits of the n-bit counter are used as a counter output, and the lower (mp) bits are used as a frequency divider. Thereby, the functions of the frequency divider and the counter can be realized by one counter. For example, by using the upper 2 bits of the 4-bit counter as output bits, a ¼ frequency divider is configured by the lower 2 bits.

  The frequency measuring apparatus of the present invention also includes a frequency divider that divides a supplied pulse train signal by m (m is a natural number), and continuously counts the divided pulse train signal in a short gate time. A short gate time counter unit that outputs a series of count values that behave in a pulse train corresponding to the frequency of the output, and outputs a level signal corresponding to the frequency of the supplied pulse train signal by removing high frequency components from the series of count values And a multiplier that multiplies the level signal output from the low-pass filter by m.

  By adopting such a configuration, it is only necessary to increase the speed of only the frequency divider portion, and it is possible to operate the short gate time counter section and the subsequent parts at a relatively low speed. Since the value output from the low-pass filter is 1 / m times the frequency of the pulse signal to be measured, appropriate scaling can be performed by multiplying the value by m. Further, it is possible to change the pulse density supplied to the counter unit by making the frequency division ratio m variable, which is good.

  Here, a multiplication circuit for scaling is provided, but this can be omitted if scaling is not a concern.

  The gate time is less than 1 second and longer than the operating limit of the apparatus. For example, the gate time is less than 1 second and greater than 0.01 μsec.

  Preferably, the gate time is less than 1 second and greater than the operating limit of the device. For example, when performing gate sampling of about 0.1 msec, compared to the conventional direct counting method, for example, it can be expected to improve performance by about 1 to 2 digits in time resolution and about 2 to 3 digits in SN ratio. By configuring the frequency counting and data recording by hardware, it is possible to perform measurement with a gate time of less than 1 μsec.

  Preferably, the short gate time counter unit includes a counter that does not cause a dead period for the pulse train signal. Here, the dead period is a period during which the pulse train signal input to the counter cannot be measured, which occurs when the counter is reset or the count value is transferred. As will be described later, if a discontinuity occurs in the output pulse train of the short gate time counter section due to a counter reset operation or the like, the preceding and succeeding data trains (values) are cut off, resulting in a kind of disturbance.

  Preferably, the low-pass filter is an analog filter or a digital filter.

  The low-pass filter is preferably an analog filter. The memory and arithmetic unit required for the digital filter can be omitted. Also, when the count value of the short gate time counter section takes a binary value and behaves as a pulse train (FIG. 4), the analog filter low-pass filter functions as a DA converter, which is good. When the output of the counter is n-bit data, a DA converter can be used before the low-pass filter.

  The low-pass filter is preferably a digital filter. A moving average filter is more desirable. The moving average filter can be configured with a relatively small circuit scale and a small amount of calculation compared to a general FIR filter (finite impulse response filter), and a linear phase compared with an IIR filter (finite impulse response filter). It is possible to enjoy the advantages of the FIR filter as it is, such as realizing characteristics and guaranteeing stability.

  It is desirable that the low-pass filter has a configuration in which moving average filters are connected in series in multiple stages (two or more stages). The multi-stage moving average filter has an advantage that the performance as a low-pass filter can be improved while minimizing an increase in the amount of calculation, compared to the one-stage moving average filter.

  The counter that does not generate the dead period is a direct count type counter that cumulatively counts the pulse train signal, and a subtractor that obtains the current count value from the difference between the previous accumulated count value and the current accumulated count value. It is desirable to include. As a result, it is possible to configure a counter having no dead period without using the two counters alternately.

  Preferably, the low-pass filter is a combination of a digital filter and an analog filter. Thereby, it is possible to combine the advantages of a digital filter with a good S / N ratio and an analog filter that does not require computation. Compared with the processing using only the digital filter, the combination of the digital filter and the analog filter does not require the performance of the digital filter as a low-pass filter, so the number of taps can be greatly reduced. For example, when a one-stage moving average filter is used as the digital filter, an up / down counter can be used for the filter processing, so that the circuit can be simplified in addition to the reduction in the number of taps.

  In addition, the frequency measuring method of the present invention continuously counts a supplied pulse train signal with a short gate time counter in a short gate time, and obtains a series of count values that behave like a pulse train corresponding to the frequency of the pulse train signal. Thus, a high-frequency component is removed from the series of count values by a low-pass filter to obtain a level signal corresponding to the frequency of the supplied pulse train signal, and the short gate time counter has a maximum frequency of the pulse train signal. The series of count values is output using an n (n is a natural number of 2 or more) bit counter having a smaller number of bits than that necessary for display. Preferably, n is 2 to 4 bits. Frequency measurement can be performed with a relatively simple configuration.

  Further, the supplied pulse train signal is divided by a frequency divider and supplied to the short gate time counter unit, and the level signal output from the low-pass filter is scaled by a multiplier. Thereby, the apparent frequency of the pulse train signal can be lowered.

  Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 show an outline of the frequency measuring apparatus of the present invention. In each figure, the same reference numerals are given to corresponding parts.

  In FIG. 1, a signal source 10 generates a pulse train signal. The signal source 10 is, for example, a crystal oscillator having an oscillation frequency f0 of 30 MHz, and corresponds to a detection unit such as an odor sensor, a gas sensor, or a biosensor described later. When an odor substance or the like adheres to the crystal resonator, the oscillation frequency decreases according to the amount of adhesion. This pulse train signal is supplied to a short gate time counter (hereinafter simply referred to as “short gate counter”) 20. The short gate counter 20 performs pulse counting of the supplied pulse train signal without interruption in a short gate time. The count value has a corresponding relationship with the frequency of the pulse train signal, and is sequentially supplied to the low pass filter (LPF) 30.

  FIG. 4 shows an example of the count value. In this example, the pulse train signal is counted at a sampling frequency of 100 Hz (gate time 0.01 seconds). When the sampling frequency is 100 Hz, the frequency resolution is also reduced to 100 Hz, so that information of 100 Hz or less of the supplied pulse train signal cannot be detected from only one count value, but 100 count values can be obtained per second. Become. The frequency which is 100 times the count value is distributed in a pulse shape on the time axis between 30,072,300 Hz and 30,072,400 Hz.

  Here, a quantization error (± 1 count error) in sampling will be described. For example, consider the case of measuring a pulse train signal that is stable at 123.34 Hz with a direct count counter.

  When the gate time is 10 seconds: 1233 counts or 1234 counts every 10 seconds

  This is multiplied by 1/10 to display 123.3 Hz or 123.4 Hz (every 10 seconds). (Measurement error is 0.1Hz)

  When the gate time is 1 second: 123 or 124 counts per second

  The display is 123 Hz or 124 Hz (every second). (Measurement error is 1 Hz)

  When the gate time is 0.1 seconds: 12 or 13 counts every 0.1 seconds

  This is multiplied by 10 to display 120 Hz or 130 Hz (every 0.1 second). (Measurement error is 10Hz)

  When the gate time is 0.01 seconds: 1 count or 0 count every 0.01 seconds

  This is multiplied by 100 to display 100 Hz or 200 Hz (every 0.01 seconds). (Measurement error is 100Hz)

In this way, when a pulse train signal that is stable at a certain frequency is counted, a quantization error corresponding to the gate time occurs, and the count value is distributed in a pulse train having an amplitude between two values determined by the gate time. To do. On the other hand, even if the frequency of the pulse train signal to be counted fluctuates, the count values are still distributed in a pulse train having an amplitude between two values as long as the fluctuation is within the measurement error. For example, when the gate time is 0.01 seconds, as long as the variation in the frequency of the pulse train signal to be counted is within 100 to 200 Hz, a display of 100 Hz or 200 Hz can be obtained.

  As shown in FIG. 4, in the method of sampling with a short gate time of less than 1 second (hereinafter referred to as “short gate time count method”), the count value behaves as a pulse train, and the pulse train is changed according to the change in the measured frequency. The frequency (roughness) changes. The magnitude of the vibration frequency corresponds to the density of the pulse train. Information on the frequency of the pulse train signal to be counted exists in the low frequency component of the frequency spectrum of the count value that behaves as a pulse train. Therefore, the frequency information of the pulse train signal to be counted can be demodulated by extracting the low frequency component from the count value by the low pass filter (removing the harmonic component due to the quantization error).

  FIG. 5 shows an example in which the above-described column of count values in FIG. 4 is applied to a (digital) low-pass filter 30 with 512 taps to remove high frequency components. As shown in the figure, the change in the frequency of the supplied pulse train signal is output as a continuous (analog) curve. It is possible to detect a region that cannot be measured by counting at a sampling period of 100 Hz, in particular, a frequency change of 1 Hz or less.

  Next, a comparison between the short gate time counting method and the direct counting method will be described with reference to FIGS.

  In the graph of FIG. 6, the vertical axis represents frequency and the horizontal axis represents time. A curve A in the figure shows a case where sampling is performed by setting the gate time to 1 second by the direct counting method. A curve B shows a case where sampling is performed by setting the gate time to 0.1 second by the direct count method. A curve C shows a case where sampling is performed by setting the gate time to 0.01 seconds by the direct counting method. Note that the curve C is displayed separately below because the unit (digit) of the time axis is different and a waveform cannot be represented on the same graph. A curve D shows a case where sampling is performed by setting the gate time to 0.01 seconds + low-pass filter by the direct count method (short gate time count method). FIG. 7 compares the curve A and the curve D by enlarging the frequency axis range of FIG. The curve D of the present application can be read up to the order of several tens of mHz.

  From FIG. 6, it can be seen that when the gate time is less than 1 second, the frequency change of the pulse train signal to be counted falls within the measurement error, so that the count value becomes one of the binary values to form a pulse train. It can be seen that the pulse frequency (pulse density) changes according to the frequency change. That is, it can be seen that the count value that behaves like a pulse train includes the frequency information of the pulse train signal counted in the time axis direction. Therefore, although the measurement error included in one measurement value is enlarged by shortening the gate time, this influence is removed by the low-pass filter, and the SN ratio is improved. When the gate time is 1 second, the curve becomes zigzag and the frequency of 1 Hz or less is not known, but if this is processed to remove high frequency components with a low-pass filter, the smooth characteristics similar to those of the present application will be the same. Can be obtained. Therefore, even when the gate time is 1 Hz, this method can be applied in the case where the frequency change band is slower than 1 Hz and changes slowly.

  In this way, in the short gate time counting method, if the gate time is shortened (the sampling frequency is increased), each measurement error increases, but a series of measurement values is obtained. The frequency measurement resolution is improved as shown in FIG. Since the circuit scale can be reduced, multi-channeling is easy. By using an analog low-pass filter, it is possible to cope with an analog output.

  FIG. 2 shows a first configuration example of the short gate counter unit 20 described above. It is desirable that the short gate counter unit 20 counts the pulse train signal supplied from the signal source without interruption (so as not to provide a dead period for the input signal).

  FIG. 9 shows an example of the frequency output of the low-pass filter when the count is interrupted (when the count value string to the low-pass filter is missing). It can be seen that there is a disturbance as shown by the dotted circle in the figure.

  Therefore, in the first embodiment, the first counter 21 and the second counter 22 are provided with two counters. The pulse train signal is supplied to both the first counter 21 and the second counter 22. The control unit 23 sends a gate signal and a reset signal to both counters, and supplies the outputs of both counters to the low-pass filter 30 via a switch. Count values are alternately output from both counters, and when one is counting, the other resets or transfers data, thereby avoiding a dead period that occurs during counter reset or data transfer. The control unit 23 may be configured as hardware, or may be configured as software using a personal computer or the like.

  FIG. 3 shows a second configuration example of the short gate counter unit 20. In this embodiment, one counter 24 is used. The counter 24 is a direct counting type counter, and always counts the sampled pulse signal and outputs an accumulated value (not reset). The output of the counter 24 is sent to a subtracter 25 and a register 26 that holds the previous accumulated value. The subtracter 25 subtracts the previous cumulative value from the current cumulative value output from the counter 24 to obtain the current count value, and supplies it to the low-pass filter 30. The overall operation of the apparatus is the same as that of the measuring apparatus of FIG.

  FIG. 10 shows an example in which the low-pass filter 30 is configured by an analog circuit. In this example, a low-pass filter including resistors R1 to R3, capacitors C1 and C2, and an operational amplifier OP1 is connected in two stages. When the 1-bit serial data is output from the short gate counter 20, it can be input to the low-pass filter 30 as it is. When the short gate counter 20 outputs n bits, it can be input via a DA converter.

  FIG. 11 shows an output example of the analog low-pass filter 30 when the sampling frequency is 1000 Hz.

  FIG. 12 shows an example in which the low-pass filter 30 is configured by a moving average filter. In the figure, 31 is an adder, 32 is a shift register, 33 is a subtracter, 34 is an inverter, and 35 is a control unit that supplies an operation timing clock to each unit. Reference numeral 36 denotes a divider.

  The count value output from the counter is supplied to both the adder 31 and the shift register 32 having a storage area corresponding to the number of taps. In the shift register 32, N data for which the average value is to be calculated sequentially move in synchronization with the other data. The other value of the adder 31 is supplied with the total value of the previous calculation, and the adder adds the new count value and the previous total value. The count value of the first (old) data is removed from the cumulative addition value by the shift register 32 by the subtracter 33, and this is used as the new total value. The new total value is returned to the adder as the previous total value, and the new total value is divided by the number of target data N by the divider 36. A moving average value is obtained by performing such calculation for all data. Here, the divider has a function of scaling the output value to the frequency (Hz), but it can be omitted if the scaling need not be taken care of. Further, when the moving average filter has a multi-stage configuration, a divider may be disposed only in the final stage.

  FIG. 13 is a diagram schematically illustrating the output of the moving average filter. In this example, it is assumed that the frequency of the pulse train signal to be measured gradually changes from a state where 123.34 Hz is maintained to 124.7 Hz. First, when sampling is performed at a gate time of 0.1 second, the counter 20 sends a count value of 12 or 13 at a certain rate. The total three sets of 10 data are 124, 123, 125, and the value moves in the direction of 124.7 Hz. Here, 10 of the count values of 12 or 13 (number of taps 10) are subject to moving average calculation (first stage moving average). From the moving average value in the first stage, it can be seen that the appearance of data with increased numerical values increases as it moves to the right. Furthermore, when the moving average value of the first stage is used as an input to calculate the moving average of the second stage (10 taps), this tendency is strengthened and the accuracy is improved. Using multiple stages of moving average filters is equivalent to making the attenuation slope, which is a characteristic of the low-pass filter, steep, and at the same time, removing high-frequency components from the frequency spectrum of the pulse train consisting of 12 or 13.

  In this embodiment, three stages of moving average filters (low-pass filters) are connected (total number of taps 4096, number of taps 818 (one stage), 1640 (two stages), 1640 (three stages)).

  FIG. 14 shows the impulse response of the three-stage moving average filter. FIG. 15 shows an output example of the three-stage moving average filter. Thus, a frequency change of 1 Hz or less can be measured. The moving average filter can have a multi-stage configuration in order to obtain desired characteristics.

  Next, a case where the low-pass filter 30 is configured by a combination of a digital filter and an analog filter will be described with reference to FIGS.

  FIG. 16 shows an example in which the low-pass filter 30 includes a digital filter (low-pass filter) 30a, a D / A converter 30b, and an analog filter (low-pass filter) 30c. This configuration has the following advantages.

  First, when the sampling frequency is high and the signal change of the frequency to be measured is small relative to the sampling frequency, the SN ratio may be lowered in the analog filter processing even when the digital filter processing can be demodulated without any problem. This is because the apparent dynamic range is reduced because the change in the output after filtering corresponding to the change in the signal at the measured frequency is smaller than the amplitude of the pulse. In the case of digital filter processing, the information of the quantized count value does not deteriorate, so that such a problem does not occur.

  For example, if a sampling frequency of 1000 Hz is used and a frequency change of 100 Hz is to be observed, a voltage change of 100 mV is observed when a 1000 mV pulse is analog-filtered. If it is attempted to observe a frequency change of 0.1 Hz under the same conditions, the voltage change is 0.1 mV. Therefore, for example, a signal of 0.1 Hz cannot be detected in an environment where noise of 1 mV exists in the measurement.

  On the other hand, since the frequency information quantized as the count value is not deteriorated by digital processing, such a problem does not occur in the case of digital filter processing. Therefore, the SN ratio can be improved by combining with a digital filter. Specifically, as described above, the output of the digital filter 30a is D / A converted by the DA converter 30b and input to the analog filter 30c.

  Compared with the processing using only the digital filter, the combination of the digital filter 30a and the analog filter 30c does not require the performance of the digital filter 30a as a low-pass filter, so the number of taps can be greatly reduced. In particular, when a one-stage moving average filter is used as the digital filter 30a, an up / down counter can be used for the filter processing, so that the circuit can be simplified in addition to the reduction in the number of taps.

  An example of characteristics when the low-pass filter 30 is configured by a combination of a digital filter and an analog filter and counting is performed at a sampling frequency of 1000 Hz will be described with reference to FIGS.

  First, FIG. 17 shows an output example of the low-pass filter 30 only by digital filter processing (three-stage moving average filter, number of taps 4096) as a comparative example. FIG. 18 shows an output example of the low-pass filter 30 only by analog filter processing as a comparative example. It can be seen that the analog filter has a large influence of noise (the SN ratio is reduced).

  FIG. 19 shows a digital filter when the low-pass filter 30 is composed of a combination of a digital filter 30a (single-stage moving average filter, 128 taps), a D / A converter 30b and an analog filter 30c, as shown in FIG. The output example of the DA conversion value of the output of 30a is shown. The number of taps (1 stage moving average filter, number of taps 128) of the digital filter 30a is significantly reduced compared to the comparative example (3 stage moving average filter, number of taps 4096).

  FIG. 20 shows an example in which the D / A converter output of FIG. 19 is analog processed by the low-pass filter 30c. A configuration example of the analog low-pass filter is shown in FIG. As shown in FIG. 20, the S / N ratio is improved as compared with the case of the single analog low-pass filter of FIG. 18, and it can be seen that the signal can be detected in the same manner as when only the digital filter shown in FIG. 17 is used. . As described above, the number of taps of the digital filter 30a is greatly reduced.

  In this way, by configuring the low-pass filter with a digital filter and an analog filter, it is possible to reduce the number of taps of the digital filter (decrease in the amount of calculation) and simplify the circuit while preventing a decrease in the SN ratio. .

  Next, the simplification (decrease in the number of digits) of the counter circuit configuration of the short gate counter unit 20 will be described. In the above-described embodiment, the short gate counter unit 20 is configured with a circuit scale of the number of bits (number of digits) sufficient to display the count value, and can detect the frequency of the pulse train signal via the low-pass filter.

  However, instead of measuring the absolute value of the frequency, it may be sufficient to measure the time variation (difference) of the frequency. When the short gate time count method described above is used, a change appears in several bits of the lower bits of the counter circuit output. Therefore, the counter circuit configuration can be simply configured by using an n-bit counter corresponding to this. It becomes possible.

  FIG. 21 shows an embodiment in which such a circuit is simply configured. In the figure, portions corresponding to those in FIG. 1 are denoted by the same reference numerals.

  As described above, the signal source 10 generates a pulse train signal. This pulse train signal is supplied to the short gate time counter unit 20. The short gate time counter unit 20 performs pulse counting of the supplied pulse train signal without interruption in a short gate time (sampling frequency). The count value is sequentially supplied to the low pass filter 30. The short gate counter 20 is composed of an n-bit counter that is smaller than the number of bits (number of digits) required to display the frequency (for example, 30 MHz) of the pulse train signal.

  FIG. 22 shows an example of an output value using a 3-bit counter as an n-bit counter. The sampling frequency is 10 Hz. In this example, the output value of the 3-bit counter changes within the range of 6 to 2 (decimal number display), and no carry or carry occurs. In such a case, the short gate counter unit 20 can be constituted by a 3-bit counter.

  FIG. 23 shows an example in which the frequency component is demodulated by removing the harmonic component from the count value string of the 3-bit counter by the low-pass filter 30 (64 taps). The absolute frequency cannot be grasped only with this data, but the frequency change of the pulse train signal can be sufficiently grasped.

FIG. 24 shows an example in which a 2-bit counter is used as the n-bit counter of the short gate counter unit 20 described above. In the figure, parts corresponding to those in FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted.
If the supplied pulse train signal is sampled with a short gate time and no carry or carry occurs in the count value, a 2-bit counter can be used.

  FIG. 25 shows an example of the output value of the 2-bit counter sampled at 100 Hz. In the figure, the vertical axis represents the count value (decimal number display), and the horizontal axis represents the time. In the figure, the 2-bit output counter unit 20 alternately outputs “1” and “2” count values in a pulse train form.

  FIG. 26 shows a state in which frequency components are extracted from the count value sequence of the 2-bit counter by the low-pass filter 30 (tap number 512). In the figure, the vertical axis represents frequency and the horizontal axis represents time. Detection is possible with a frequency resolution of 1 Hz or less.

  Next, a case where the count value is outside the count output range of the n-bit counter when using an n-bit counter (carry (overflow), carry-down (underflow)) will be described.

  FIGS. 27 to 30 show an embodiment in which carry-over and carry-down processing of a 2-bit counter is performed. In this embodiment, in order to cope with carry and carry, the count value output of the 2-bit counter is replaced with a 4-bit output and supplied to the low-pass filter.

  In this example, the short gate counter unit 20 uses a 2-bit counter 24. The counter 24 is a direct counter and always counts the sampled pulse signal and outputs an accumulated value (not reset). The output of the counter 24 is sent to a subtracter 25 and a register 26 that holds the previous accumulated value. The subtracter 25 subtracts the previous cumulative value from the current cumulative value output from the counter 24 to obtain the current count value (see FIG. 3).

  The count value (current count value) output from the subtracter 25 is supplied to the 2-4 bit conversion unit 28. The 2-4 bit conversion unit 28 is configured by a data processing program or programmable logic by a microprocessor (MPU), and determines whether a carry or a carry is generated from a continuous 2-bit count value sequence. A 4-bit value indicating the value that has been dropped is output to the low-pass filter 30.

  For example, the 2-bit counter 24 outputs “0”, “1”, “2”, “3” in decimal notation, but the count value is “ The next “4” after “3” returns to “0”. In the decreasing direction, the count value returns to “3” at “−1” after “0”. Therefore, when the count value changes from “2”, “3” (binary number 10, 11) to “0” (binary number 00), it can be determined that a carry has occurred. I can do it. When the count value changes from “0”, “1” (binary number 00, 01) to “3” (binary number 11, complement), it is determined that a carry has occurred. I can do it.

  A 2-bit input 4-bit output subtractor having the functions of the subtractor 25 and the 2-4 bit conversion unit 28 may be used.

  28 and 29 show examples of input values to the 2-4 bit conversion unit 28 and examples of output values of the 2-4 bit conversion unit 28, respectively (sampling frequency 10 Hz). When the 2-bit counter outputs 1 and 0 (decimal number) alternately, the 2-4 bit conversion unit 28 outputs 1 and 0 (decimal number) correspondingly. Next, as shown in FIG. 28, when the first carry-down occurs, the 2-4 bit conversion unit 28 sets the output to the -1 and 0 alternate output states. Further, the output of the 2-4 bit conversion unit 28 is set to −1, − corresponding to each level drop to the alternate input state of count value 3, 2 and 2, 1 alternate input state, and 1, 0 alternate input state. 2 alternate output states, -2 and -3 alternate output states, and -3 and -4 alternate output state values. Further, the output of the 2-4 bit conversion unit 28 is set to the -4 and -5 alternate output states corresponding to the second carry of the 2-bit counter output. Next, an alternate output state of -3 and -4 is made corresponding to an alternate input state of 0 and 1 of the 2-bit count value. In the same manner, the count values 1 and 2 are alternately input, the count values 2 and 3 are alternately input, the count values 3 and 0 are alternately input (the first carry is generated), and the 0 and 1 are alternately input. Corresponding to each level decrease, the output of the 2-4 bit conversion unit 28 is changed to -3, -2 alternating output state, -2, -1 alternating output state, -1, 0 alternating output state, 0, 1 Set to alternate output state.

  FIG. 30 shows an example in which the high frequency components are removed from the 4-bit count value sequence shown in FIG. 29 by the low-pass filter 30 (tap number 64). The change in frequency can be grasped sufficiently.

  FIG. 31 shows another embodiment in which the short gate counter unit 20 is constituted by a 1-bit counter. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

  As described above, when the frequency change range of the signal source is known, it is possible to set a condition in which no carry occurs in the 1-bit counter by increasing the sampling frequency of the short gate counter unit 20. In this case, a measurement result similar to that of the above-described embodiment can be obtained with a 1-bit counter.

  However, with 1-bit information, it cannot be determined whether the output of the count values 0 and 1 corresponds to the magnitude of the count value or a complement relationship. Therefore, in this embodiment, a bit discrimination unit 70 is provided. The bit discriminating unit 70 increases or decreases the oscillation frequency of the signal source 10, and when the output of the low-pass filter increases or decreases correspondingly, the output of the count values 0 and 1 corresponds to the magnitude of the count value. Is determined. Further, when the oscillation frequency of the signal source 10 is increased or decreased and the output of the low-pass filter is decreased or increased correspondingly, the outputs of the count values 0 and 1 have a complement relationship (the output is reversed). Is determined. In the case of a complement relationship, the output characteristic of the output of the low-pass filter 30 is inverted by the forward / reverse inversion unit 60.

  32 to 34 show output examples of the low-pass filter (each example tap number 2048) in the embodiment using the 1-bit counter. FIG. 33 shows an output waveform of the frequency when the count value is a complement. FIG. 34 shows the inversion of the frequency output after passing through the low-pass filter. It can be seen that the original waveform is corrected by inversion.

FIG. 35 shows an example in which scaling is performed by providing a frequency divider before the short gate counter 20. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
In the example shown in the figure, the pulse train signal from the signal source 10 is divided by m by the frequency divider 40 and supplied to the short gate counter 20. The short gate counter 20 performs counting with a short gate signal having a gate time smaller than 1 second, and supplies a series of count value sequences to the low-pass filter 30. Frequency information of the original pulse train signal is obtained by multiplying the frequency signal extracted by the low-pass filter 30 by m times by the multiplier 50.

FIG. 36 shows an example of frequency output when processing is performed by the low-pass filter 30 (number of taps 2048) with the frequency division ratio m of the frequency divider 40 and the multiplier ratio m of the multiplier 50 set to 16 in the configuration of the above embodiment. ing. Similar to other examples, a smooth frequency output of 1 Hz or less can be obtained.
By providing such a frequency divider (prescaler) in front of the short gate counter unit, when the frequency to be measured is a high frequency, it is only necessary to speed up the frequency divider, and the circuit after the counter unit is relatively low. It is possible to drive at a frequency, which is good.

  FIG. 37 shows an application example of the embodiment shown in FIG. 35. Parts corresponding to those in FIG. 35 are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, the frequency divider 40 and the short gate counter unit 20 are constituted by a 4-bit counter. For example, by using the upper 2 bits of a 4-bit counter, an output similar to that obtained when a frequency divider that divides by 4 and a 2-bit counter are combined can be obtained. That is, the upper bit p (for example, the upper 2 bits) of the m-bit counter can be used as an output bit, and the lower (mp) bit can be used as a prescaler. Other configurations are the same as those in FIG.

  FIG. 38 shows an output example of the frequency of the example using the upper 2 bits of the 4-bit counter. The sampling frequency is 1000 Hz, and the number of taps of the low-pass filter is 2048. A smooth output capable of discriminating frequencies of 1 Hz or less is obtained.

  FIG. 39 shows an example in which the frequency measurement device of the present application is provided in an odor sensor array as a signal source 10 including a large number of odor sensors 10a to 10n. Since the short gate sensor unit 20 and the low-pass filter 30 have already been described, a description thereof will be omitted.

  FIG. 40 shows an output example for eight channels of the sensor array at a sampling frequency of 1 Hz in the conventional direct count method. On the way, the odor component was supplied for several seconds at the arrow on the time axis. The frequency decreased due to the odor component adhering to the sensor, and the adhering odor substance was detached in about 10 seconds.

  FIG. 41 shows an example of measurement using the short gate time counting method of the present invention under the same conditions. It can be seen that both time resolution and frequency resolution are improved. In addition, the short gate time count method is convenient for use in a multi-sensor module (or substrate) because the circuit is not complicated.

  According to the embodiment of the present invention described above, since the short gate count unit is constituted by a 2-bit counter, the counter circuit is simplified and power consumption can be suppressed.

  Further, by providing a function for incrementing or decrementing the count value, it is possible to cope with frequency fluctuations in which a carry or a carry is caused in the bits of the counter used.

  In addition, by configuring the short gate count unit with an n-bit counter that does not cause carry or carry out of the display output, a correction circuit that increases or decreases the count value in response to the occurrence of carry or carry is unnecessary. It looks good.

  In addition, when the short gate counter unit is configured with a 1-bit counter, the counter circuit is simplified.

  Further, by using the upper 2 bits of the m-bit counter, it is possible to incorporate functions as a prescaler and a counter.

  In addition, each implementation mentioned above can be combined suitably.

  As described above, the circuit is not complicated as compared with the reciprocal method by counting with a short gate time and passing the low-pass filter. Time and frequency resolution can be improved at the same time. This is suitable for measurement under conditions where the sampling frequency is oversampling with respect to the signal under measurement. In addition, since the conventional direct count method is easily affected by the duty cycle modulation, it is necessary to devise if this effect cannot be ignored, but in this method, the influence is reduced by increasing the sampling frequency. No special device is required.

  In addition, the short gate time count method is a method in which the count value is obtained by shortening the gate time to increase the number of measurement points and removing the high frequency spectrum component of the data string, and the frequency resolution is remarkably improved. However, since the quantization error of each measurement value is large, the influence of the lack of one measurement point on the resolution becomes relatively large. Therefore, measurement errors can be reduced by using a counter that can count the pulse signal without interruption.

  It is effective to use a counter that does not require reset as proposed in the embodiment. There is a method in which two counters are switched and used in order to make a dead time caused by reset operation, data reading, etc., but the circuit scale becomes large. This method can be substituted by preparing two latch circuits and switching between them. In this case, the count value is calculated by subtracting the previous measurement value from the measurement value. When the sampling frequency is lower than the operating frequency of the counter, the calculation time can be given a margin. By doing so, only one counter is required, and the circuit scale does not increase.

  By using the apparatus equipped with the method of the present invention, the resolution of the sensor can be obtained without changing the measurement system by applying this signal processing to the measured value obtained from the conventional frequency counter regardless of the counting method. Is improved. The counter designed with this system in mind is smaller in circuit scale than the conventional counter having the same performance and can be easily multi-channeled. The short gate time counting method of the present invention is convenient for use in an odor sensor, a gas sensor, a biosensor, an A / D conversion element utilizing frequency change, or the like.

It is a figure explaining the outline | summary of this invention. FIG. 3 is a diagram illustrating a configuration example of a short gate counter unit 20. It is a figure explaining the other structural example of the short gate counter part. It is a figure explaining the example of the count value by the short gate counter part. 4 is a diagram illustrating an output example of a low-pass filter 30. It is explanatory drawing explaining a short gate time system. It is explanatory drawing explaining the example of an output by a short gate time system. It is explanatory drawing explaining the example of an effect by a short gate time system. It is a figure explaining the influence of the discontinuity of input. It is a figure explaining the example of a low-pass filter (analog). It is a figure explaining the example of an output of a low-pass filter (analog). It is a figure explaining the example of a low-pass filter (moving average). It is a figure explaining the example of a moving average calculation, the number sequence of the 2nd row in the figure is equivalent to 1 step moving average filter output value (the number of taps of the 1st step), and the number sequence of the 3rd row moves 2 steps This corresponds to the average filter output value (10 taps in the second stage). It is a figure explaining the example of an impulse response of a low-pass filter (moving average). It is a figure explaining the example of an output of a low pass filter (moving average). It is a figure explaining the example which comprises a low-pass filter combining a digital filter and an analog filter. It is a figure explaining the example of an output of the digital filter (moving average filter 3 steps | paragraph structure) of a reference example. It is explanatory drawing explaining the example of an output of the analog filter of a reference example. It is a figure explaining the example of an output which D / A converted the output of the digital filter (moving average filter 1 step | paragraph structure). It is a figure explaining the example which processed the D / A conversion value by the analog filter. It is a figure explaining the example which comprises a short gate counter part by the counter of n bits. It is explanatory drawing explaining the example of an output of a 3-bit counter. It is a figure explaining the example of an output of a low-pass filter. It is a figure explaining the example which comprises the short gate counter part 20 by a 2-bit counter. It is explanatory drawing explaining the example of an output of a 2-bit counter. It is a figure which shows the example of an output of a low-pass filter. It is a figure explaining the example which provided the circuit which converts 2 bit output into 4 bit output in the back | latter stage of the short gate counter part of 2 bit output. It is explanatory drawing explaining the example of an output of a 2-bit counter. It is explanatory drawing explaining the example of the 4-bit input value to a low-pass filter. It is a figure which shows the example of a 4-bit input and the output of a low-pass filter. It is a figure explaining the example which comprised the short gate part with 1 bit counter. The figure which shows the example of an output at the time of comprising a short gate part by 1 bit counter. It is a figure which shows the example of an output when the output of a 1-bit counter is a complement. It is a figure explaining the output example which correct | amended the complement output. It is a figure explaining the example which uses a frequency divider in the front | former stage of a short gate counter. It is a figure explaining the example of an output at the time of using a frequency divider. It is explanatory drawing explaining the example which functions as a prescaler and a counter using the upper 2 bits of a 4-bit counter for output. It is a figure which shows the example of an output at the time of using the upper 2 bits of a 4-bit counter. It is a figure explaining the example which applied this application to the sensor array. It is a figure which shows the example of an output of the sensor array by the conventional method. It is a figure which shows the example of an output of the sensor array by the method of this application.

Explanation of symbols

10 signal source, 20 short gate counter, 30 low-pass filter

Claims (15)

A short gate time counter unit that continuously counts the supplied pulse train signal in a short gate time and outputs a series of count values that behave in a pulse train shape corresponding to the frequency of the pulse train signal;
A low-pass filter that removes high-frequency components from the series of count values and outputs a level signal corresponding to the frequency of the supplied pulse train signal, and
The short gate time counter unit outputs the series of count values with an n bit counter (n is a natural number of 2 or more) having a bit number smaller than the number of bits necessary for displaying the maximum frequency of the pulse train signal. A characteristic frequency measuring device.   The frequency measuring apparatus according to claim 1, wherein n is 2 to 4 bits.   The frequency measuring device according to claim 1, further comprising a frequency divider that divides the supplied pulse train signal and supplies the divided pulse train signal to the short gate time counter unit.   The frequency measuring device according to claim 1, further comprising a multiplier that scales a level signal output from the low-pass filter. A short gate time counter unit that continuously counts the supplied pulse train signal in a short gate time and outputs a series of count values that behave in a pulse train shape corresponding to the frequency of the pulse train signal;
A low-pass filter that removes high-frequency components from the series of count values to obtain a level signal corresponding to the frequency of the supplied pulse train signal, and
The frequency measuring device, wherein the short gate time counter unit is a 1-bit counter to which the pulse train signal is supplied. Furthermore, the short gate time counter unit is
The frequency of the pulse train signal is increased or decreased, and the increment / decrement direction of the count value output from the 1-bit counter is determined correspondingly, and the count value of the 1-bit counter is determined based on the determination result. Including a polarity discrimination circuit for determining,
The frequency measuring device according to claim 5, wherein A frequency divider for dividing the supplied pulse train signal;
A short gate time counter unit that continuously counts the divided pulse train signal in a short gate time and outputs a series of count values that behave in a pulse train corresponding to the frequency of the pulse train signal;
A low-pass filter that removes high-frequency components from the series of count values and outputs a level signal corresponding to the frequency of the supplied pulse train signal;
A frequency measuring device comprising: A multiplier for scaling the level signal output from the low-pass filter;
The frequency measurement device according to claim 7.   The frequency measurement apparatus according to claim 1, wherein the upper p bits of the n-bit counter are used as a counter output, and the lower (mp) bits thereof are used as a frequency divider.   The frequency measurement device according to claim 1, wherein the gate time is a time shorter than one second and longer than an operation limit of the device.   The short gate time counter unit includes a counter that does not cause a dead period for the pulse train signal. The frequency measuring device according to claim 1.   The frequency measurement device according to claim 1, wherein the low-pass filter is an analog filter or a digital filter.   The frequency measurement device according to claim 1, wherein the low-pass filter is a combination of a digital filter and an analog filter.   The frequency measuring device according to claim 12 or 13, wherein the digital filter is a moving average filter having a multistage configuration.   The apparatus using the frequency measuring device in any one of Claims 1 thru | or 14.

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