JP2010127914A - Frequency measurement device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency measurement device of short gate counting method, which simplifies a circuit such as a filter as much as possible, increases the speed, and reduces the power in a circuit operation. <P>SOLUTION: This frequency measurement device includes: a short gate time counter (10) that counts signals to be measured at a predetermined sampling frequency and outputs a counted value corresponding to the frequency of the signals to be measured; and a low-pass filter (20) for filtering the counted value. The low-pass filter includes a first moving average filter (21), and is set so that the value obtained by dividing the sampling frequency by the number of taps of the first moving average filter is larger than a frequency variation range of the signals to be measured. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a frequency measurement device, and more particularly, to improve a short gate time count frequency measurement device that continuously counts a signal under measurement with a short sampling period and detects a frequency fluctuation component by removing a high frequency component from a count value sequence. About.

The frequency measurement method includes a direct counting method (see, for example, Patent Document 1) that counts pulses passing within a predetermined gate time, and a reciprocal method that accurately measures the pulse period and obtains the frequency from the reciprocal of that time ( For example, see Patent Document 2), and a method of knowing the frequency by obtaining a ΔΣ modulation signal (see Patent Document 3, for example) is known.
JP 2001-119291 A JP-A-5-172861 US Pat. No. 7,230,458

  In addition to the above, the applicant has proposed a frequency measurement apparatus using a short gate time count method (Japanese Patent Application No. 2008-099721).

  This frequency counting method repeats counting (sampling) without interruption in a short gate time, and removes high-frequency components from the obtained count value sequence (filtering). Both time resolution and frequency resolution are greatly improved. Can be improved. The frequency counter of this system is composed of a counter circuit and a small arithmetic circuit, and has an advantage that multi-channeling is easy while suppressing an increase in circuit scale. Further, there is a feature that the resolution is improved as the sampling frequency is increased.

  A low pass filter is used to remove the high frequency components. For example, when a digital filter is used as the configuration of the low-pass filter unit, a memory and an arithmetic unit are required. By using a moving average filter as a low-pass filter, the amount of calculation can be greatly reduced, and high-precision real-time measurement is possible. The short gate count unit has a simple hardware configuration and is suitable for high-speed operation, but the filter unit requires multi-bit addition and subtraction, so the upper limit of the sampling frequency for real-time measurement is specified. It is mainly the processing capability of the filter part that does. If such a circuit is simplified, high-speed operation, real-time processing, and low power can be achieved.

  Therefore, the present invention provides a frequency measurement device that simplifies circuits such as a low-pass filter unit as much as possible in a frequency measurement device of a short gate time count method, and that enables high-speed circuit operation and low power consumption. Objective.

  Further, the present invention makes it possible to more easily configure the frequency measuring device when the signal under measurement is a binary level signal such as a pulse train signal or a bit stream signal (digital data output serially). It is to provide a frequency measuring device.

  In order to achieve the above object, one of the embodiments of the frequency measuring apparatus of the present invention is a short gate time counter that counts a pulse train signal at a predetermined sampling frequency and outputs a count value corresponding to the frequency of the pulse train signal. And a low-pass filter unit that filters the count value, the low-pass filter unit includes a first moving average filter, and a value obtained by dividing the sampling frequency by the number of taps of the first moving average filter is: It is set to be larger than the frequency change range of the pulse train signal.

  Here, “sampling frequency ÷ tap number of moving average filter” is defined as a dynamic range. If the frequency change of the signal under measurement is kept within the dynamic range, no carry (overflow) and no carry (underflow) occur in the output of the moving average filter.

  With this configuration, the signal flow can be converted into a bit stream from the input section of the counter to the output section of the first-stage moving average filter of the low-pass filter section. Can be configured easily. This makes it possible to simplify the circuit, increase the speed, and reduce power consumption.

  In the frequency measurement device, an operating point (more precisely, the following operating point parameter), which is a ratio of the frequency of the pulse train signal to be measured and the sampling frequency, is set as an operation setting parameter. It is desirable to select a value with a low pattern noise level in the output. As a result, pattern noise can be avoided and the SN ratio can be improved. The operating point parameter is defined as follows.

  Operating point parameter = measured frequency ÷ sampling frequency−Int (measured frequency ÷ sampling frequency) where Int (c) is a function that returns the integer part of c. From the definition formula, it can be seen that the value of the operating point parameter takes a value between 0 and 1. As will be described later, in the short gate time count method, generation of pattern noise is observed in the output. By appropriately selecting the operating point parameter, generation of pattern noise can be avoided or the level of pattern noise can be reduced.

  In the frequency measurement device, the binary signal sequence is further input, and the binary signal sequence is inverted and output, and the inverted / non-inverted adjustment unit is inverted / A determination circuit for giving a non-inversion instruction, wherein the counter value is output as a binary signal sequence and is input to the inversion / non-inversion adjustment unit, and the output of the inversion / non-inversion adjustment unit is the low-pass filter unit It is desirable to be input.

  When the frequency change of the pulse train signal to be measured is small, it is possible to more easily configure the short gate counter unit with a 1-bit counter. However, in this case, it is unclear whether the counted values “0” and “1” mean large or small (true value) or complement (or inversion). ) The meaning of the count value (true value) is determined by changing the frequency of the pulse train signal in one direction (frequency increasing direction or frequency decreasing direction) by the determining circuit and determining whether the count value has increased or decreased correspondingly. Or a complementary value) can be discriminated.

  It is desirable that the short gate time counter unit and the first-stage moving average filter include a latch circuit, a shift register circuit, and an exclusive OR circuit. The short gate time counter unit and the first stage moving average filter are configured by an equivalent simplified circuit (equivalent circuit). Thereby, circuit simplification, high speed, and low power consumption are achieved, which is preferable.

  It is desirable that the low-pass filter unit further includes a plurality of stages of moving average filters, and the plurality of stages of moving average filters are provided at a stage subsequent to the first moving average filter. Thereby, better low-pass filter characteristics can be obtained.

  It is desirable that an analog filter unit is further provided after the first stage moving average filter, and the plurality of stages of moving average filters are provided after the first moving average filter. Thereby, better low-pass filter characteristics can be obtained.

  It is desirable that the low-pass filter unit further includes an up-counter unit, and the up-counter unit is provided at a subsequent stage of the first moving average filter.

  Further, it is desirable that a shift register and an up / down counter are provided after the first stage moving average filter. The shift register and up / down counter function as a moving average filter, and the low-pass filter characteristics of the one-stage moving average filter are improved.

  The above-described frequency measuring apparatus uses a QCM (Quartz Crystal Microbalance) method using a crystal resonator to convert a small amount of mass change on the surface of the resonator substrate into a frequency change, such as a mass sensor. It is suitable for use in odor sensors, gas sensors, biosensors and the like.

  Embodiments of the present invention will be described below with reference to the drawings.

  In the frequency measurement device of the short gate time count system of the present invention, the signal flow from the input portion of the signal under measurement to the output portion of the one-stage moving average filter is bitstreamed (binary signal output string). In addition, parameters such as the measured signal frequency, sampling frequency, operating point, number of taps of the one-stage moving average filter, and the like are set so that carry or carry-down does not occur in the bit stream portion to be processed by the binary output circuit. Adjusted.

    (Example 1)

  First, the short gate time counting method described in the present application continuously counts a supplied pulse train signal with a short gate time to obtain a series of count values that behave like a pulse train corresponding to the frequency of the pulse train signal. The frequency change is extracted by obtaining a series of signals corresponding to the frequency of the pulse train signal supplied by removing high frequency components from the series of count values. The basics of such a short gate time counting method are described in detail in the above-mentioned Japanese Patent Application No. 2008-099721 for circuit configuration and operation. Japanese Patent Application No. 2008-099728 describes an example in which a 1-bit counter constitutes a short gate time count frequency measuring device.

  FIG. 1A is a block diagram illustrating an example in which a frequency measurement device is configured with a 1-bit (binary) output counter using the short gate time count method.

  As shown in the figure, a frequency measuring device is constituted by the short gate time counter unit 10, the low-pass filter unit 20, the inversion / non-inversion unit 80, and the like.

  The short gate time counter unit 10 counts the frequency of a signal under measurement (pulse train signal) supplied from a crystal oscillator of a QCM device (not shown) with a 1-bit output counter at a predetermined sampling period, and generates a bit stream (a series of 2 Value output). When the frequency change range of the signal source is known, it is possible to perform an operation in which no carry occurs in the 1-bit counter by appropriately setting the sampling frequency of the short gate counter unit 10. Under such conditions, a measurement result can be obtained with a 1-bit counter.

  As will be described later, for example, the simplified short gate time counter unit 10 includes a data latch that operates at a sampling frequency fs, a binary counter that outputs 1 bit, and a moving average filter that has m taps. Is done.

  The low pass filter unit 20 removes (filters) high frequency components from the count output of the bit stream signal output from the short gate time counter unit 10 and outputs a measurement value corresponding to the frequency change. The filtering process is a process of removing unnecessary information contained therein and extracting target information.

  As will be described later, the output of the 1-bit counter is such that the sequence of “0” and “1” corresponds to the magnitude of the count value (in the case of positive output), and the output value sequence is reversed (complement). (Complement output). For example, when the frequency of the signal under measurement is manually increased or decreased and the count value is increased or decreased correspondingly, it can be determined that the output value correctly corresponds to the input frequency. Further, when the frequency of the signal under measurement is increased or decreased and the count value is decreased or increased, it can be determined that the output value is a complement output.

  The inversion / non-inversion unit 80 relays the binary output of the short gate time counter unit 10 to the low-pass filter unit 20 as inversion or non-inversion based on the polarity determination result. As a result, a correct frequency count value can be obtained even with a frequency measurement device using a 1-bit counter.

FIG. 1B shows an example of a short gate time count type frequency measuring apparatus that automatically performs the above-described counter output complement determination / correction.
In the figure, parts corresponding to those in FIG. 1A are denoted by the same reference numerals, and description thereof is omitted.

  As described above, when sampling is performed by a binary counter with 1-bit output and a count value is output, whether the output of count values 0 and 1 corresponds to the magnitude of the count value in 1-bit information It is impossible to judge whether the relationship is complementary. Therefore, in this embodiment, a bit discrimination unit 70 is further provided. Other structures are similar to those in FIG.

The determination unit 70 is configured as a function executed by a control program in a computer system, for example. The determination unit 70 (more precisely, a computer) operates in response to the occurrence of a predetermined event. The determination unit 70 first increases / decreases the oscillation frequency of the signal source 10 using the up / down signal. When the output of the low-pass filter unit 20 increases or decreases correspondingly, it is determined that the outputs “0” and “1” of the counter unit 10 correspond to the magnitude of the count value. When the oscillation frequency of the signal source 10 is increased or decreased, and the output of the low-pass filter is increased or decreased correspondingly, the outputs of the counter unit 10 “0” and “1” have a complement relationship (the output is reversed). ) Is determined. In the case of a complement relationship, the determination unit 70 gives a complement determination signal to the inversion / non-inversion unit 80, inverts the outputs of “0” and “1” of the counter unit 10 to the low-pass filter unit 20. Relay.
Note that the output monitored by the determination unit 70 may be the output of the counter unit 10 or the output of the inversion / non-inversion unit 80 in addition to the output of the low-pass filter unit 20.

  Next, circuit simplification of a short gate time count frequency measuring apparatus using a 1-bit (binary) output counter will be described.

  2A to 2H show each stage of the circuit simplification process of the frequency measuring device. In the drawings, corresponding parts are denoted by the same reference numerals, and description thereof will be omitted.

  First, as shown in FIG. 2A, a basic short-gate time-count frequency measurement apparatus uses a signal to be measured (for example, a pulse train signal supplied from a crystal oscillator of a QCM device) at a predetermined sampling frequency. An n-bit output counter unit 10 that counts and a low-pass filter unit 20 that performs a filtering process for removing a high-frequency component from a continuous count value sequence output from the counter unit 10 and extracting a frequency change component are provided.

  In FIG. 5B, the short gate time counter unit 10 is composed of a 1-bit output counter. It is assumed that the frequency change range of the signal under measurement is known or has a sufficiently large change range with a margin (for example, a + 3b when the change range width is a and the range width variation is b). For example, some of the above-described crystal oscillators of the QCM device have a known frequency change range. For this reason, as will be described later, the sampling frequency is selected in advance (frequency change range <sampling frequency) so as not to cause a carry or a carry in the counting result. Under this condition, a 1-bit counter can be used as the short gate time counter unit 10. The low-pass filter unit 20 performs signal processing on the continuous binary output of the 1-bit counter 10.

  As shown in FIG. 3C, the 1-bit counter can be configured by, for example, a latch 11 that operates at a sampling frequency and a count calculation unit 12 that functions as a 1-bit counter. The 1-bit counter outputs “0” when “0” is input when the hold value is “0”, and outputs “0” when “1” is input when the hold value is “0”. When “0” is input when “1” and the holding value is “1”, the output is “1”, and when “1” is input when the holding value is “1”, the output is “0”. " The low-pass filter unit 20 can be configured by, for example, three-stage moving average filters 21 to 23.

  As shown in FIG. 4D, even if the first stage 21 of the three-stage moving average filters 21 to 23 of the low-pass filter section 20 is moved to the 1-bit counter section 10 side, the circuit is the same.

  As shown in FIG. 5E, the remaining low-pass filter unit 20 only needs to function as a low-pass filter. As will be described later, a digital filter or an analog filter only needs to have the required characteristics.

FIG. 3 shows a specific configuration example of the latch unit 11, the count value calculation unit 12, and the moving average filter 21 shown in FIGS. 2C to 2E. The 1-bit counter can be composed of one latch 11, one register z ⁻¹ and one exclusive OR circuit. The moving average filter 21 can be constituted by a 1-bit m-tap (m-stage) shift register z- ^m and an up / down counter.

  FIG. 2F illustrates an example in which the count value calculation unit 12 and the moving average filter 21 described above are simplified and configured with a count / filter unit 13 described later.

  Furthermore, as shown in FIG. 5G, when the counter unit 10 with 1-bit output is used (or when signal processing is performed with a bit stream of a binary signal), the output may be in a complement state. Therefore, the inversion / non-inversion unit 80 described above is provided at the subsequent stage of the count / filter unit 13 (corresponding to the output of the first-stage moving average filter), and the count output is inverted / non-inverted as appropriate. The operation of the inversion / non-inversion unit 80 is controlled by the determination unit 70 (see FIG. 1). In this way, a correct count value output can be maintained.

  FIG. 5H shows an example in which the inversion / non-inversion unit 80 is provided between the count value calculation unit 12 and the moving average filter unit 21. Although not shown, the inversion / non-inversion unit 80 may be provided at the subsequent stage of the low-pass filter unit 20. Thus, the inversion / non-inversion unit 80 can be arranged at a convenient position.

  FIG. 4A shows the moving average filter unit (up / down counter format) 21 shown in FIG. 3 by using an m-tap shift register, an exclusive OR circuit, a 1-tap shift register, and an exclusive OR circuit. A configured example is shown. In the case of a bitstream operation, increment and decrement have the same result, so the up / down counter is equivalent to exclusive OR.

Further, FIG. 5B shows the count value calculation unit 12 and the moving average filter unit 21 of FIG. 5A that are equivalent to the m-tap shift register z- ^m and an exclusive OR circuit. The example replaced with is shown.

  5 to 8 are diagrams for explaining that the logic circuit in FIG. 4A is equivalent to the logic circuit in FIG. As shown in FIG. 5 (A) and FIG. 5 (B), when the signals A (i) to J (i) of each part are set, as shown in FIG. 8, G (i) = A (i) + A ( i−n) = J (i).

  Using this result, as shown in FIG. 2 (F), a simplified count / filter circuit 13 (FIG. 4 (B)) having the same functions as those of the count calculation unit 12 and the moving average filter unit 21. Can be replaced.

  Next, parameters (dynamic range, operating point) to be selected in the short gate time count frequency measuring apparatus for processing the above-described bit stream (serial digital data) signal will be described. The dynamic range relates to the occurrence of a carry or a carry in the short gate time count type counter unit 10. The operating point is related to pattern noise generation and noise level.

  First, the condition under which no carry or carry occurs in the signal processing of the bit stream signal will be described.

  FIG. 9 shows, for example, a sampling frequency of 1 kHz, an operating point of around 0.283, and a first-stage moving average filter in the short gate time counter unit (1 bit counter + one-stage moving average filter) 10 shown in FIG. An output example (one-stage moving average filter) when the number of taps of the unit 21 is 100 is shown. As shown in the figure, when a signal under measurement having a relatively large frequency change (indicated by a thick solid line in the figure) is input, digit fluctuation occurs, and the output is as shown by the solid line in the figure. Multi-valued.

  The condition for causing such digit fluctuation is “change in signal frequency to be measured> dynamic range of first-stage moving average filter”. In this case, the dynamic range is expressed by “sampling frequency ÷ tap number of moving average filter”.

  When this is applied to the example of FIG. 9, the frequency change is about 25 Hz, the sampling frequency is 1 kHz, and the number of taps is 100. The dynamic range is 1 kHz / 100 = 10 Hz. Since the frequency change is about 25 Hz> the dynamic range is 10 Hz, the moving average filter output is multivalued.

  FIG. 10 shows an example where the frequency change of the signal under measurement is relatively small. The other conditions are the same as in FIG. The output of the moving average filter unit 21 is within a binary value. The condition in which such digit fluctuation does not occur is “frequency change of signal under measurement <dynamic range of one-stage moving average filter”. By satisfying this condition, the signal can be processed as a bit stream.

  When specifically applied, the frequency change is about 7 Hz. Since the frequency change is about 7 Hz <dynamic range 10 Hz, the above requirement is satisfied, and the output value of the moving average filter 21 can be kept in a binary value.

  FIG. 11 shows an example of dealing with bitstreaming by reducing the number of taps in the frequency change measurement of the signal under measurement of FIG. By reducing the number of taps of the moving average filter from 100 to 25, 1 kHz ÷ 25 = 40 Hz, and the dynamic range is increased from 10 Hz to 40 Hz to satisfy the above requirement.

  FIG. 12 shows an example of dealing with bitstreaming by increasing the sampling frequency in the frequency change measurement of the signal under measurement of FIG. The operation of the counter and the moving average filter is increased from 1 kHz to 3 kHz, 3 kHz ÷ 100 = 30 Hz, and the dynamic range is increased from 10 Hz to 30 Hz to satisfy the above requirement.

  As described above, in the short gate count method, digit change can be prevented from occurring by appropriately selecting a parameter related to the dynamic range. The measured signal frequency falls within the dynamic range, the count value becomes binary, and the information can be expressed as a bit stream.

  The parameters related to the dynamic range include the measured signal frequency, the sampling frequency fs, the number of taps m of the one-stage moving average filter 21, and the like.

  FIG. 13 shows an example of the operating point parameter dependence of the pattern noise intensity distribution in the short gate time counting method.

  As described above, the operating point parameter is defined as “measured frequency ÷ sampling frequency−Int (measured frequency ÷ sampling frequency). Here, Int (c) is a function that returns the integer part of c.

  It can be seen from the definition formula that the operating point parameter takes a value between 0 and 1. In the short gate time count method, pattern noise is generated in the output. The intensity of the pattern noise is a complex function of the operating point parameter and has symmetry with the operating point parameter of 0.5. That is, the pattern noise intensity at the operating point parameter 0.5-d has the property of being equal to the pattern noise intensity at the operating point parameter 0.5 + d (0 <d ≦ 0.5).

  Therefore, FIG. 13 shows the relationship between the noise intensity and the operating point in the range of operating point parameters 0 to 0.5.

As can be seen from the figure, when the operating point parameter is close to a simple rational value, a large pattern noise is generated. In the first-order ΔΣ modulation, there is an input value whose output generates a periodic sequence, and pattern noise generated when an input close to this is added is known, but this is the same analogy.

  However, the idea is different between the pattern noise avoidance method in the ΔΣ modulation and the pattern noise avoidance method in the short gate time count method. In the case of ΔΣ modulation, a high-order configuration or a multistage configuration is devised to suppress pattern noise itself. This is due to the fact that an AD converter using ΔΣ modulation handles an input signal change comparable to the dynamic range. In the case of the short gate time count method, it is possible to design the input signal change width to be within a certain range with respect to the dynamic range, so it is harmful to select the operating point range appropriately without changing the configuration. Pattern noise can be avoided.

  It can be seen that the S / N ratio can be improved by selecting parameters so that the operating point parameters are also appropriate when selecting the binarization conditions.

Next, with reference to FIG. 14 to FIG. 17, the inversion of the short gate count output of the short gate time counter method and the bit stream will be described.
To supplement.

  FIG. 14 is a graph for explaining the relationship between the sampling frequency, the moving average filter tap number, and the dynamic range when the short gate count output and the one-stage moving average filter output described above are handled as a bit stream.

  The horizontal axis of the illustrated graph is time (seconds), and the vertical axis is frequency shift (Hz). In the graph, when the gate time is 0.1 seconds (sampling frequency 10 Hz), the output of the short gate counter (pulse-like output indicated by a thin line between the lower limit value and the upper limit value of the sampling frequency), It shows the output of a moving average filter (5 taps) (pulse-shaped output indicated by a thick line) and the frequency to be measured (output of a moving average filter indicated by a curve in a pulse train). The same applies to FIGS. 15 to 17 below.

  As described above, the dynamic range is defined as “dynamic range = sampling frequency ÷ number of moving average filter taps”. In this example, the dynamic range is 2 (= 10 ÷ 5). If the frequency variation of the signal under measurement is within this dynamic range, the counter will not carry a carry and the counter output (single-stage moving average filter output) will be in the binary output state and the bit stream output will be Become. This can be realized by selecting the sampling frequency and the number of taps of the moving average filter with respect to the frequency of the signal under measurement. By using the signal of the part of the short gate time counter and the one-stage moving average filter as a bit stream, the circuit configuration of the part can be simplified by a logic gate as described above. Subsequent circuits can be processed with a digital (binary) circuit, which can be simplified.

  FIGS. 15 to 17 illustrate another procedure for determining whether the binary output of the counter is a complement.

  First, FIG. 15 shows an example of the short gate count value and the moving average filter output value (when the count value and the moving average value are treated as integers).

  For example, when a signal under measurement changing between 120 Hz and 130 Hz is measured with a gate time of 0.1 second (sampling frequency 10 Hz), the short gate count value is 12 or 13. The moving average is calculated by dividing the sum of the count values in the section by the number of taps, but if scaling is not considered, it may not be divided by the number of taps. When the number of taps is 5, any one of values 60 to 65 is output as the moving average value.

  FIG. 16 shows an example of the short gate count value and the moving average filter output value (when the count value and the moving average value are handled as a bit stream). When it is handled as a bit stream, it is replaced with a binary value. That is, “13” → “1”, “12” → “0”, “65” → “1”, “64” → “0”,..., “60” shown on the right side of the graph of FIG. → Replaced with “0”.

  FIG. 17 shows an example of the moving average filter output value (when the count value and the moving average value are handled as a bit stream). On the right side of the graph of the same figure, “OK”, “complement”, “OK” are shown in each range of the moving average filter output value corresponding to “1”, “0”,..., “0” in FIG. ... “OK” is described.

  15 is compared with FIG. 17, whether the magnitude relationship of the moving average filter output value corresponds to the increase / decrease relationship of the measured frequency, depending on which range the measured frequency (right column in FIG. 15) falls within. , It can be seen whether there is a complement relationship (right column in FIG. 17).

    (Example 2)

  FIG. 18 shows another configuration example of the low-pass filter unit 20. In this example, an analog level output is obtained by connecting a known analog low-pass filter downstream of the count / filter unit (function of 1-bit counter + moving average filter) 13.

  FIG. 19 shows an output example of the analog filter when the apparatus operation parameters are set to a sampling frequency of 3 kHz and an operating point parameter of around 0.336. There is distortion compared to the signal under measurement.

  FIG. 20 shows an output example of the analog filter when the operating point parameter is around 0.283 and the other conditions are the same as those in FIG. The same output as the signal under measurement is obtained. Comparing FIG. 19 and FIG. 20, it can be seen that the SN ratio varies depending on the operating point parameter.

  Consider the advantages of a hybrid filter using a digital filter (for example, moving average filter 21) and an analog filter as shown in FIG.

  When the filter processing is performed digitally, a high signal-to-noise ratio can be ensured without deterioration of information, but a memory for holding information necessary for calculation is required.

  In the case of an analog filter, there is a merit that the circuit can be simplified because the memory part necessary for the digital filter can be omitted. However, when a high sampling frequency is used, a signal that varies greatly with the amount of change in the signal under measurement is handled. For this reason, there are cases where it is necessary to devise countermeasures for nonlinear distortion, and the circuit for correcting this becomes complicated. Moreover, if the signal change is small with respect to the dynamic range, it is essentially difficult to ensure a high S / N ratio.

  The hybrid filter is configured to input the output of the digital filter to the analog filter. In this case, the signal that changes greatly at 2 levels is converted to a smaller step size by the digital filter (here, moving average filter), so (1) the design of the analog filter becomes easy, and (2) a high S / N ratio is secured. (3) Since the digital filter does not require high performance, the configuration of the digital filter unit is easy.

    (Example 3)

FIG. 21 shows a two-stage moving average in which a second-stage moving average filter using an m-tap shift register z- ^m and an up / down counter is provided after the first-stage moving average filter 21 (count / filter circuit 13). An example in which a digital output is obtained with a filter configuration is shown. A signal is transmitted as a bit stream up to the up / down counter, and an up / down counter outputs a plurality of bits. The digital output is Int (log ₂ m + 1) bits.

  FIG. 22 shows an output example of the digital filter when the sampling frequency is 3 kHz, the operating point parameter is 0.336, and the number of taps of the two-stage moving average filter is 200. It can be seen that the noise is larger than the signal under measurement.

  FIG. 23 shows an output example of the digital filter when the operating point parameter is 0.283 and the other conditions are the same. It can be seen that the noise is reduced. Thus, it can be seen that the SN ratio varies depending on the selection of the operating point parameter.

  As described above, in the embodiment of the present invention, since the configuration of the bit stream converted short gate count unit (1 bit counter) +1 stage moving average filter unit is used, In comparison, the circuit can be simplified, and high-speed driving is possible. Measurement resolution is improved and power consumption can be suppressed.

  In addition, the configuration of the bit gate converted short gate count unit + 1 stage moving average filter unit is simplified by an equivalent circuit, the circuit area is reduced, and the power consumption is reduced.

  Also, in the configuration of the short gate count unit + 1 stage moving average filter unit, the output can be made binary output by appropriately selecting the sampling frequency and the number of taps, and the signal in the configuration can be converted into a bit stream. it can. In addition, by appropriately selecting the operating point parameter, it is possible to reduce the influence of pattern noise when bitstreaming is performed.

  Further, by adopting the configuration of the short gate count unit + 1 stage moving average filter unit + analog filter unit, a high resolution analog output can be obtained with a simple configuration.

  Further, by adopting a configuration of a short gate count unit + 1 stage moving average filter unit + up / down counter, a 2-stage moving average filter output (digital output) can be obtained with a simple configuration.

  Since the frequency measuring apparatus described above has a small circuit scale and can be easily mounted, the apparatus can be reduced in size, increased in accuracy, reduced in weight, and reduced in cost. For example, it is suitable for reducing the size and increasing the resolution of various sensors using quartz. It is suitable for integration and platformization of various sensors using quartz. It is suitable for use in odor sensors, gas sensors, biosensor transducer arrays, QCM devices, and the like.

It is a block diagram explaining the example of the frequency measuring apparatus of the short gate time count system provided with the circuit which inverts / non-inverts the output of the short gate time counter of 1 bit output. It is explanatory drawing explaining the circuit simplification of a short gate time counter. It is a block diagram explaining the structural example of 1 bit counter of a bit stream structure, and a moving average filter. It is a block diagram explaining the equivalent circuitization of 1 bit short gate counter + one-stage moving average filter. It is a block diagram explaining the equivalent circuitization of 1 bit short gate counter + one-stage moving average filter. It is a block diagram explaining the equivalent circuitization of 1 bit short gate counter + one-stage moving average filter. It is a block diagram explaining the equivalent circuitization of 1 bit short gate counter + one-stage moving average filter. It is a block diagram explaining the equivalent circuitization of 1 bit short gate counter + one-stage moving average filter. It is a graph which shows the output example (example of large frequency change) of a short gate counter + 1 step | paragraph moving average filter. It is a graph which shows the output example (example with a small frequency change) of a short gate counter + 1 step | paragraph moving average filter. It is a graph which shows the output example (tap number adjustment example) of a short gate counter + 1 step moving average filter. It is a graph which shows the output example (example of sampling frequency number adjustment) of a short gate counter + 1 step | paragraph moving average filter. It is a figure explaining pattern noise intensity-operating point parameter characteristic. It is a figure explaining the dynamic range in a 1 step moving average filter output. It is a figure explaining a response | compatibility with the output range and count value of a one-stage moving average filter. It is a figure explaining the correspondence of the complement in a one-stage moving average filter output. It is a figure explaining the correspondence of the complement in a one-stage moving average filter output. It is a block diagram explaining the example of a short gate counter + 1 step moving average filter + analog filter structure. It is a graph which shows the output example (operating point 0.336) of a short gate counter + 1 step moving average filter + analog filter. It is a graph which shows the output example (example of operating point adjustment) of a short gate counter + 1 step moving average filter + analog filter. It is a block diagram explaining the example of a short gate counter + 2 step | paragraph moving average filter structure. It is a block diagram explaining the output example (operating point parameter 0.336) of a short gate counter + 2 stage moving average filter. It is a block diagram explaining the output example (operation point parameter adjustment example) of a short gate counter + 2 stage moving average filter.

Explanation of symbols

10 short gate time counter unit, 20 low-pass filter unit, 50 up counter unit, 70 determination unit, 80 inversion non-inversion unit

Claims (6)

A short gate time counter that counts a pulse train signal at a predetermined sampling frequency and outputs a count value corresponding to the frequency of the pulse train signal;
A low-pass filter for filtering the count value;
With
The low-pass filter unit includes a first moving average filter;
A frequency measurement device, wherein a value obtained by dividing the sampling frequency by the number of taps of the first moving average filter is set to be larger than a frequency change range of the pulse train signal. As a parameter for setting the operation of the frequency measuring device,
The frequency measuring device according to claim 1, wherein a value of measured frequency ÷ sampling frequency−Int (measured frequency ÷ sampling frequency) (where Int (c) is a function that returns an integer part of c). Furthermore,
An inversion / non-inversion adjustment unit that takes a binary signal sequence as input and can invert and output the binary signal sequence;
A determination circuit that gives an inversion / non-inversion instruction to the inversion / non-inversion adjustment unit,
The counter value is output as a sequence of binary signals and is input to the inversion / non-inversion adjustment unit.
The frequency measurement device according to claim 1, wherein an output of the inversion / non-inversion adjustment unit is an input of the low-pass filter unit. The low-pass filter unit further includes a plurality of stages of moving average filters,
4. The frequency measurement device according to claim 1, wherein the plurality of stages of moving average filters are provided after the first moving average filter. 5. The low-pass filter unit further includes an analog filter,
4. The frequency measurement device according to claim 1, wherein the plurality of stages of moving average filters are provided at a stage subsequent to the first moving average filter. 5. The low-pass filter unit further includes an up counter unit,
4. The frequency measurement device according to claim 1, wherein the up-counter unit is provided at a subsequent stage of the first moving average filter. 5.

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