JPH03233369A - Frequency detector - Google Patents

Abstract

PURPOSE:To detect a frequency without the effect of offset amount by providing a comparator to compare the signal outputted from a subtracting device with a reference value and to convert it to a rectangular wave consisting of two level values. CONSTITUTION:By a phase difference branching filter 2 furnished with phase shifters 4 and 6, an inputted digital signal (a) is divided to signals K and I having the phase difference of 90 deg. and sent out to the subtracting device 8. By the subtracting device 8, the signal I is subtracted from the signal K and a signal (m) is sent out. Next, the signal (m) is compared with zero volt by the comparator 10 and converted to the rectangular wave consisting of two level values. That is, when the signal (m) is higher than zero volt, it is sent out to an edge counter 12 as a signal (n) of the rectangular wave of +1, and the rectangular wave of -1 when the signal (m) is less than zero volt. After a reset signal is inputted, the edge of signal (n) is counted for one second by the edge counter 12 to send out the counted value to a dividing device 16 as a signal 0. The frequency of signal (a) obtained by dividing the counted value of signal 0 by 2 is outputted by the dividing device 16 as a signal P.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency detector, and more particularly to a frequency detector using digital signal processing.

[Conventional technology]

FIG. 5 shows the configuration of a first conventional frequency detector. In the frequency detector with this configuration, when the digital signal a whose frequency is to be detected is input, it is input to the comparator 40 which outputs +1 if the input signal is O port or more, and -1 if it is less than 0 volts, Once output, the output C of the delay device 42 which delays the output of the comparator 40 by the sampling interval and outputs the result is input to the multiplier 44, and the edges of the output d are counted by the edge counter 46. The output e is input to the divider 48, and the input signal e
When divided by 2, the division result f is output. By performing the above operation within one second after the edge counter reset signal RST is input, the output f is obtained as the frequency of the input digital signal a.

FIG. 6 shows the configuration of a second conventional frequency detector. In a frequency detector with this configuration, when a digital signal a whose frequency is to be detected is input, the input is first set to 0.
Input g to a comparator 50 which outputs 1 if the voltage is greater than or equal to 0 volts, and O if it is less than O volts. The output j is input to the exclusive OR circuit 54 which outputs the exclusive OR of two inputs, and the rising edge of the output i is counted for 1 second by the edge counter 56, so that the output j becomes the input digital signal a.
is obtained as the frequency of

[Problem to be solved by the invention]

Both the first and second conventional frequency detectors described above detect the frequency by counting the zero-crossing points of the input signal, so if there is no offset for the input signal as shown in FIG. 7(A), the frequency can be detected without any problem. However, if the input signal has a large offset amount and there is no zero cross point, as shown in FIG. 7(B), it cannot be counted, and therefore the frequency cannot be detected.

An object of the present invention is to eliminate such drawbacks and provide a frequency detector that can detect frequencies without being affected by the amount of offset.

[Means to solve the problem]

The frequency detector of the first invention includes: a phase difference duplexer that divides an input signal whose frequency is to be detected into one signal and the other signal having a phase difference; a subtracter for subtracting and forming a signal unaffected by the offset of the input signal; and comparing the signal output from the subtracter with a reference value;
It has a comparator that converts it into a rectangular wave consisting of two level values, and a counter that detects the frequency of the input signal by counting the edges of the rectangular wave for a certain period of time.

The frequency detector of the second invention includes: a local maximum value detector that detects a local maximum value of an input signal whose frequency is to be detected; a local minimum value detector which detects a local minimum value of an input signal whose frequency is to be detected; an adder that adds the output of the maximum value detector and the output of the minimum value detector; a divider that divides the output of the adder by 2 to obtain an offset amount of the input signal; and a divider that calculates the offset amount of the input signal. A comparator to compare with the input signal as a threshold value, a delay device to which the output signal of the comparator is input, and an exclusive OR to take an exclusive OR of the output signal of the comparator and the output signal of the delay device. and a counter that detects the frequency of the input signal by counting the edges of the output signal of the exclusive OR circuit for a certain period of time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the first invention.

This frequency detector includes a phase difference converter 2, a subtracter 8,
Comparator 10, edge counter 12, and divider 1
It consists of 6.

The phase difference converter 2 includes a phase shifter 4 and a phase shifter 6, and divides the input digital signal a into a signal with a phase difference of 90'' and a signal l, and sends the divided signals to a subtracter 8.

Subtractor 8 subtracts signal 1 from signal k and sends out signal m.

The comparator 10 compares the signal m with O volts, and outputs a rectangular wave signal n of +1 if the signal m is O volts or more and -1 if it is less than 0 volts to the edge counter 1.
Send to 2.

After inputting the reset signal R3T, the edge counter 12
The edges of the signal n are counted for one second, and the count value is sent to the divider 16 as a signal 0.

The divider 16 divides the count value of the signal O by 2 and outputs the resulting frequency value of the signal a as the signal p.

Next, the operation of this embodiment will be explained with reference to the waveform diagram of FIG. 2. 2(A) is the output signal k of the phase shifter 4, (B) is the output signal l of the phase shifter 6, and (C) is the output signal of the subtracter 8.
output signal m, (D) is the output signal n of the comparator 10
It shows.

It is assumed that the input signal a whose frequency is to be measured is expressed as Ya = As in (ωt) + a:. However, α is the offset amount.

The signal a is input to the phase difference waveform filter 2, and the phase shifter 4 shifts the phase by φ5, the phase shifter 6 shifts the phase by the phase (φ1+π/2),
It is divided into two signals with a phase difference of 90° and a signal l. In these signals, 1 is expressed by the following equation.

Yk=As in (ωt+φ1)+αYL=As
in (ωt+φ++π/2)+α=Acos(ωt+
φ1)+α FIG. 2(A) shows the signal k, and FIG. 2(B) shows the signal 1. These signals include an offset amount α.

The signal l is input to a subtracter 8, and the subtracter 8 subtracts the signal l from the signal k. In other words, the signal m is Y, = Yk - Yt = Asin (ωt + φ,) + α - Acos (ωt + φ1) - α = As in (ωt + φ,) - Acos (ωt
+φI)=11/TAsin (ωL+φ1+φ2). The offset amount α is eliminated by the subtraction, and the signal m becomes a signal that is not affected by the offset amount α. This signal m is shown in FIG. 2(C).

Signal m is input to comparator 10, and comparator 1
0 is a square wave signal n in which a signal of 0 volts or more is +1.0 volts or less is -1, and the edge counter 12
Send to. Figure 2 (D) shows this signal n.
It is. As is clear, the frequency of this rectangular wave signal n is equal to the frequency of the input signal a.

This signal n is input to edge counter I2.

The edge counter 12 receives a reset signal R3T every second.
is input, so the edge counter 12 counts the edges of the square wave signal n for 1 second after being reset,
The count value is input to the divider 16 as a signal O.

The divider 16 divides the count value signal O by 2 and outputs the division result as a signal p. The signal p is the input signal a
represents the frequency value of

As explained above, the frequency detector of this embodiment inputs the input digital signal to the phase difference waver, subtracts one output signal from the other output signal using the subtracter, and outputs the output signal from the comparator. The frequency is detected by converting it into a rectangular wave, counting the edges of the rectangular wave with an edge counter, and dividing by 1/2.

Although the divider 16 is used in this embodiment, the edge counter and divider can be replaced with a rising edge counter or a falling edge counter.

FIG. 3 is a circuit block diagram showing an embodiment of the second invention.

This frequency detector includes a local maximum value detector 20, a local minimum value detector 22, a two-input adder 24, a divider 26, an offset control circuit 28, a comparator 30, and a delay device 32.
, an exclusive OR circuit 34, an edge counter 36,
It is composed of an AND circuit 38.

This frequency detector detects the maximum value and minimum value of the input digital signal, adds these values, divides by 2, uses the obtained result as the offset amount of the input digital signal, and calculates the offset amount of the input digital signal and the value of the offset amount. The frequency is detected by counting the cross points with the input digital signal, and the offset amount is updated by repeating the detection cycle every cycle of the input digital signal.
The structure is such that the frequency is detected according to fluctuations in the amount of offset of the input digital signal.

Each component will be explained below.

The maximum value detector 20 outputs the input value if the input value of the input signal a is equal to or greater than the output value at that time, otherwise holds the output value, and inputs it unconditionally at the falling edge of the initialization signal INIT. Output the value.

The minimum value detector 22 outputs the input value if the input value of the input signal a is less than the output value at that time, otherwise holds the output value and outputs the input value unconditionally at the falling edge of the initialization signal INIT. do.

The adder 24 adds the output signal q of the maximum value detector 20 and the output signal r of the minimum value detector 22, and outputs the result as a signal S.

The divider 26 divides the input value by 2 and outputs the result as a signal t. This signal t represents the amount of offset of the input signal a.

The offset control circuit 5 takes in and outputs the input signal t at the falling edge of the input signal CLK, holds the output at other times than the falling edge of the input signal CLK, and also outputs the input signal t when the input signal CLK falls.
When O is input to T, the input signal t is output as is unconditionally. The output signal U of the offset control circuit is supplied to a comparator 30 as a threshold value.

The comparator 30 outputs 1 as a signal V if the value of the input signal is greater than or equal to the value of the threshold input, and outputs O if it is smaller than the value of the threshold input.

The delay device 7 delays the output signal V of the comparator 30 by a sampling interval, and applies it as a signal W to the exclusive OR circuit 34 .

The exclusive OR circuit 34 performs an exclusive OR on the signal V and the signal W, and adds the output signal X to the edge counter 36.

The edge counter 36 counts up at the rising edge of the input signal X, outputs the counted number, and resets the counted number to 0 when O is input to the initialization signal INIT.

The AND circuit 38 performs a logical product of the initialize INIT signal and the output signal V of the comparator 30 and provides an initialize signal INIT for the maximum value detector 20 and the minimum value detector 22.

In the circuit with this configuration, the digital signal a is sent to the maximum value detector 20. It is input to a minimum value detector 22 and a comparator 30. Local maximum value detector 20 and local minimum value detector 22
The respective outputs q and r are added in an adder 24, and the output S is divided by 2 in a divider 26, and the obtained offset measurement is input to the offset control circuit 28. Here, the output V of the comparator 30 is input to the input signal CLK of the offset control circuit 28 and one of the two inputs of the AND circuit 38, and the initialization signal INIT is input to the other of the two inputs of the AND circuit 38. . Further, this initialization signal INIT is input to the INIT terminal of the offset control circuit 28, and the output of the AND circuit 38 is input to the local maximum value detector 20.
and input to each INIT terminal of the minimum value detector 22. Therefore, when the output signal V of the comparator 30 falls, the input signal t of the offset control circuit 28 is captured and output as the signal U, and the output signal V of the comparator 30
At times other than the falling edge of , the output U is held. At the same time, when the output signal V of the comparator 30 falls, each input a of the maximum value detector 20 and the minimum value detector 22 is unconditionally output as is, and a new cycle of maximum and minimum value detection begins. In this way, the output U from the offset control circuit 28 to the comparator 30 is updated every cycle of the input digital signal a by feedback of the output (2) of the comparator 30.

On the other hand, the digital signal a input to the comparator 30 is compared using the output U of the offset control circuit 28 as a threshold value, and the output V and the output W obtained by inputting the output V to the delay device 32 are exclusively OR circuit 34
The rising edge of the output X is counted by the rising edge counter 36 to obtain the count number y. Note that this rising edge counter is reset to count number 0 by inputting the initialization signal INIT.

FIG. 4 shows the results of functional simulation using the above configuration.

After inputting the initialization signal INIT,
By performing this for a certain period of time, an output y is obtained as the frequency of the input digital signal a.

As explained above, the frequency detector of this embodiment uses an external digital signal for frequency detection and an AND circuit 3.
A local maximum value detector 20 and a local minimum value detector 22 to which the output of 8 is input, an adder 24 to which the output of the local maximum value detector and the output of the local minimum value detector are input, and an adder 24 to which the output of the adder 24 is input. an offset control circuit 28 to which the output of the divider 26, an external initialization signal, and the output of the comparator 30 are input, and a comparator 3 to which the digital signal and the output of the offset control circuit 28 are input.
0, an AND circuit 38 to which the initialization signal and the output of the comparator 30 are input, a delay circuit 32 to which the output of the comparator 30 is input, and an exclusive circuit to which the output of the comparator 30 and the output of the delay circuit 32 are input. OR circuit 3
4, the initialization signal and the exclusive OR circuit 34
The rising edge counter 36 receives the output of the rising edge counter 36.

In other words, the frequency detector of this embodiment calculates the maximum and minimum values of the input digital signal whose frequency is to be determined, adds these values using an adder, divides the result by 2 using a divider, and calculates the input signal by dividing the result by 2 using a divider. Find the offset amount of the digital signal,
Input this to the offset control circuit, and in order to output this output to the comparator, the output of the comparator is fed back to the offset control circuit, and at the falling edge, it is output to the comparator as a threshold value, and the maximum value/minimum value detector By having a configuration in which the output of the comparator is fed back and a new detection cycle is entered, the offset value is updated every cycle of the input digital signal to a threshold value that corresponds to fluctuations in the amount of offset of the input digital signal. It has a configuration that detects frequency without being affected by fluctuations in quantity.

According to the frequency detector having such a configuration, the frequency of the input digital signal can be detected without being affected by the amount of offset of the input digital signal and its temporal fluctuation.

〔Effect of the invention〕

As explained above, the present invention has the effect of being able to detect the frequency of an input signal without being affected by the offset amount of the input signal.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the first invention, FIG. 2 is a diagram showing waveforms of each part of the circuit in FIG. 1, and FIG. 3 is an embodiment of the second invention. 4 is a diagram showing the functional simulation results using the configuration shown in FIG. 3, FIG. 5 is a circuit block diagram of the first conventional example, and FIG.
FIG. 7, a circuit block diagram of the second conventional example, is a diagram showing an example of an input signal without an offset and an example of an input signal with an offset. 2... Phase difference waveform generator 8... Subtractor 10... Comparator 12... Edge counter 16... Divider 20... Maximum value detection unit 22... Minimum value detector 24... 2-input adder 26... Divider 28... Offset control circuit 30... Comparator 32...・Delay unit 34...Exclusive OR circuit 36...Rising edge counter 38...AND circuit

Claims (2)

[Claims] (1) A phase difference duplexer that divides an input signal whose frequency is to be detected into one signal and the other signal having a phase difference, and subtracts the other signal from the one signal, and A subtracter that forms a signal that is not affected by offset, and a signal output from this subtracter that is compared with a reference value,
A frequency detector comprising: a comparator that converts the signal into a rectangular wave consisting of two level values; and a counter that detects the frequency of the input signal by counting edges of the rectangular wave for a certain period of time. (2) a local maximum value detector that detects the local maximum value of the input signal whose frequency is to be detected; a local minimum value detector that detects the local minimum value of the input signal whose frequency is to be detected; and an output of the local maximum value detector. and the output of the minimum value detector; a divider that divides the output of the adder by 2 to obtain an offset amount of the input signal; a comparator for comparing the output signal of the comparator, a delay device to which the output signal of the comparator is input, an exclusive OR circuit that takes an exclusive OR of the output signal of the comparator and the output signal of the delay device, and this exclusive logic A frequency detector comprising: a counter that detects the frequency of the input signal by counting edges of the output signal of the summation circuit for a certain period of time.