RU1812518C - Device for analysis of signals in real-time scale - Google Patents

Abstract

The invention relates to the field of measurement technology and can be used to measure the amplitudes of the harmonic components in the signals under study. SUMMARY OF THE INVENTION: the device comprises a variable-frequency clock generator 1, a read-only memory unit 2, a phase shift unit 6, an address generation counter 7, a counter 9 cycles, an analog-to-digital multiplier 10, an analog integrator 13 with a reset, an allocation unit 14 the absolute value of the signal, the amplitude detector 15, bus 3, 4, 5, inverter 8. pulse shaper 11, the element OR 12. 3 ill.

Description

The invention relates to the field of measurement technology and can be used to measure the magnitudes of the amplitudes of the harmonic components in the signals under study at given frequencies.

The purpose of the invention is to increase speed.

In FIG. 1 shows a functional diagram of a device; in FIG. 2 is a diagram of a phase shift block; in FIG. 3 - the block selection of the absolute value of the signal ..

The device (Fig. 1) comprises a variable frequency clock generator 1, a read-only memory unit 2, an initial state setting bus 3, an input and output bus 4 and 5, a phase shift unit 6, an address generation counter 7, an inverter 8, 9 cycle counter, analog-to-digital multiplier 10, implemented, for example, on the basis of a multiplier digital-to-analog converter, pulse shaper 11, OR element 12, analog integrator 13 with reset, absolute signal value extraction unit 14, amplitude detector 15, the output being 15 generator 1 t of variable frequency pulses is connected to the signal input of the phase shift unit b, the output of which is connected to the counting input of the address forming counter 7, all of whose outputs, where g is the bit of the address forming counter, are connected respectively to the inputs of the memory unit 2, and the output of the high order is also connected to the input of the inverter 8, the output of which is connected to the counting input of the counter 9 cycles, the output of the high order of which is connected to the input of the pulse shaper 11 and to the first installation input block 6 phase shifts / outputs of the memory block 2 are connected to the digital inputs of the analog-to-digital multiplier 10. the output of which is connected to the signal input of the analog integrator 13 with a reset, the output of the pulse shaper is connected to the first input of the element OR 12, the output of which is connected to the reset input an analog integrator 13, the output of which is connected to the input of the absolute value extraction unit 14, the output of which is connected to the signal input of the amplitude detector 15, the initial setting condition bus 3 is connected to the second tanovochnomu entry unit 6 phase shift, - the Setup Valid counter 9 cycles of the Setup Valid pulse shaper 11 and to the second input of the OR gate 12, the input bus 4 is connected to the analog input of analog to digital multiplier 10, and output bus

5 is connected to the output of the amplitude detector 15.

An adjustable frequency clock generator 1 is a rectangular pulse generator of any known design with a frequency f adjustable in a given frequency range f 1 S f f2. The storage unit 2 is intended for digital storage and sequential reproduction of the values of the function y (t) sln ("t + /)} over a period T 0 TS 2 l; where is the cyclic frequency, equal to 2 tg / T, t is the current time, (p-phase. This block has n inputs, m outputs and the capacity of m-bit binary words. Phase shift block 6 is designed for sequential change phase of the sinusoidal signal y (t) generated by block 2. The phase of the sinusoidal signal y (t} sln (fut + j) varies with the step DN in the range from p 0 to p 2Ј,

A possible design of block 6 (Fig. 2) contains the first and second two-input

elements And 16 and 17, binary counter direct count 18, two-input element OR 19, trigger 20, switched on the trailing edge of the pulses (on the edge of 1-0) received at its counter input, and the first input of the first element And 16 is the signal input of the phase shift unit and is connected to the output of the device 1 clock pulses of the device, and it is also connected to the first input of the second element And 17,

the output of which is connected to the counter input of the counter 18, the high-order bit of which is connected to the first input of the two-input element OR 19, the output of which is connected to the even input of the trigger 20, zero output

of which Q is connected to the second input of the first element And 16, and a single output Q is connected to the second input of the second element And 17, the second input of the OR element 19 is the first installation input of block 6

phase shift, the installation input of the trigger 20 to the zero state is connected to the installation input of the counter 18 to the initial zero state and is the second installation input of the block 6 phase shift and connected to

the initial state setting bus 3. Counter 7 is a forward counter binary counter, switched at the leading edge of the pulses arriving at its counter input, and has a number of binary bits. The inverter 8 is designed to invert pulses from the high order of the counter 7 to the counter input of the counter 9 to ensure that the counter 9 switches at the moment the counter 7 goes to zero. Inverter 8

implemented, for example, on the basis of a two-input 2I-NOT circuit with combined inputs. Counter 9 is a direct counter binary counter, switched on the leading edge of the pulses arriving at its counter input, and has P2 binary bits. The analog-to-digital multiplier 10 is implemented on the basis of a multiplying DAC; the pulse shaper 11 is used to generate the setting pulses at the moment the counter 9 goes to the zero state, resetting the integrator 13 to the zero state.

The pulse shaper 11 is implemented either on the basis of a standby multivibrator with a closed input, or it contains (Fig. 3) a two-input element OR 21, a trigger 22, switched by the trailing edge of the pulses (over the difference 1-0) received at its counter input, and a delay line 23, the first input of the two-input element OR 21 is the signal input of the pulse shaper 11 and connected to the high order of the counter 9 .., the output of the two-input element OR 21 is connected to the counting input of the trigger 22, the single output of the trigger 22 is connected to the input delay 23, and also is the output of the pulse shaper, the output of the delay line 23 is connected to the second input of the two-input element OR 21, and the installation input of the trigger 22 to the initial zero state is the installation input of the pulse shaper 11 and connected to the bus 3 setting the initial state neither. The analog integrator 13 with a reset, the absolute signal separation unit 14, the amplitude detector 15 are analog blocks and are implemented according to one of the known schemes.

The device operates as follows.

To measure the amplitude of the sinusoidal component of the studied signal x (t) at the frequency F (at the cyclic frequency (V 2 p F) supplied to the device via the input bus 4, the clock generator 1 is tuned to the frequency f

F-2n1, where m is the bit of the counter 7 of the formation of the address, to ensure that the block 2 generates a constant memory of a sinusoidal signal with the same cyclic frequency w 2 l F. Then, a setting pulse is sent to the initial state bus 3, setting the initial state zero state counter 18 and trigger 20 in the phase shift unit b, address generation counter 7, cycle counter 9, trigger 22 in the pulse former 11.

an analog integrator 13 with a reset and an amplitude detector 15. Next, the clock generator 1 is turned on. The first 2P1 pulses pass through block b

5 phase shift seamlessly. In this case, the counter 7 for generating the address generates a complete set of addresses from 00 ... 0 to 11 ... 1, from which the digital values of the sinusoidal signal are read out sequentially from the block 2 of constant memory over the entire period T 0.2 L. Those.

2n2 periods of a sinusoidal signal are generated in digital form with a frequency of F f / 2n1 or with a cyclic frequency (o-f / 2n12 p. After passing through the first group of 2n1 2n1 pulses, both counters 7 and 9 are reset to their initial zero state. the moment the counter 9 cycles to zero, on the edge (edge) of the pulse from the high-order bit of the counter 9 cycles to the counting input of the trigger 20, the trigger 20 is set to

5, the single state and 2 SC of pulses from the generator 1 clock pulses are fed to the counter input of the counter 18, and the last of the 2 SC of pulses, the counter is transferred to the zero state and the pulse from the highest bit of the counter goes through the OR element 19 to the counting input of the trigger 20, setting it to initial zero

state, and the next 2n1. pulses arrive at the counting input of the counter 7 for changing the address, which, at the moment of their arrival, like the counter 9 of the cycles, is in the zero state. The delay of each of the groups of 2 SC impulses provides a sequential shift of the 0 phase of the generated sinusoidal signals by the block 2 of constant memory on D)

2lg / 2p12 3. The digital sinusoidal signal generated by the read-only memory unit 2 on the analog-to-digital multiplier 5 is multiplied with the analyzed analog-- signal x (t), and their product for

of each series of sine periods is integrated by an analog integrator 13 cq reset, which is reset to the original

-P

the state after the generation of 2 periods of a sinusoidal signal using the 11 pulse generator, which generates a pulse at the moment of transition of the 5 counter of 9 cycles to the zero state - at the moment the high-order bit of the counter of 9 cycles switches from one to the zero state, the trigger 22 and the pulse former switches to single state 0

This gives rise to a high potential, which resets the analog integrator with a reset to the zero state and which, after passing through the delay line 23 and the OR element 21, resets the trigger 22 to its initial zero state. The maximum absolute value of the calculated integrals modulo calculated using block 1 for extracting the absolute value of the signal) is detected by the amplitude detector 15. This value is the desired value proportional, accurate to a constant, to the amplitude of the sinusoidal component of the signal x (t) at frequency F calculated according to the known

by the formula A (F) max I / x (t) sln (2 jfFi + 0dt

t-at

when selecting the value of p. The frequency setting of the clock generator 1 for measuring the amplitudes of the sinusoidal components of the analyzed signal at predetermined frequencies can be done either manually or using a microcomputer.

The bandwidth of the analyzed signals when using the proposed device is the same as the bandwidth of the sinusoidal signal reproduced by the read-only memory unit 2.

Claims (1)

SUMMARY OF THE INVENTION A real-time signal analysis apparatus comprising a generator. adjustable frequency clock pulses, constant block memory connected in series cycle counter, pulse shaper and OR element, initial setup bus conditions, input and output buses, in that, in order to improve performance, a series-connected phase shift unit, an address generation counter and an inverter, a series-connected analog-to-digital multiplier, an analog integrator with a reset, and an absolute value extraction unit are introduced into it and an amplitude detector, the output of which is connected to the output bus, and the second input to the initial setting conditions bus connected to the first installation input of the phase shift unit, with the installation input of the counter world address, with the installation input of the cycle counter, with the installation input pulse shaper and the second input of the OR element, the input bus is connected to the analog input of the analog-to-digital multiplier, the output of the clock generator with an adjustable frequency it is connected to the signal input of the phase shift unit, the outputs of all bits, except the high one, the address generation counter are connected to the input of the read-only memory module, its output is connected to the digital inputs of the analog-digital multiplier, the high-order output of the cycle counter is connected to the second installation input phase shift unit, / and the output of the OR element is connected to the reset input analog integrator. From1 TO K7-o V eighteen 6 0U8.2 OTZ -about raj g G7ZHP mt i , 0t 9 P . -N 23 aj g Figure 3