SU953588A1 - Sine voltage distortion digital meter - Google Patents

Description

(54) DIGITAL MEASURING DETAILS SINUSOIDAL STRESS

one

The invention relates to electrical measuring equipment and is intended for use in the implementation of continuous monitoring of voltage distortions of any form at the terminals of electrical receivers, for example, in control systems with thyristor converters.

A device is known for measuring, based on the integral principle of estimating the change in the waveform of the signal, p, and it is a set of functional blocks for determining the difference between the test and sinusoidal voltages, as well as comparing the calculated difference with the normalized area, 5 spars ± 1.

The disadvantages of the known device are associated with the inconvenience of its practical use and the complexity of the design, since in the process of measuring the implementation of an equality schedule for the two compared curves is done.

The closest technical solution is a device for measuring

sinusoidal voltage distortion, which measures the sinusoidal voltage distortion and contains an analog-to-digital converter, one of the outputs of which is connected to the corresponding input of the memory unit, the other output - with the input of the indication unit, and one of the inputs - with the output of the memory unit , the selection unit of the characteristic measurement points, the output of which is connected to another input of the analog-digital converter and to the control key input in the information circuit of the memory unit, and the input to the integrator output connected to the input in a general input device and an information input key 2.

A disadvantage of this device is the impossibility of a comprehensive automatic assessment of halts or harmonic emission emissions at several instantaneous values.

The purpose of the invention is to expand the functionality of the measuring device and reduce the complexity of the measurement process. The goal reaches; In that a sinusoidal voltage distortion measurement device containing an analog-to-single converter, the output of which is connected to the first input of a memory unit, a shaking unit, is entered, a scale converter, a frequency selector filter, a write control unit, two comparators, an OR element, a generator, reference frequency, memory block, a counter, a shaper of short pulses, an adder, a NOT element, a readout control unit, eight registers and four comparison blocks, the output of the reference frequency generator being connected The second and the main inputs of the recording control unit are connected to the output of the frequency-selective filter, the first input of the first KONm speaker and the second input of the second ctarator, the information input of the frequency-selective filter is connected with the information input of analog-digital converter, with the first input of the first comparator, the first input of the second comparator and through the large-scale converter with the terminal of the voltage under study, the first output of the control unit of the record It is connected to the control input of an analog-to-digital converter, the second with a memory unit, the third with a read control unit, the first output of which is connected to the control input of the display unit, the second with the first control inputs of the first and second registers, the third with the third the fourth, fifth and eighth registers and with a mute input of the counter; the fourth register with the address inputs of the memory unit and the storage unit, the informative output of which through the second input of the adder, the first register and the first comparison unit are connected to vt The first control input of the third register, the first output of which is connected to the first comparison unit, the second - from the block and), and the input to the first register, the output of the memory unit through the first input of the sum, the second register and the second comparison unit, is connected to the second the control input of the fourth register, the first output of which is connected to the second input of the second comparison unit, the second one - to the display unit, and the input - to the second register output, the character output of the adder is connected to the second control input of the first register and to the element input NOT, the output of which is connected to the second control input of the second register, the output of the first comparator through the first input of the OR element, the first input of the counter connected to the sixth and seventh registers, the control inputs of which are connected, respectively, to the outputs of the first and second comparators, the first output of the last connected to the second the input of the element OR and Via Yego with the short pulse shaper, the output of which is connected to the input of the zero setting of the counter, the output of the sixth register is connected to the inputs of the third comparison unit and the fifth register The first output of which is connected to the display unit, the second to the third comparison unit, the output of which is connected to the control input of the fifth register, the output of the seventh register is connected to the inputs of the fourth comparison unit and the eighth register, the first output of which is connected to the display unit, the second - with the fourth unit of comparison, the output of the latter is connected to the control input of the eighth register .. The drawing shows the block diagram of the device. The device contains a table-top converter 1, an analog-digital converter (AIP) 2, a memory block 3, an adder 4, a register 5, a comparison block 6, a register 7, a frequency-selective filter 8, a recording control block (ACU), permanent storage block Yu, element 11, register 12, comparison block 13, register 14, comparator. 15, the OR element 16, the counter 17, the read control block (BEAD) 18, the comparison unit 19, the register 20, the indicator 21, the comparator 22, the reference frequency generator 23, the pulse shaper 24, the registers 25 and 26, the comparison unit 27, the register 28. The device It works in the following way. The voltage under study is through May-TAB conversion 1 TEL. It is fed to the input of ADC 2, which converts the analog signal to the corresponding digital code. The operation of A11P 2 is controlled by a control block 9. The frequency-selective filter serves to eliminate the influence of the high harmonics of the network on the operation of the recording control btuk 9 and forming the reference sine wave for the Comparators 15 to 22. When the output voltage of the frequency-selective filter rises to zero crossing, the recording control block 9 generates the control pulses for ADC 2, as well as write addresses for memory block 3. At the same time, the output code of the A / D converter 2 is recorded in the memory block 3 at the corresponding addresses. After the memory block 3 is filled with input data for the period, the reception of the information block 3 of the memory is stopped and the control block 9 controls the transfer signal of the control 18 to the read control block.

The read control block 18 begins to generate read addresses arriving at the memory block 3 and the block. ip. In the block Yu, the code corresponding to the period of the negative sinusoid is recorded. The output codes of the 1O block and the corresponding output codes of the memory block 3 are fed to the input of the adder 4, and since the negative sinusoid code is received from the 1O block, the output of the adder 4 forms the deviation code of the investigated voltage from the sinusoid, the current value of which is written to register 5 troughs or into the ejection register 12. The selection of the register controls the ADDRESS digit of the adder 4.

If the output code of the adder is negative, the current deviation code is recorded in the register 5 of the cavity, otherwise, the sign bit of the adder is inverted by the element NOT 11, which permits the recording of a positive deviation code (outlier). In this case, registers 5 and 12 are clocked with short pulses of the read control block 18.

The output code of register 5 is fed to the first input of the compare block 6, the second input of which receives the output code of the register 7. In the case of the first code of a large second code, the compare block 6 generates a census pulse of the contents of register 5 into the output register 7 (troughs). Thus, in register 7, the maximum value of the negative deviation of the input voltage from the sinusoid (trough) is recorded.

The operation of the registers 12 and 14 and the comparison unit 13 is similar, and in register 14 the maximum value of the positive deviation of the input voltage from the sinusoid (surge) is recorded

After the processing of the information recorded in memory block 3 is completed, the output

Codes of registers 7 and 14 are posted to indicator 21, whose operation is also controlled by read control unit 18. The indication time is set by the block.

18 of the control, reading and after its completion, the block 18 of the control of reading reads registers 7 and 14, as well as 2O and 28 and the counter 17 into the nut. After that, the next receive cycle begins.

information control block read

18 transfers control to block 9,,

no record. The operation of the BUS 9 and the BEAD 18cHHJi: p (is downgraded by the reference frequency generator 23.

The channels for determining the temporal parameters of the emissions and the troughs of the input voltage operate simultaneously with the recording of information in the memory as follows.

The voltage from the output of the masigub converter is fed to the inverted input of the comparator 15 and to the direct input of the comparator 22. The sinusoidal voltage of the frequency-selective filter 8, whose transmission coefficient is 1, is used as the reference voltage, and the reference sinusoidal voltage goes to the direct input the comparator 15 and the inverted input of the comparator 22. As a result, at the output of the comparator 15 there is a positive voltage pulse at the occurrence of a depression at the input voltage, and at the output of the cockshare 22 - upon the occurrence of an outlier, the duration of the output pulses of the comparators 15 and 22 being the duration of the depression and the outburst, respectively. These pulses do not overlap in time, since the outburst and valleys cannot exist alone {5muenno.

Claims (2)

Through the element OR .; 16, the pulses are alternately received at the resolution input of the counter 17 and during the duration of the depression (ejection) the counter 17 counts the pulses arriving at it from the generator 23 of the reference frequency. After the end of the depression, the pulse at the output of the comparator 15 stops, and the trailing edge of this pulse occurs; Record the contents of the counter 17 in the register 25 (hollows). At the same time, the negative pulse front from the output of the OR element 16 is fed to the short pulse shaper 24, which resets the counter 17 to zero, preparing it to determine the code of the next release (depression). The code for the ejection duration is determined in the same way, and its 6 entry is made in the register 26, the output code of the register 25 is received on the first input of the comparison unit 19, to the second input of which the code of the output register 20 of the trough length arrives. If the register code 25 is faster than the register code 2O, the digital comparator 2 2 generates a signal of the census of the register code 25 into the register 2O. In this case, in register 20, the maximum duration of the depression that takes place during the information receiving cycle in memory block 3 (for the period of the input signal) is recorded. Registers 26 and 28 to Comparison Block 27 operate similarly. In this case, in register 28, the maximum emission is recorded, which takes place during the reception cycle of information in memory 3. The output codes of registers 2O and 28 are sent to the Schshitcher 21. Invention formula Digital distortion meter of sine-voltage, containing analogue a digital converter, the output of which is connected to the nepBbDvi input of the memory unit, the display unit, which differs from that in order to expand the functionality and reduce the laboriousness of the measurement process, a large-scale conversion is introduced into it spruce, frequency-selective filter, recording control unit, two Comparators, eleme;: t OR, reference frequency generator, storage unit, counter, shaper of short impediments, adder, element NOT, count control unit THBamieM, eight registers and four comparison units The output of the reference frequency generator is connected to the clock inputs of both control units and the counter, and the second contacting input of the record control unit is connected to the output of the frequency-selective filter, to the first input of the first comparator and the second input the second cocharator, the information input of the frequency selective filter is connected to the information input of the analog-digital converter, the second input of the first comparator, and the first input of the second comparator, and through the Masigate converter - to the terminal of the voltage under test, the first output of the recording control unit is connected to the control KTsM input 66 analog-digital converter, the second - with the memory unit, the third - with the read control unit, the first of which is connected to the control unit input of the display unit, the second - the control inputs of the first and second registers, the third with the third, fourth, fifth and eighth registers and with the control input of the counter, the fourth with the address inputs of the memory unit and the storage unit, the information output of which through the second input of the adder, the first register and the first comparison unit is connected: to the second control input of the third register, the first output of which is connected to the first comparison unit, the second to the display unit, and the input to the first register, the output of the memory unit through the first input of the adder, the second register and the second comparison unit is connected to the second control input of the fourth register, the first output of which is connected to the second input of the second comparison unit, to the idication unit, and the input to the output of the second register, the sign output of the adder is connected to the second control msod of the first register, and with the input of the element NOT, the output of which is connected to the second control input of the second register, the output of the first comparator through the first input of the element OR, the first input of the counter connected to the second and seventh registers, controlling; respectively, are connected to the outputs of the first and second comparators, the output of the latter is connected to the second input of the OR element, and through it to the short pulse shaper, the output of which is connected to the installation input to the counter zero, the output of the third register is connected to the inputs of the third comparison unit and a fifth register, the first in which the output is connected to the display unit, the second to the third comparison unit, the output of which is connected to the control input of the fifth register, the output of the seventh pei% CTpa connected to the inputs of the fourth comparison unit audio and eighth register, a first output connected to the display unit, the second - fourth comparison unit, the latter output is connected to the control input of the eighth register. Sources of information taken into account during the examination 1. Smoked E.G. and Kharchenko V.A. Application of the maximum of the average 9 53568Л loads to estimate the sine distortion 2. USSR author's certificate long voltage Electromechanics, № 63О591, кл. G O1 R 19/00, 1977 Lime universities, 1978, № 6, p. 629. (prototype).