RU1837324C - Statistical analyzer of voltage surges and drops - Google Patents

Abstract

The invention relates to electrical engineering and can be used in instrumentation monitoring of electricity. The purpose of the invention is to increase the reliability of measurements. The statistical analyzer contains an RS flip-flop, a counter, memory blocks, a module driver, a zero-organ, an analog-to-digital converter, a NOT element, a voltage source, a subtractor, and an AC / DC converter. 2 ill.

Description

ri va po

vano

The invention relates to electrical equipment and can be used in apparatus control of power quality indicators.

The aim of the present invention is to increase the reliability of measurements due to the analysis of outliers and dips with both increasing and decreasing nature of the change in the envelope of the studied voltage of the network.

In FIG. 1 is a structural diagram of a proposed statistical analyzer of surge and voltage dip; in FIG. 2 is a timing diagram of the voltages at the outputs of individual components illustrating its operation.

The statistical analyzer of surges and gallops contains a variable-voltage converter 1 to a constant, the input of which is the information input of the analyzer, and the output is connected to the summing input of the amplifier-subtractor 2, subtracting the input of the compensating voltage connected to the source 3. The output of the amplifier - subtractor 2 is connected to a point that combines the input of the null-organ 4 and the input of the driver 5 of the module, the output connected to the information input of the ADC b, the information outputs of which are connected via the data bus 7 with the combined information inputs-outputs of RAM 8 and 9. Output the readiness of the ADC is connected to the write enable inputs of RAM 8 and 9, to the counting input of the address counter 10 and through the element 11 to the ADC-enabling input, the start input of which is connected to the inverse output of the RS flip-flop 12, the setting input is zero to the transfer output of the address counter 10, the bit outputs of which are connected by the address bus 13 with the combined address inputs of RAM 8 and 9. The direct output of the zero-organ is connected to the sample input of RAM 8, and its inverse output is connected to the sample input of RAM 9. the single input of trigger 12 is the trigger input of the analyzer.

"" &

s xi

Yu

The analyzer is single-channel. The device memory unit is made on two parallel connected random access memory devices.

Information is accumulated during the analysis of the random process of voltage surges and dips using ADC 6, and its storage is in RAM cells 8 and 9. In this case, the ADC responds to every change in the signal and fixes its stable state in the form of a digital code which is then written to RAM.

The device operates as follows.

The variable input signal U8x is converted by the block 1 to a constant, which is fed to the summing input of the amplifier - subtractor 2, to the subtracting input of which a compensating voltage is applied proportionally to the rated voltage (Fig. 2a), supplied from block 3. At the output of the amplifier-subtractor 2, a deviation of the mains voltage from its nominal level U U-UHOM is formed, represented as a direct current voltage (Fig. 26), which is supplied simultaneously to module former 5 and to zero-organ 4.

Consider the operation of the device in the analysis of voltage surges. In this case, the voltage deviation formed at the output of the amplifier-subtractor 2 (Fig. 26, time ti-t4) is repeated by the driver 5 of the module without changes and is supplied to the information input of the ADC 6 (Fig. 2c, time).

In the process of changing the voltage, U crosses the zero value (at time ti), which leads to the operation of the zero-element 4, a single pulse from the direct output of which is applied to the input of the RAM sample 8.

At this moment. By the Start signal, trigger 12 starts the ADC 6, which starts converting the received analog information into a digital code .. At the end of this conversion, the analog code, i.e. when generating a code corresponding to the value of emissions Ui (Fig. 2c), a single pulse appears at the output of the ADC ready. The indicated signal is simultaneously supplied to the element NOT, to the combined write enable inputs of RAM 8 and 9, and to the counting input of the address counter 10, which goes into the next state upon the decline of this pulse. In this case, the element 11 removes from the ADC a ban on the output of data, and from its information outputs, the received information goes to the data bus 7. Since at this moment RAM 8 is ready to receive information, the codes issued by the ADC

are recorded in its cells at the address indicated by the address counter 10.

Further, at time ta, a decrease in the voltage U to the level U2 (Fig. 2c) leads to a change in the state of the ADC 6, which switches from the output mode to the information processing mode. In this case, a zero occurs at the ADC ready output, which causes a unit to appear at the output of the NOT element. Then, the ADC starts again and the voltage-code is converted in it. When a digital code is generated corresponding to the value of Va emissions (Fig. 2c), one more appears at the output of the ADC ready, and then the process continues similarly.

In this way, information is accumulated in the memory unit of the device.

When a voltage dip appears at time m (Fig. 26), the null-organ 4 returns to its original state and a unit voltage arises at its inverse output, which is applied to the input of the RAM sample 9, and the driver 5 module inverts the output voltage a subtractor amplifier (U-UH).

Otherwise, the operation of the analyzer during voltage dips is similar to that described above. Only the accumulation of information is carried out in RAM 9.

After accumulating a sufficient amount of information on the contents of random access memory 8 and 9, respectively, histograms of outliers and dips are constructed, according to which the quality of the studied voltage of the network is more reliably estimated.

The advantages of the proposed device in comparison with the known ones are high reliability of measurements, twice as much information needed to obtain histograms of surges and voltage dips, as well as greater efficiency and reliability, lower cost and power consumption.

Claims (1)

The claims A statistical analyzer of surges and voltage dips containing an RS trigger, a counter, a first memory block, a module former and a zero-organ, whose direct output is connected to the read control input of the first memory block, whose address input is connected to the counter output, characterized in that, in order to increase the reliability of measurements, an analog-to-digital converter, a second memory unit, a HE element, a voltage source, a subtractor, and are introduced into it. d AC converter E is a constant whose input is input f. ohm of the analyzer, and the output is connected to the input of the diminishing subtractor, the input of which is subtracted is connected to the output of the voltage source, and the output is connected to the input of the zero-organ and, through the module former, to the v information input of the analog-to-digital converter, the information output of which connected to the information inputs of the memory blocks, the inverse output of the zero-organ is connected to the read control input the second memory block, the address input of which is connected to the counter output, the overflow output of which is connected to R-sxo - the home of the RS-flip-flop, the S-input of which is the start input of the analyzer, and the inverse output is connected to the clock input of the analog-to-digital converter, the output is terminated the operation of which is connected to the recording permission input of the memory blocks, to the counter input of the counter and through the element NOT to the operation enable input of the analog-to-digital converter. ti 45 Figure 2 (b)