RU2046359C1 - Multiple-harmonic predicting filter - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: device has adders, delay gates, component decomposition unit, component variance calculation units, divider, subtraction unit, threshold unit, amplifier, differentiating unit, variance calculation unit, counter, decoder, read- only memory units, AND gates, digital-to-analog converters, filters, extrapolation units. EFFECT: increased functional capabilities. 2 cl, 3 dwg

Description

 The invention relates to radio engineering and can be used to extrapolate a random process containing a periodic component with an unknown repetition period.

 In FIG. 1 shows a block diagram of a polyharmonic predictive filter; figure 2 is a structural diagram of a block decomposition into components; figure 3 timing diagrams of the operation of the device.

 The polyharmonic predictive filter (Fig. 1) contains a second adder 1, a delay element 2, a component decomposition unit 3, component dispersion calculators 4-1, 4-K, a third adder 5, a divider 6, a calculation unit 7, a threshold unit 8, an amplifier 9, a differentiating unit 10, a dispersion calculator 11, a first counter 12, a first decoder 13, a first permanent memory unit 14, a first AND element 15, a second AND element 16, second read-only memory blocks 17-1.17-N, digital-to-analog converters 18- 1,18-N, filters 19-1, 19-N, extrapolators 20-1,20-N, third adder 21.

 Block 3 decomposition into components (figure 2) contains a clock generator 22, a second counter 23, a second decoder 24, the third elements And 25-1, 25-K, switch 26, analog-to-digital Converter 27.

 The device operates as follows.

A_mcos m ωt + ζ(t) Xⁿ(t)+ζ(t) (1) где А_m амплитуда m-й гармонической составляющей;
Т, ω период и опорная частота периодической составляющей, величина которой заранее неизвестна (ω=2 π/Т);
Xⁿ(t) периодическая составляющая;
ζ(t) случайная составляющая;
Т_р= q ˙ T длина реализации;
q число периодов в реализации.Before starting work, the elements of the device are set to the initial state: the number p = 4 is recorded in counter 12, the counter 23 is set to zero. The input of the device, which is the first input of the first adder 1, receives a signal x (t) (figa), which is an implementation of an additive mixture of a periodic component, which is conveniently represented as the sum of N harmonics and a random component:
X (t)

A _m cos m ωt + ζ (t) X ⁿ (t) + ζ (t) (1) where A _{m is the} amplitude of the m-th harmonic component;
T, ω period and reference frequency of the periodic component, the value of which is not known in advance (ω = 2 π / Т);
X ⁿ (t) is a periodic component;
ζ (t) is a random component;
T _p = q ˙ T implementation length;
q the number of periods in implementation.

In order to predict (extrapolate) for an arbitrary lead time Δ t _e , i.e. to find the value x * (t + Δ t _e ), it is necessary to know the amplitudes of the harmonic components A _m and the magnitude of the reference frequency ω.

The value of the reference frequency ω is as follows. From the output of the adder 1 of the implementation of the random process x (t) through the amplifier 9 and the delay element 2, the delay time of which is equal to the implementation length T _{p of the} signal x (t), is fed to the first input of the component decomposition unit 3. In this case, the first input of the component decomposition unit 3 is simultaneously the first input of the analog-to-digital converter 27, the second input of which receives clock pulses with a period Δt _e from the second input of the clock generator 22. In the analog-to-digital Converter 27 is the discretization of the original implementation and its conversion to digital form (figa).

 As an analog-to-digital converter 27 of the component decomposition unit 3, a standard ADC is used, at the output of which a multi-bit digital code is generated synchronously with each clock pulse, corresponding to the value of the input analog signal per given clock cycle (Fig.3b, c, d). This digital code arrives simultaneously at the first inputs of all systems of elements And 25-1.25-K. Each element And 25-1,25-K is a block and n elements And, where n is the resolution of the output signal of the ADC 27.

The control inputs of the elements And 25-1.25-K receive signals from the outputs of the decoder 24. Moreover, in each sampling cycle, only at one output of the decoder 24 a signal appears that opens at a given moment in time only one of the elements And 25-1.25-K , through which the reference code of the signal amplitude X _{t / i} , where i = 4, p, from the output of the ADC 27 enters only one of the K outputs of the decomposition block into components.

Thus, the control elements And 25-1,25-K, where K = T _p / Δ t _e , is carried out by the signals from the outputs of the decoder 24, the input of which is connected to the output of the counter 23. The counter 23 counts the number of pulses from the output of the clock generator 22 . At the outputs of the elements And 25-1.25-K, and, therefore, 1.K-th outputs of the block 3 decomposition into components are formed of the components of the random process X _{t / i} = X _i + ζ _{t / i} (Fig.3, b .to). The number of allocated components at different clock cycles of calculations (depending on the value of p) is different and is determined by the contents of the counter 12.

As noted above, at the first step of the calculation, the number p = 4 is written in the counter 12 and a control signal is generated at the output of the decoder 13, which is fed to the second input of the component decomposition unit 3, which is also K + 1 input of the switch 26. In accordance with the control signal (in this case, proportional to 4), the switch 26 connects its fourth input (fourth output of the decoder 24) to its output (to the second input of the counter 23). Therefore, as soon as the counter 23 counts four clock pulses from the output of the clock generator 22, a pulse appears at the fourth output of the decoder 24, which passes the output of the And 25-4 element to the amplitude sample from the output of the analog-to-digital converter 27 (Fig. 3d), and the same the pulse through the switch 26 is switched to the second input of the counter 23 and resets it to zero. Thus, at the first step, at the outputs 1-4 of the component decomposition unit 3, four sequences appear (Fig. 3n, g, h, and) of the samples of the amplitude of the input signal: samples at the first output are numbers 1,5,9, at the second output samples with numbers 2,6,10, at the third output samples with numbers 3,7,11, at the fourth output samples with numbers 4,8,12, then each of the four components of the random process X _{t / i} , where i = 1.4, provided to a respective calculator 4-1,4-K output from the dispersion values which i-th component S _{x / i} ² are supplied to an adder 5. The output of the adder 5 elichina dispersions sum component is supplied to the divider 6, to a control input of which a signal is output from the decoder 13. At the output of divider 6, we obtain the average value of the dispersion of all components of p = 4, i.e.,

=

S $\genfrac{}{}{0ex}{}{\text{2}}{\text{x}}$ _/i.

=

S $\genfrac{}{}{0ex}{}{\text{2}}{\text{x}}$ _{/ i} .

.From the output of the divider 6, the measured average dispersion value of all p components is fed to the input of the subtraction unit 7, the second input of which receives the calculated dispersion value of the process S _x ² . The dispersion value of the process S _x ² is measured using the dispersion calculator 11, the input of which receives a random process x (t) with K + 1 output of the decomposition block into components. At the output of the subtraction block 7, a variance difference is formed
DS $\genfrac{}{}{0ex}{}{\text{2}}{\text{x}}$ -

.

The random value of the variance D obeys the f ² distribution, is a power, and it can be used to judge the presence of a periodic component. The magnitude of the variance difference D in the threshold block 8 is compared with a threshold whose value is received from the output of the permanent memory block 14. All possible threshold values for preset probabilities of erroneous decision-making of the 1st and 2nd kind, which are tabulated for the χ ² distribution, are pre-recorded in the permanent memory block. The choice of the threshold value is carried out by a control signal coming from the output of the decoder 13. In this case, the degree of freedom for χ ² distribution is νр-1, where p is the content of counter 12.

 In the case when the threshold has not been exceeded and the impulse voltage is not generated at the output of the threshold unit 8, the signal delayed in the delay element 2 is again fed to the input of the adder 1. From the output of the adder 1, the delayed realization x (t) through the amplifier 9 is supplied to the differentiating unit 10 . At the output of the differentiating block 10, a pulse is generated that enters the counting input of the counter 12, increasing the contents of the counter by 1 (p = 4 + 1 = 5).

 Thus, the number p = 5 is written in the counter. At the output of the decoder 13, a control signal is generated corresponding to the number p = 5 recorded in the counter 12. Now, in accordance with the control signal (in this case, proportional to five), the switch 26 connects the fifth output of the decoder 24 to the second input of the counter 23. Therefore, in the second step calculations at the outputs 1-5 of the block 3 decomposition into components there are five sequences of samples of the amplitude of the input signal: at the first output, samples with numbers 1,6,11. on the second output, readings with numbers 2,7,12. on the third output, readings with numbers 4,9,14. on the fifth output, readings with numbers 5,10,16. Further, the operation of the device is similar to that described previously.

Such a process occurs until a threshold is exceeded and an impulse voltage is generated at the output of the threshold unit 8. Exceeding the threshold indicates that in a random sequence x (t) with given errors a periodic component with a period p р Δ t _{e was} detected. Next, the pulse signal (its trailing edge) of the threshold block 8 is supplied to bring the counter 12 to its initial state and to resolve the elements And 15 and 16. At the input of the element And 16 the code of the counter 12 corresponding to the period value of the detected periodic component is received, and through the And 16 element the code arrives at the address inputs of blocks 17.1,17.N, in which each output of element And 16 has its own shapers of digital values of the frequencies K / p corresponding to multiple periods of the periodic component of the random process x (t).

Blocks 17.1.17.N of permanent memory are designed so that when the input code, for example, is 4N, multiple outputs of the input code will be present at their outputs. At the output of the constant memory block 17.1, the output code will be 4N Δ t _e ; at the input of block 17.2, the output code will be 2N Δ t _e , etc. and the output of block 17. N the output code will be 4. Δ t _e . From the output of the permanent memory unit 17, the digital frequency values are fed to the inputs of the DAC 18, in which the digital values of the frequencies are converted to a control analog voltage supplied to the control inputs of the tunable resonant filters 19. At the second inputs of the tunable resonant filters 19, an implementation of random process x (t) from the output of adder 1 through amplifier 9. From the output of tunable resonant filters 19, the amplitudes of m-x harmonic components arrive at the inputs of extrapolators 20 And _{m is the} signal x (t). Each harmonic component with known A _m and ω _m can be extrapolated to an arbitrary lead time Δ t _e . From the outputs of the extrapolators 20, harmonic components extrapolated for an arbitrary lead time Δ t _e are fed to an adder 21, at the output of which one can obtain the predicted value of the random process x (t) for an arbitrary lead time.

Claims (2)

 1. POLYHARMONIC PREDICTING FILTER, containing the first adder and N channels from a series-connected filter and extrapolator, the outputs of which are connected to N corresponding inputs of the first adder, the output connected to the output of the filter, characterized in that it is connected to the input, connected in series to the second adder , an amplifier, a differentiating block, a counter, a decoder and a decomposition block for components, N calculators of dispersion of a component, a third adder, a divider, a block connected in series subtraction and the threshold block, as well as the delay element, two elements And, N series-connected circuits of blocks of read-only memory and digital-to-analog converters included between the second element And and the corresponding filters, as well as N + 1 blocks of read-only memory connected between the decoder and the second input a threshold block connected to the first inputs of the elements AND and the second input of the counter, while the second inputs of the elements AND are connected respectively to the outputs of the amplifier and decoder, the output of the first element And to the input N filters, the output of the delay element to the inputs of the second adder and the second input of the decomposition into components through N appropriate calculators of the dispersion of the components connected to the inputs of the third adder, the input of the delay element to the output of the amplifier, and the second input of the divider is connected to the output of the decoder.  2. The filter according to claim 1, characterized in that the component decomposition unit is made in the form of a series-connected clock pulse generator, a second counter and a second decoder, as well as an analog-to-digital converter, a switch, and K elements And, the first inputs of which are connected to the outputs the second decoder and with K inputs of the switch, the second inputs of the elements And are connected to the output through an analog-to-digital converter, the first input of which is connected to the first input of the unit, the second input with the first input of the second counter, the second input which is connected to the output of the switch, (K + 1) -th input of which is connected to the second input of the block, K outputs of which are connected to the outputs of the element I.

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