SU1370589A2 - Spectrum analyser - Google Patents

Abstract

The invention can be used to determine the cosine and sine components of the amplitudes and the initial phases of the periodic signal harmonics. The analyzer contains transducers 1 and 2 code - voltage and voltage - code, memory element 4, calculation and indication block 5, consisting of computing block 6 and indication block 7, combination summers 3 and 12, frequency multiplier 8, pulse distributor 9 accumulating adder II and block 13 of the formation of constants. The formation of new functional connections and the introduction of a logic circuit 14, which converts the state of the outputs of the counter 10 into the control signals of the operating modes of the combination adder 3, increases the accuracy and extends the dynamic range of the recorded harmonics. 2 Il. P "(L

Description

with

U1

00

The invention relates to a measurement technique and can be used to determine the cosine and SINUS components of the amplitudes and initial phases of the harmonics of the periodic signals.

The aim of the invention is to increase the accuracy and broaden the dynamic range of the recorded harmonics.

Fig, 1 shows the block diagram of the proposed spectrum analyzer; figure 2 - timing charts of his work.

Device (Leaves the input bus connected to the serially connected converter 1 code - voltage (PKN), converter 2 voltage - code (PNK), the second combination adder 3, the storage element 4 and the unit 5 of calculation and display consisting of a computing unit 6 and the display unit 7, the outputs of the storage element 4 are connected to the second inputs of the adder 3. The input bus is also connected via serially connected frequency multiplier 8, pulse distributor 9 and counter 10 to the start input will calculate The first unit 6. The accumulator 1O1 adder 1 1 through the first combinational adder 12 and the unit 13 for the formation of constants is connected to the control inputs of the PCN 1; 12 and the address bus of the storage element 4 are connected to the output of the first trigger of the counter 10, the second control input of the first adder 11 is connected to the output of the second trigger of the counter 10, which is connected with the remaining outputs of the counter 10 to the additional inputs logic circuit 14, the outputs of which are connected to the control inputs of the operation modes of the adder 3. The output) of the distributor 9 pulses are connected to the control inputs of the OIL 2, the storage element 4 and the adder 11.

The device works as follows.

One cycle of operation of the device corresponds to one period T of the input signal U, which is fed to the inputs of PKN I and frequency multiplier 8. The operation of the device is synchronized.

the output pulses of the frequency multiplier are 8, the period of which is equal to T / N, where I is the frequency multiplication factor. These pulses arrive at the distributor 9 pulses, which generates pulses U1, U2, and UZ, synchronizing the start of the NCP, writing to the memory 1 1 element 4, moments of summation of the adder 11, respectively (see Fig. 2). The distributor 9 also generates a pulse arriving at the counting input of the counter 10, whose capacitance is N. The overflow pulse of the counter 10 resets the adder 1 1 to the state O and starts the computing unit 6.

The control inputs of the adder 1J are supplied with a code K, corresponding to the number of the measured voltage harmonic, and After the n-th output pulse of the multiplier 8 frequency, the output code of the adder 11 is equal to

q mod (pk).

h N

This code enters through the adder 12 to the address bus of the block 13;

On the first and second control inputs of the adder 12, the following combinations of codes are possible, which come from the outputs of the first and second triggers of the counter 10:00; 01; ten; 11. These codes increase the input code of the adder 11 by the value of O, N / 4, N / 2, 3N / 4, respectively. Therefore, after 0.4.8, ..., N-4 output pulses of frequency multiplier 8, the mod code (pc) is applied to the input of block 12, after 1.5, -, 9, ..., N-3 pulses - code mod (pK - “- + N / 4), after 2,6,10, s, s, N-2 pulses - code mod (nK + N / 2), after 3,7, 11, ..., N -1 pulses - mod code. (pc + 3n / 4).

Unit 13 for the formation of constants g. 2JT does not issue output codes in --- q,

I J t |

which are defined by the q code on its address buses. Therefore, when p 0,4,8 ,, .., N-4 at the output of the block

12 there are sin PC codes, with

N

201

 , 5, 9, ..., N-3 - codes cos-rt-SH.pri

.i-j

2 jj, 4,6N-2 - codes -.h1n-g, -pK, with

yy

2G

5, 5.7, ..., N-1 codes -cos.

These codes arrive at PCN1 and determine its transmission coefficient at each time point.

31370589

The output voltage ICH1 is proportional to the product of the voltage 11 i; and the code at the inputs of TSC1, arrives

and l

At the end of the period T o and 1 of the storage element 4, the sine codes appear (n 1 V and the cosine K th of the first monitor, for example, which are equal to:

X

where and is the instantaneous value of the input voltage at the moment of the n-th trigger of the IIHK2;

m O, 1N / 4-1;

L - additive error of channel IIKH1,.

Codes X | From the output, the PNK2 is fed to the input X of the adder 3, which either transmits the code X to the output Z of the adder 3 without changing, if the command ZX is removed at its control mode inputs F from the output of circuit 14, or is added to the contents of the corresponding storage element 4, the code from which is fed to the input Y of the adder 3 with the command at its inputs F, or subtracted from the code at the input Y with the command Z Y-X at the input F.

The operation performed by the adder 3 is completely determined by the state of the counter 10, which with the help of logic circuit 14 is transformed into a command at the inputs F (see FIG. 2): () with n 0, 1;

() with p 2,3,6,7 ..., N / 4-2, N / 4 () with n 4,5, .., N / 4-4, N / 4-3

The operation corresponds to the initial installation of the cells of the storage element 4, since after it the new contents of the cells do not depend on what was stored in them before performing this operation. They are scored codes

X

defined by formula

M 1

To the other inputs 1 of the adder 3 from the storage element 4, the contents of the cell O at 4g1 + 2 or the cells 1 at 4m + 3 are output. The result of the summing from the output ./ of the adder 3 is entered into the same cell of the storage element 4. The cell address is determined by the state of the first trigger of the counter 10.

one

ten

15

- jq

d

B.

fn-o

v-,

(.. StTiv

P.,,

; 2)

/

but

fTirO

Output codes SH1K2 II

X, .X without ,, (1Т1 I

since they i111i

The minus rutas are subtracted from the code at the input I of the adder 3. Substituting the values (1) of the output codes of the NCP 2 into formula (2), we get after the transformations

po

 T1-O N

P 2 (t,

- one

and

 J o tl

sin --- 2mK; ,, cos --- (2m + l

(h;

G.

Codes b to k are output to computing unit 5, which is triggered by the overflow pulse of counter 10. In block 5, the amplitude and the initial phase of the Kth harmonic are calculated:

0

five

0

five

0

five

II tk

+ B

H arctg - which are then indicated by block 6.

The operation of shock 5 and the determination of components a and b occurs simultaneously. Therefore, measurement results can be obtained at each period.

The proposed device eliminates the additive component of the error. Despite the presence of additive linearity in the output codes of the PNK2, in the measurement results of the sine and cosine harmonics the additive error is & absent, as it follows from formula (K). This makes it possible to increase by an order the accuracy of harmonic measurements, whose amplitudes do not exceed a few percent of the first harmonic level, and expand the range of measured harmonics towards small amplitudes that are tenths and hundredths of a percent of the first harmonic level.

Thus, by introducing new connections and a logic circuit 14, which converts the state of the outputs of the counter 14 into the control signals of the operating modes of the combinational adder 3, the accuracy and increase of

Claims (1)

wide dynamic range is registered; an additional logical harmonic harmonic circuit is introduced, the output of which is connected to the control inputs of the operating modes; the second formula of the invention of the combinational adder, with this is the second control input of the first Spectrum analyzer auth. combinational adder No. 1033979, which is different to the output of the second counter of the counter, is connected with the fact that, in order to increase the accuracy of the outputs of all the bits of the counter, for and to expand the dynamic range except for the first one, the additional harmonics logical scheme.