JPH0769358B2 - Frequency-voltage converter - Google Patents

Description

The present invention relates to a frequency-voltage converter for obtaining a voltage corresponding to the frequency of a frequency signal.

[Prior Art] A conventional typical frequency-voltage converter triggers a mono-multivibrator at a leading edge of a pulse of a frequency signal to generate a pulse having a constant width, and a pulse train thus obtained is subjected to a low-pass filter. It is configured to perform smoothing (averaging).

[Problems to be Solved by the Invention] By the way, the conventional frequency-voltage converter of this kind has a drawback that it has a poor trackability to a frequency change, that is, a responsiveness.

Since the low-pass filter has a cutoff frequency, the frequency in the low frequency range below the cutoff frequency
Voltage conversion was impossible.

Therefore, a first object of the present invention is to provide a frequency-voltage converter having good followability and response to frequency changes.

A second object of the present invention is to provide a frequency-voltage converter that can perform frequency-voltage conversion even in a low frequency region.

[Means for Solving the Problems] The present invention for achieving the first object includes an input terminal for inputting a frequency signal to be converted into a voltage, and a clock signal having a frequency higher than the frequency signal. A clock signal generating circuit for generating, a counter having a counting input terminal connected to the clock signal generating circuit, and a reset terminal associated with the input terminal so as to be reset every one cycle of the frequency signal; A latch circuit that latches a clock count output obtained from a counter at the end time or start time of each cycle of the frequency signal, a counter output value obtained at any time from the counter, and a latch output value obtained from the latch circuit. In comparison, when the counter output value is smaller than the latch output value, the latch output value is selected and output. When the counter output value is larger than the output value, a data synthesizing circuit that selects and outputs the counter output value, and an output value corresponding to the cycle of the frequency signal obtained from the data synthesizing circuit is a digital voltage corresponding to the frequency. The present invention relates to a frequency-voltage converter having a data conversion circuit for converting a value.

Further, in order to achieve the second object, it is desirable to configure the clock signal generation circuit as a variable clock signal generation circuit.

[Operation] The counter according to the present invention outputs a value corresponding to the cycle of the frequency signal. Since the output of the counter changes every time the clock signal is input, it changes like a triangular wave or a sawtooth wave. on the other hand,
The output of the latch circuit changes like a staircase wave according to the change of the cycle of the frequency signal. The output of the latch circuit includes cycle information, but since it is a staircase wave, it has poor followability and responsiveness to cycle changes. However, if the larger one of the latch output and the counter output is selected and output, the counter output that increases with time is arranged between the low stage and the high stage of the latch output, and the followability to the change of the period and Responsiveness is improved. Since the period T and the frequency f have a relation of f = 1 / T, it is possible to convert the data of the period T into the data of the frequency f, that is, the data of the voltage V by a known method.

[Embodiment] Next, a frequency-voltage converter according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

A waveform shaping circuit 2 is connected to the frequency signal input terminal 1 of FIG. The waveform shaping circuit 2 shapes the input signal into a rectangular wave and outputs the frequency signal shown in FIG.

The oscillator 3 generates a clock of 1 MHz which is sufficiently higher than the frequency signal. The frequency divider 4 connected to the oscillator 3
The output of is divided into multiple stages and output. Multiplexer 5
Is a plurality of terminals a to connected to the oscillator 3 and the frequency divider 4.
The signal of h is selectively selected and sent to the output line 6.
The clock signal obtained on the output line 6 also has a higher frequency than the frequency signal on the input terminal 1. The switch SW of the multiplexer 5 is automatically controlled by the control circuit 7.

The clock input terminal of the counter 8, that is, the count input terminal CK is connected to the output line 6 of the multiplexer 5, and the reset terminal R is connected to the waveform shaping circuit 2. Counter 8
A digital counter for generating a 16-bit output, the leading edge (t1 ,, t of the frequency signal pulse of FIG. 2B)
2, t3, etc.), that is, reset at the end (start) of each cycle,
Count the clock again. FIG. 2 (C) schematically (digitally) shows the digital output of the counter 8. As is apparent from FIG. 2 (C), the counter 8 has a frequency signal of 1
The cycle is being measured.

The outputs of the upper 3 bits (MSB, 2SB, 3SB) of the counter 8 are connected to the control circuit 7 of the multiplexer 5. In the control circuit 7, the above 3 bits of the counter 8 are from [000] to [00
1] when the output frequency of the multiplexer 5 changes
The switch SW is controlled so that the frequency signal of the frequency divider 4 which is one step lower is selected every time when the step is lowered and then one digit is increased. Therefore, the input clock frequency of the counter 8 changes as shown in FIG.

The latch circuit 9 is formed by connecting 16 D flip-flops in parallel, and the 16-bit output line 10 of the counter 7 is connected.
16 input terminals D connected to each other and a clock input terminal CK connected to the waveform shaping circuit 2. Latch circuit 9
When the frequency signal pulse of FIG. 2 (B) is input to the clock input terminal CK of, the output of the counter 8 is read in response to this leading edge (rising edge). Therefore, the latch circuit 9 holds the counter output (data indicating the cycle) one cycle before the frequency signal for the next one cycle, and outputs the output as shown in FIG. 2D to the Q output terminal. That is, the counter output data D1 at t1 in FIG. 2C is held by the latch circuit 9. The clock is still input to the latch circuit 9 at time t2,
Since the counter output is the same, the latch output does not change. Since the counter output data has changed to D2 at time t4, the output of the latch circuit 9 also becomes D2.

The data synthesis circuit 11 includes a first data selection circuit 12 including a latch connected to the counter output line 10 and a second data selection circuit including a latch connected to the latch circuit 9.
13, a data comparison circuit (comparator) 14 connected to the latch circuit 9 of the counter output line 10, and a comparison circuit
And a selection control circuit 15 for controlling the data selection circuits 12 and 13 with the output of 14. The comparison circuit 14 digitally compares the 16-bit counter output and the 16-bit latch output, and generates an output indicating the magnitude of both. Selection control circuit 15
Controls the first data selection circuit 12 to be in the ON state when the counter output is larger than the latch output, and sets the counter output to 16
When the counter output is less than or equal to the latch output, the second data selection circuit 13 sends the output of the latch circuit 9 to the common output line 16 when the counter output is less than or equal to the latch output. As a result, the data schematically shown in FIG. 2E is obtained on the common output line 16. As is clear from the comparison of FIGS. 2C, 2D and 2E, t0 to t1, t3 to t4, t7 to t8, t9.
The output of the counter 7 is sent to the common output line 16 in the subsequent sections, and the output of the latch circuit 9 is sent in the other sections. The data shown in FIG. 2 (E) has better followability and response to the frequency change of the input signal than the latch output data shown in FIG. 2 (D). That is, if it is determined that the current cycle is longer than the previous cycle even within one cycle, the counter output is selected from that time, and the data indicating the new cycle is obtained. As a result, the output of FIG. 2 (E9) has better response characteristics to the input frequency signal than the output of FIG. 2 (D).

Further, even during one cycle of T2 to t4, when the counter output reaches a predetermined level, the input clock frequency of the counter 7 decreases from f1 to f2, and the rising speed (gradient) of the output data of the counter 7 becomes gentle. Become. At time t10 in FIG. 2, the clock frequency further decreases to f3 in response to the increase in the counter output. If the clock frequency is lowered according to the increase in the output of the counter 7, overflow of the counter 7 when the cycle of the input frequency signal is long can be prevented, and it becomes possible to measure up to an extremely long cycle.

The data conversion circuit 17 is a circuit that converts the cycle data given from the common output line 16 into voltage data, and is composed of a ROM. Various voltage data corresponding to various cycle data are written in advance in the ROM of the data conversion circuit 17, and the voltage data is read by using the cycle data of the common output line 16 as an address signal. The period T is converted into the voltage V according to the following equation.

V = K (1 / T) However, K is a constant. Since 1 / T is a frequency in the above equation, the voltage (digital value) corresponding to the frequency can be obtained from the data conversion circuit 17.

The data (voltage) obtained from the data conversion circuit 17 is converted into an analog voltage value by the digital / analog converter (DAC) 18.

The frequency-voltage converter of this embodiment has the following effects.

(1) If the cycle becomes long (frequency becomes low) even in the middle of one cycle of the frequency signal, the counter value is output from that point, so a value close to the true value without waiting for one cycle Can be obtained.

(2) Forming a pulse of constant width based on the frequency signal,
Unlike the conventional method of averaging with a low-pass filter, RO
Low frequency (long cycle) because the data conversion circuit 17 consisting of M obtains digital voltage corresponding to the cycle.
Can also be measured.

(3) When the cycle of the frequency signal becomes long, the frequency of the input clock of the counter 7 automatically lowers. Therefore, the counter 7 is prevented from overflowing, and the increase in the ROM capacity of the data conversion circuit 17 is suppressed to measure a wide range. It can be carried out.

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) V = (1 /
It may be configured by an arithmetic circuit that performs the operation of T).

(2) The data obtained on the common output line 16 or the output data of the data conversion circuit 17 may be written in the storage device.

(3) The counter 7 may be reset at the trailing edge (falling edge) of the frequency signal pulse shown in FIG. 2 (B) and the clock may be supplied to the latch circuit 9.

(4) A circuit that forms a narrow pulse (trigger pulse) may be added to the output stage of the waveform shaping circuit 2. Further, when a rectangular wave is input, the waveform shaping circuit 2 can be omitted.

[Effects of the Invention] As described above, according to the present invention, data close to a true change in the frequency of a frequency signal can be obtained with good responsiveness.

Further, according to the second aspect, by changing the frequency of the input clock of the counter, the frequency-voltage conversion in the low frequency region becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency-voltage converter according to an embodiment of the present invention, and FIG. 2 is a diagram schematically showing a state of each part of FIG. DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Waveform shaping circuit, 3 ... Oscillator, 4 ... Divider, 5 ... Multiplexer, 8 ... Counter, 11 ... Data combining circuit, 12 ... First data selection circuit, 13 ... Second data Selection circuit, 14 ... Comparison circuit, 15 ... Selection control circuit, 16 ... Common output line, 17 ... Data conversion circuit, 18 ... Digital
Analog converter.

Claims (2)

[Claims] 1. An input terminal for inputting a frequency signal to be converted into a voltage, a clock signal generating circuit for generating a clock signal having a frequency higher than the frequency signal, and a counting input terminal for the clock signal generating circuit. Connected,
A counter having a reset terminal associated with the input terminal so as to be reset every cycle of the frequency signal, and a clock count output obtained from the counter at the end time or start time of each cycle of the frequency signal. A latch circuit for latching, comparing a counter output value obtained at any time from the counter with a latch output value obtained from the latch circuit,
A data synthesizing circuit that selects and outputs the latch output value when the counter output value is smaller than the latch output value, and selects and outputs the counter output value when the counter output value is larger than the latch output value. And a data conversion circuit for converting an output value corresponding to the cycle of the frequency signal obtained from the data synthesizing circuit into a digital voltage value corresponding to the frequency. 2. The clock signal generating circuit is a variable clock signal generating circuit, wherein: an oscillator; a frequency divider that divides an output of the oscillator to generate a frequency-divided output of a plurality of stages; And a control circuit for controlling the multiplexer so as to reduce the frequency of the input clock of the counter in response to the output value of the counter exceeding a predetermined value. The frequency-voltage converter according to claim 1, which is characterized in that.