JPH05276042A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the resolution without increasing number of bits of a flash type A/D converter. CONSTITUTION:A triangle wave is superimposed on an analog input signal at an input terminal 1 and the result is used for an input to the flash type A/D converter 5. The period of the triangle wave is selected to be an integral number of multiple of the sampling period of the flash type A/D converter 5. In order to obtain a mean value of outputs of the flash type A/D converter 5 at a prescribed time interval, outputs of the flash type A/D converter 5 are added At a period of a half of the period T of a triangle wave. An output in a bit number more than the bit number of the flash type A/D converter 5 is outputted from an averaging circuit 6 including full adders 16,17,18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter which can obtain an output with a number of bits larger than a predetermined number of bits by using an analog-to-digital converter (ADC) with a predetermined number of bits.

[0002]

2. Description of the Related Art Typical conventional ADCs are successive approximation type ADCs and double integration type ADCs. The former has a faster conversion speed than the latter,
If the number of bits is increased, the conversion time becomes longer. The latter is extremely long in conversion time and is not suitable for constructing a high speed ADC.

In recent years, a flash type (direct conversion type) ADC is commercially available as an ultra-high speed ADC.
However, since the flash type ADC requires a large number of comparators (for example, 256 bits in an 8-bit ADC), it is inevitably costly to configure it with a large number of bits (for example, a number of bits larger than 8 bits).

Therefore, an object of the present invention is to set the desired number of bits A.
An object of the present invention is to provide an analog-to-digital conversion device which can use DC to obtain an output having a number of bits larger than a desired number of bits.

[0005]

According to the present invention for achieving the above object, an analog / digital converter having a predetermined number of bits, an analog signal input terminal, and a cycle longer than a sampling cycle in the analog / digital converter. And a periodic signal generating means for generating a varying periodic signal, and a signal in which the periodic signal of the periodic signal generating means is superposed on the analog input signal of the analog signal input terminal is formed. An analog-to-digital converter including a signal superimposing means to be supplied to the analog-to-digital converter and an averaging means for averaging the output of the analog-to-digital converter with a predetermined period and increasing the number of bits. Related to. The periodic signal is preferably a triangular wave voltage or a sawtooth wave voltage having a ramp section that linearly increases or decreases. Further, it is desirable that the averaging means is composed of an adding means for adding the outputs of the analog-digital converter in a constant cycle.

[0006]

In the present invention, a signal obtained by superimposing a periodic signal such as a triangular wave or a sawtooth wave on an analog input signal is
It vibrates based on the input signal. Therefore, even if the input signal waveform belongs to the range of the analog signal level corresponding to one bit, the superimposed signal is out of this amplitude range. By knowing the size of the protrusion rate, it is possible to know at which position in the range of the analog signal level corresponding to one bit the waveform of the analog input signal is located. The analog-digital converter AD-converts the superimposed signal with a sampling period shorter than the period of the periodic signal. Therefore, it is possible to know the proportion of the periodic signal that is out of the range of the analog signal level corresponding to the bits in one cycle. The averaging means averages the output of the analog-digital converter in a predetermined cycle and outputs data having a bit number larger than the output bit number of the analog-digital converter. As is apparent from the above, according to the present invention, an increase in the number of AD conversion bits and an improvement in resolution can be achieved by adding a periodic signal generating means and an averaging means. That is, it is possible to achieve an improvement in resolution and an increase in the number of bits without significantly increasing the cost. Further, when the input signal contains noise, an averaging action of this noise occurs and noise can be suppressed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An analog / digital converter according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, this analog-to-digital converter is roughly divided into an analog signal input terminal 1, a clock signal generation circuit 2, a triangular wave generation circuit 3, a superposition (addition) circuit 4, a flash ADC (analog). A digital converter 5 and an averaging circuit 6.

From the analog input terminal 1, a converted analog input signal F as shown in FIG. 2A or FIG.
s (t) is input.

The clock signal generation circuit 2 comprises a clock input terminal 7 to which a 10 MHz clock signal is input, and a counter 8 connected thereto. The clock input terminal 7 is connected to the input terminal of the counter 8 and the ADC 8
Is connected to the clock input terminal CLK. The 1/8 frequency division output terminal C2 of the counter 8 outputs a square wave pulse train having a cycle eight times the cycle of the clock of the clock input terminal 7. The frequency of the clock at this output terminal C2 is 10 /
It is 8 MHz. The output terminals C0 and C1 of the counter 8 are 1
They are a 1/2 frequency division output terminal and a 1/4 frequency division output terminal.

The triangular wave generating circuit 3 includes a series capacitor 9, a resistor 10 for forming an RC filter, and a capacitor 1.
2 and generates a triangular wave having a period T shown in FIG. 2B and supplies it to the superposition circuit 4. The period T of the triangular wave is 8 times the period of the clock of the clock input terminal 7, that is, the sampling clock of the ADC 5. The amplitude of the triangular wave is AD
It is determined to be equal to or larger than the voltage range of the analog signal corresponding to 1 bit of C5.

The superposition circuit 4 is composed of resistors 12, 13, 14 and an operational amplifier 15, and adds the analog input signal shown in FIG. 2A and the triangular wave shown in FIG. The superimposed signal shown in C) is formed. The operational amplifier 1
The non-inverting input terminal of 5 is connected to the ground, the inverting input terminal is connected to the analog input terminal 1 via the resistor 12, and is connected to the triangular wave generating circuit 3 via the resistor 13, and the output terminal of the ADC 5 is It is connected to the input terminal IN.

The flash ADC 5 is a commercially available well-known 8-bit ultra-high speed ADC, and AD-converts the superimposed signal of FIG. 2C at a sampling frequency of 10 MHz. Figure 2
In (C), D1, D2, D3, and D4 represent the data at the time of sampling and are obtained at the period τ. In this embodiment, since the triangular wave Fc (t) is generated at the cycle T which is eight times the sampling cycle τ, eight data are obtained in one cycle T of the triangular wave and four data are obtained in one half cycle. can get.

The averaging circuit 6 includes four memories M1 and M2.
, M3 and M4, three full adders 16, 17, and 18, a latch circuit 19, a decoder 20, and a delay circuit 21, and outputs 10-bit data to an output line 22. The ADC 5 and the memories M1 to M4 have an 8-bit parallel output, the two full adders 16 and 17 have a 9-bit parallel output, the full adder 18 and the latch circuit 19 have a 10-bit parallel output, and the decoder 20 has a 4-bit output. , Which are shown in a single line for simplicity of illustration.

The structure of the averaging circuit 6 will be described in more detail. The input terminals of the four memories M1 to M4 are connected to the ADC 5, respectively. Decoder 20 is 1/2 of counter 8
It is connected to the frequency division output terminal C1 and the 1/4 frequency division output terminal C2 and forms a store control signal for the four memories M1 to M4 and the latch circuit 19. The decoder 20 stores data D1 and D5 in the first memory M1 at times t1 and t5 in FIG.
Is stored and the data D is stored in the second memory M2 at t2 and t6.
The memory M stores 2 and D6, stores the data D3 and D7 in the third memory M3 at t3 and t7, and stores the data D4 and D8 in the fourth memory M4 at t4 and t8.
Controls store (write) control terminals of 1 to M4. Further, the decoder 20 gives a latch control signal to the latch circuit 19 at the timing when t4 and t8 are delayed by the minute delay circuit 21. The first full adder 16 is the 8th memory of the first memory M1.
The bits and the 8 bits of the second memory M2 are added bit by bit to produce a 9 bit output. Second full adder 17
Is 8 bits of the third memory M3 and 8 bits of the fourth memory M4
Bits are added bit by bit to produce a 9 bit output. The third full adder 18 is the first and second full adders 1
The 9-bit outputs of 6 and 17 are added bit by bit to generate a 10-bit output. The latch circuit 19 latches the output of the third full adder 18 at the timing of delaying t4 and t8 of FIG. 3B and outputs a 10-bit output.

Next, the principle of increasing the number of bits (improving the resolution) will be described with reference to FIG. To facilitate understanding, if the analog input signal X + Δx shown in FIG. 3A, which is shown by a horizontal straight line that does not change with time, is supplied to the input terminal 1, and if this is AD-converted only by the flash ADC 5, , 8-bit data corresponding to the analog value X is output regardless of the analog value being X + Δx. That is, ADC
5 is 1 from X-α to x + α centering on the analog value X.
Even if the input changes in the analog signal range corresponding to the bit, different output data are not transmitted and the same value is transmitted, so that the information of Δx cannot be output and the resolution is low. On the other hand, according to the present invention, a triangular wave voltage having an amplitude of the analog signal corresponding to 1 bit of the ADC 5 (2α) or more (preferably in the range of 2α to 4α, more preferably a value slightly larger than 2α) is superimposed on the input signal according to the present invention. ADC5
When the A / D conversion is performed with, the triangular wave is located in one or both of the X + 1 and X-1 regions beyond the range corresponding to X. X-1 area, X area and X + in 1/2 cycle of triangular wave
If the number of data belonging to the area 1 and the ratio of these are calculated, the deviation value Δx from the center value of the area of the actual analog input signal X + Δx can be known. In FIG. 3B, three pieces of data D1, D2, D3 out of the four pieces of data D1 to D4 in a linearly increasing half-cycle section having a positive slope of a triangular wave belong to the X region, and 1 One data D4 belongs to the X + 1 area. Ratio of this number 3: 1
By this, it is possible to know how much the input level of the analog input signal deviates from X. The averaging circuit 6 calculates the average value of 1/2 cycle based on the above principle. Figure 3
In the case of (B), since D1, D2 and D3 are X and D4 is X + 1 respectively, the average value is obtained by the following equation. D1 + D2 + D3 + D4 = 3X + (X + 1) = 4X + 1 When mathematically obtaining the average value, it is necessary to divide the added output value by the sum total of the number of data, that is, 4 Can obtain equivalent information.
The bits that increase corresponding to Δx are full adders 16, 17,
Obtained by carry in 18.

The negative slope half-cycle data D5, D6, D7, and D8 of the superimposed signal of FIG. 3B also contains the same information as the positive slope half-cycle data D1, D2, D3, and D4. Therefore, an average value can be obtained by adding these, and a high resolution output (high bit output) can be obtained in the same manner.

Eight memories are provided in place of the memories M1 to M4, the data D1 to D8 shown in FIG. 3B are stored respectively, and these outputs are input to four full adders. Next, the outputs of the four full adders are input to the two full adders, the outputs of the two full adders are input to one full adder, and a total of seven full adders are used, as in FIG. It is also possible to obtain the addition output and latch the addition output (the output indicating the average value) by the delay signal of t8 to obtain the 11-bit output. It is also possible to set the number of samplings in the positive slope section and the negative slope section of the triangular wave to a plurality of times different from four. For example, if sampling is performed 8 times in a half cycle (T / 2), an 11-bit output can be obtained.

FIG. 4 shows a waveform in which an 8-bit output AD-converted only by the ADC 5 without the superposition circuit 4 and the averaging circuit 6 according to the present invention is restored to an analog signal by a 12-bit DA converter. As is clear from this waveform, the conventional method has a high step and has a poor resolution. on the other hand,
The waveform obtained by converting the output of the apparatus of FIG. 1 into an analog signal by a 12-bit DA converter is shown in FIG. 5, and the resolution is greatly improved. If the number of bits of the flash type ADC 5 is increased, the resolution will of course be increased, but as described above, the number of comparators will be increased and the cost will be increased. On the other hand, in the present embodiment, it is possible to achieve high resolution (high bit) by using a commercially available ADC 5 of relatively low cost without adding a comparator. Since the circuit parts other than the ADC 5 of FIG. 1 are relatively simple circuits and are easy to be integrated into an IC, the cost increase due to the addition thereof is small.

In this embodiment, the data D1 to D4 or D5
Since the average value is calculated by adding ~ D8, the conversion time is T /
2, which is four times the unit conversion time τ of the ADC 5. However, since an 8-bit flash type ADC of about 100 Msample / sec can be obtained, it is possible to output data to the output stage of the latch circuit 19 at a speed of about 12.5 Msample / sec, which is practically almost impossible. There is no problem.

Since the present embodiment is a method of obtaining the average value of the output of the ADC 5, it is possible to obtain the effect of averaging (cancelling) the noise contained in each sample of the ADC 5.

The waveform added to the input signal is not limited to the triangular wave, but may be a sawtooth wave as shown in FIG.
In this case, the ADC output data D1 to D8 in the interval of one cycle T of the sawtooth wave are added to obtain an average value. Further, a signal having various periodicity similar to a triangular wave or a sawtooth wave can be superimposed on an analog input signal and AD-converted. Further, a triangular wave or a sawtooth wave can be formed into a stepped wave shape based on a digital signal and added to the superposition circuit 4.

[Brief description of drawings]

FIG. 1 is a block diagram showing an analog-digital conversion device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a state of each part of FIG.

FIG. 3 is a waveform diagram for explaining the principle of AD conversion by the apparatus of FIG.

FIG. 4 is a waveform diagram obtained by DA converting the output of a conventional AD converter.

FIG. 5 is a waveform diagram in which the AD conversion output of the embodiment is DA converted.

FIG. 6 is a waveform diagram showing a sawtooth wave.

[Explanation of symbols]

 3 Triangular wave generation circuit 4 Superposition circuit 5 Flash type ADC 6 Averaging circuit

Claims (3)

[Claims] 1. An analog / digital converter having a predetermined number of bits, an analog signal input terminal, and a periodic signal for generating a periodic signal that changes with a period longer than a sampling period in the analog / digital converter. Generating means, signal superimposing means for forming a signal obtained by superimposing the periodic signal of the periodic signal generating means on an analog input signal of the analog signal input terminal, and supplying the signal to the analog-digital converter, An analog-to-digital converter comprising an averaging means for averaging the output of the analog-to-digital converter with a predetermined period and increasing the number of bits. 2. The analog-digital converter according to claim 1, wherein the periodic signal is a triangular wave or a sawtooth wave. 3. The analog-digital conversion device according to claim 1, wherein the averaging means is an adder circuit that adds the outputs of the analog-digital converter in a constant cycle.