JP3230227B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a configuration of a conventional A / D converter. The analog signal is input to the adder 1, added to the signal output by the multi-bit D / A converter 11, supplied to the integration circuit 2, and integrated.
The output of the integration circuit 2 is input to the adder 4 via the buffer amplifier 3 and is added to the output of the D / A converter 11. The output of the adder 4 is input to the integration circuit 5, integrated, and then input to the adder 7 via the buffer amplifier 6.

An adder 7 adds an input signal from the buffer amplifier 6 and a signal from the D / A converter 11, and
Output to the integration circuit 8. The integration circuit 8 integrates the input signal and outputs the integrated signal to the multi-bit simultaneous comparison A / D converter 9. The A / D converter 9 compares the input analog signal with a plurality of predetermined reference levels at the same time, and outputs a digital signal of a plurality of bits.

The output of the A / D converter 9 is supplied to the delay circuit 1
After being delayed by one sample by 0, it is input to the D / A converter 11 and D / A converted. The output of the D / A converter 11 is fed back to the adders 1, 4 and 7, respectively.

[0005] As a result, oversampling A / D conversion using a so-called ΔΣ modulator is performed, and the digital signal output is filtered by a digital decimation filter (not shown) at the subsequent stage to obtain, for example, 16-bit digital data. Can be obtained.

The A / D converter 9 and, therefore, the D / A converter 11 is configured not to have a plurality of bits but to have one bit, so that the digital output is +1 or -1 and ΔΣ
When the modulator has a second or higher order configuration, the input level of the analog signal increases, and the corresponding digital signal output approaches +1 or -1 (when the modulation rate of the ΔΣ modulator approaches 1, ), The signal waveform is distorted. Therefore, as disclosed in, for example, U.S. Pat. No. 4,851,841, a good digital signal of full scale (± 1) cannot be obtained unless the gain is set to a value of 1 or more in the digital decimation filter at the subsequent stage.

[0007] However, as shown in FIG.
If converter 9 and, therefore, D / A converter 11 have a multi-bit configuration, the ΔΣ modulator will be stable and have a higher S
/ N can be obtained.

That is, if the quantization bit in the A / D converter 9 is not one bit, the accuracy of the bit becomes a problem. Even if there is an error in the A / D converter 9, the error is corrected. In addition, since the ΔΣ modulator operates, the accuracy of the overall oversampling A / D converter is not affected.

[0009]

However, in a conventional A / D converter, a D / D for feedback is used.
As the A / A converter 11 uses a resistance-divided D / A converter of the R-2R type or the like, errors occur due to variations in resistance values and changes with time.
The error of the A / D converter 9 is compensated by the action of the ΔΣ modulator, but the error of the D / A converter 11 is not compensated by the action of the ΔΣ modulator, and the error remains unchanged for the entire A / D converter. An error occurs, and S / N deteriorates.

The present invention has been made in view of such a situation, and aims to obtain a better S / N.

[0011]

According to the present invention, there is provided an A / D converter comprising an integrating means for integrating an input signal;
The output is set to the specified frequency with the sampling clock of the specified frequency.
A / D that outputs a digital signal in comparison with the reference level of
Conversion means and a sampling clock in the A / D conversion means.
A / D with sampling clock of higher frequency than
A first signal corresponding to the analog signal output by the conversion means;
Generating means for generating a second signal and a second signal;
Holding means for holding a first signal and a second signal,
The difference between the first signal and the second signal held by the means.
Calculation means for calculating and feeding back to the integration means.
Characterized in that it obtain.

The output of the integration means is supplied to the A / D conversion means.
A plurality of predetermined reference levels are compared at the same time to output a digital signal of a plurality of bits.
Absolute value conversion means (for example, two's complement decoder 54 in FIG. 1) for converting the output of the D conversion means into a value whose absolute value is greater than 1 can be further provided.

[0013]

[0014]

In the A / D converter having the above structure, the output of the simultaneous comparison type A / D converter 46 is converted into a PWM signal by the PWM / D / A converter 60, and the integration circuit 3
5, 40, and 45 are fed back. Therefore, S /
N can be further improved.

[0015]

FIG. 1 is a block diagram showing the configuration of an embodiment of an A / D converter according to the present invention. In this embodiment, the integrating circuits 35, 40, and 45 are cascaded in three stages.
In addition, the input signal and the feedback signal are
1, 32, 36, 37, 41, 42,
It is designed to be integrated. The integrating circuit 35 includes an operational amplifier 33 and a capacitor 34, the integrating circuit 40 includes an operational amplifier 38 and a capacitor 39, and the integrating circuit 45 includes an operational amplifier 43 and a capacitor 44.

The output of the integrating circuit 45 is a simultaneous comparison type A / D
It is input to a converter 46. The simultaneous comparison type A / D converter 46 includes three comparators 51, 52, 53
And voltage dividing resistors 47 to 50 for supplying a predetermined reference potential to these comparators. The resistors 47 to 50 have the same resistance value, and the reference voltage supplied to the comparators 51, 52, 53 is a value obtained by dividing the predetermined voltage V to 1/4, 1/2, or 3/4, respectively. It has been.

The outputs of the comparators 51 to 53 are supplied to a two's complement decoder 54 and converted into two's complement data, and then output as A / D conversion output via a register 55 to a circuit (not shown) (not shown). Digital decimation filter).

The outputs of the comparators 51 to 53 are supplied to a PWM / D / A converter 60.
The PWM / D / A converter 60 includes a comparator 5
PWM decoder 56 for converting the outputs of 1 to 53 into PWM signals, shift registers 57 and 58 for sequentially holding the outputs of PWM decoder 56, and shift registers 57 and 58
, And a differential amplifier 59 that calculates the difference between the outputs. The output of the differential amplifier 59 is supplied to the integrating circuits 35 and 4 via the resistors 61 and 32, 37 and 42, respectively.
The feedback is made to 0,45.

The clock generation circuit 71 has a clock CK1.
And CK2, and the clock CK1 is used as the simultaneous comparison type A /
The clock CK2 is output to the D / A converter 60 and the complement decoder 54 of the D converter 46 and the D / A converter 60. The frequency of the clock CK2 is four times the frequency of the clock CK1. That is, in the PWM / D / A converter 60, oversampling is performed.

Next, the operation will be described. The input analog signal is added to the feedback signal output from the differential amplifier 59 via the resistors 31 and 32, and is integrated by the integration circuit 35. The output of the integration circuit 35 is
The feedback signal is added via the resistors 36 and 37, input to the integration circuit 40, and integrated. Integration circuit 4
0 is the output of the differential amplifier 59 and the resistance 41
And 42 are added to each other, input to an integration circuit 45, and integrated.

The analog signal output from the integration circuit 45 is
It is supplied to the non-inverting input terminals of the comparators 51 to 53 of the simultaneous comparison type A / D converter 46. Comparator 5
The inverting input terminals 1 to 53 respectively have V / 4 and V /
A reference voltage of 2, 3 V / 4 is supplied.

Therefore, when the level of the analog signal output from the integrating circuit 45 is larger than 3V / 4, all the outputs C0, C1, C2 of the comparators 51 to 53 become 1 respectively. Analog signal level is V / 2 to 3V /
4, the output C2 of the comparator 53 becomes 0, and the outputs C1 and C1 of the comparators 52 and 51 become zero.
C0 is 1 each. When the level of the analog signal is in the range of V / 4 to V / 2, the outputs C2 and C1 of the comparators 53 and 52 become 0, and the output C0 of the comparator 51 becomes 1. Furthermore, when the level of the analog signal is smaller than V / 4, the outputs C2, C1 and C0 of the comparators 53 to 51 are all 0.

That is, the outputs (C2, C1, C0) of the simultaneous comparison type A / D converter 46 are (111), (01)
1), (001) or four-valued digital data (000).

The two's complement decoder 54 converts this digital data into +3, +1, -1 or-, as shown in FIG.
The value is converted to a 3's two's complement value and output to the register 55.

That is, the outputs (C2, C1, C0) of the simultaneous comparison type A / D converter 46 are (111),
When (011), (001) or (000),
The output (Q2, Q1, Q0) of the two's complement decoder 54 is
(011) (+3), (001) (+1),
(111) (-1) or (101) (-3).

On the other hand, P of the PWM / D / A converter 60
The WM decoder 56 includes a simultaneous comparison type A / D converter 46.
The three-bit data output from the comparators 53, 52, and 51 are converted into two PWM signals P and N as shown in FIG.
And output.

That is, the comparator outputs (C2, C1, C
When (0) is (111), the output of the first to fourth phases of the P signal of the PWM signal is (0000), and the N signal is (1110). When the comparator output (C2, C1, C0) is (011), PW
The P signal of the M signal is (1000), and the N signal is (11).
00). In addition, comparator outputs (C2, C
When (1, C0) is (001), the P signal of the PWM signal is (1100), and the N signal is (1000). Further, when the comparator output (C2, C1, C0) is (000), the P signal of the PWM signal is (111).
0) and the N signal is (0000).

Of the PWM signals output from the PWM decoder 56, the P signal is transmitted through the shift register 57,
The N signals are sequentially input to the differential amplifier 59 via the shift register 58, respectively. The differential amplifier 59 outputs the difference (P−N) between the P signal and the N signal input to the non-inverting input terminal and the inverting input terminal via the shift registers 57 and 58.
To generate a PWM signal as shown in FIG.

That is, when the P signal is (0000) and the N signal is (1110), a PWM signal having a level of (-1, -1, -1,0) in the first to fourth phases is obtained. , P signal is (1000) and N signal is (110).
0), it becomes a PWM signal of (0, -1, 0, 0). When the P signal is (1100) and the N signal is (1000), the PW of (0, +1, 0, 0)
When the M signal, the P signal is (1110), and the N signal is (0000), the PWM of (1,1,1,0)
Signal. This +1 is + 5V, -1 is -5V,
0 can correspond to each level of 0V.

As described above, the clock CK2 supplied to the PWM / D / A converter 60 is a synchronous comparison A /
D converter 46, two's complement decoder 54, register 5
4 times the frequency of the clock CK1 (1/4)
), The signal for one cycle (the first to fourth phase signals) is fed back to the integration circuits 35, 40, and 45. Therefore, in these integration circuits,
The average value of the PWM signal will be integrated.

As described above, the feedback D
Since the accuracy of the / A converter 60 is determined in accordance with the time axis of the clock, processing such as trimming when using a conventional resistor is not required, and a highly accurate A / D converter can be realized. Become.

Also, the A / D converter 46, and thus the D
Since the / A converter 60 has a multi-bit configuration, the A / D conversion operation can be stably performed, and a high S / N can be realized at a lower oversampling rate.

Further, the maximum (absolute value) output of the A / D converter 46 is set to ± 1 ((001) or (11)
1)), not ± 3 ((011) or (101))
Therefore, even if the ΔΣ modulator has a second or higher order configuration and the gain of a digital decimation filter (not shown) at the subsequent stage is 1 or less, ± 1
Within this range, digital data without distortion can be obtained. Therefore, by substantially using only the digital data within the range of ± 1, it is possible to obtain data without distortion even at full scale (± 1).

[0034]

As described above, according to the A / D converter of the present invention, the PWM signal corresponding to the analog signal output from the A / D conversion means is generated and supplied to the integration means. With a simple configuration, a high S / N can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an A / D converter of the present invention.

FIG. 2 is a diagram illustrating input and output of each unit in the embodiment of FIG.

FIG. 3 is a block diagram illustrating a configuration of an example of a conventional A / D converter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 adder 2 integration circuit 3 buffer amplifier 4 adder 5 integration circuit 6 buffer amplifier 7 adder 8 integration circuit 9 multiple-bit simultaneous comparison type A / D converter 10 delay circuit 11 multiple-bit D / A converter 35, 40, 45 integration Circuit 46 Simultaneous comparison type A / D converter 51 to 53 Comparator 54 Two's complement decoder 55 Register 56 PWM decoder 57, 58 Shift register 59 Differential amplifier 60 PWM D / A converter 71 Clock generation circuit

Claims (2)

(57) [Claims] And 1. A integrating means for integrating an input signal, the output of the integrating means, a sampling clock of a predetermined frequency, and A / D converting means with a predetermined reference level, and outputs a digital signal, the From sampling clock in A / D conversion means
A / D conversion with high frequency sampling clock
A first signal corresponding to the analog signal output by the means;
Generating means for generating the second signal, the first signal and the second signal output by the generating means.
Holding means for holding the signal, the first signal held by the holding means,
Calculate the difference between the two signals and feed it back to the integrating means
An A / D converter, comprising: 2. The A / D conversion means compares the output of the integration means simultaneously with a plurality of predetermined reference levels, outputs a digital signal of a plurality of bits, and outputs the output of the A / D conversion means. 2. The A / D converter according to claim 1, further comprising absolute value conversion means for converting the absolute value into a value larger than 1.