JPS6166411A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain a monolithic A/D converter with high speed, high accuracy, low power consumption and low cost by using a subtraction circuit whose accuracy of gain is not required so as to connect a parallel A/D converter and a cascade A/D converter. CONSTITUTION:A high-order m-bit of an analog input signal from a terminal 1 is subject to digital coding by the parallel A/D converter 2. The coded signal is inputted to an output buffer 6, converted into an analog signal by a D/A converter 3 and inputted to a subtraction circuit 5, where the said signal is subtracted with an output from a sample-and-hold circuit 4, the low-order n-bit is coded by the cascade A/D converter 8 and the result is outputted from an output buffer 12. Since the output amplitude has only to by symmetry to 0V in the circuit 5 and it is not required to match the gain strictly, the A/D converter with high accuracy is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an A/D converter, and particularly to a structure of an A/D converter suitable for high-speed, high-precision monolithic conversion at or above the video band.

Conventional configurations and their problems In recent years, digital processing of video signals has progressed, and there has been a demand for lower power consumption, lower prices, and more compact A/D converters as key devices.

In order to meet this condition, it is necessary to implement a monolithic structure, and conventional monolink structure video A/D converters have been mainly of the so-called parallel type with a built-in comparator (N is the resolution). However, as mentioned above, this parallel type requires 2N comparators, so the limit is about 10 bits (requiring 1,024 comparators); becomes 4,096
This requires individual comparators, which is no longer possible.

On the other hand, there is a conversion method called the successive approximation method, but this method repeats processing for the number of bits before converting one sample point to a digital signal.
The clock frequency needs to be N times the sampling frequency (N is the resolution). Therefore, if we consider the video band and set the sampling frequency to 20 MHz, in the case of 12 bits, a clock of at least 240 MHz is required, which is quite difficult to implement. Also, the settling time of the internal D/A converter is 1nse.
c is required, making it difficult to achieve high accuracy.

Therefore, a promising method is called the series-parallel method, in which two or more parallel A/D converters are connected in series.For example, in the case of 12 bits, a two-stage configuration of 6 bits each is used. , the number of comparators is 2X26=
Only 128 circuits are required, which significantly reduces power consumption.
This is also possible in terms of the degree of integration as an IC.

Furthermore, since the clock that drives the entire circuit can be the same as the sampling frequency, it has the advantage that it is relatively easy to achieve high speed.

However, a drawback of this series-parallel system is that there is a problem in the accuracy of the joints between stages. FIG. 1 shows a block diagram of this series-parallel type A/D converter, and its operation and problems will be explained.

In Figure 1, 101 is an analog input terminal, 102 is a high-order bit A/D converter, and MSB (most significant bit)
This is a parallel A/D converter that performs m-bit A/D conversion from . 103 is a digital output terminal for upper m bits, and 104 is an m-bit D/A converter for converting this upper m bit digital signal back into an analog signal.

105 is a delay circuit, 106 is a subtraction circuit, 107 is a lower n
This is a parallel A/D converter that performs bit A/D conversion. 108 is an output terminal for the lower n bits.

Next, the operation will be explained. First, the analog signal applied to the terminal 101 is sent to the A/D converter 10 of the upper m bits.
A/D conversion is performed in step 2. This output is directly output from the terminal 103 as a digital signal for the upper m bits, and is also input to the m-bit D/A converter 4, where it is reproduced again into an analog signal. On the other hand, the analog input signal is input to the delay circuit 105, and the upper pin) A/D converter 102
The signal is delayed by the D/A converter 104 by a time equal to the delay time of the signal, and is applied to the subtraction circuit 106. In the subtraction circuit 106, the output of this delay circuit and the D/A
Subtraction is performed between the output signals of the converter 4. That is, the result of subtraction between the analog original signal and the reproduced signal of the upper m bits,
The analog signal for the remaining lower n bits is sent to the subtraction circuit 106.
appears in the output of This signal is converted into a digital signal by an A/D converter for the lower n bits to produce a digital signal for the lower n bits.

As mentioned above, this series-parallel type A/D converter is
Although the configuration is relatively simple and it is easy to increase the speed, the major problem is that the accuracy of the 106 subtraction circuits must be within the bit size, and usually the parallel A/A of the lower bits is
In order to widen the input dynamic range of the D converter 107, the subtraction circuit 106 is given a gain of v- times, but the accuracy of this gain and the A/D converter 10 for lower bits are
It is necessary to improve the accuracy of the 70 input DC level to below the bit size. However, it is difficult to achieve these improvements in precision in a monolithic IC without adjustment, and requires external adjustment or trimming to obtain precision, making it impossible to realize a low-cost A/D converter.

Purpose of the Invention Therefore, in order to solve such conventional problems, the present invention uses a parallel type A/D converter for the upper bits and a cascade type A/D converter for the lower bits, and improves the gain accuracy between them. By connecting signals using unnecessary subtraction circuits, conventional fully parallel, series-parallel, or fully cascaded A/
The purpose of the present invention is to provide a monolithic A/D converter that has high speed, high precision, low power consumption, and low cost, which cannot be achieved with a D converter.

Structure of the Invention The present invention is a parallel type A/D that encodes the upper m bits.
Near 7/: L/-event, this parallel type A/D
An m-bit D/A converter that regenerates the converter output into an analog signal, a delay circuit that delays the analog input signal, and a differential amplifier that subtracts the outputs of the D/A converter and delay circuit to create a difference signal. A subtraction circuit composed of circuits and a lower n
A configuration that includes a cascaded A/D converter that encodes bits, and a reference voltage generation circuit formed by the same differential amplifier circuit as the subtraction circuit, whose output is the reference voltage input to the first stage of the cascaded A/D converter. This makes it possible to manufacture a monolithic A/D converter that is faster than the video band, has high precision, and has low power consumption.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows the basic configuration of an A/D conversion device in an embodiment of the present invention.

In FIG. 2, 1 is an analog input terminal, 2 is a parallel A/D converter that encodes the upper m bits, 3 is an m-bit D/A converter, 4 is a sample and hold circuit that functions as a delay circuit, and 5 6 is an output buffer for the upper m pinpoints, and 7a is a subtraction circuit.

7b is an output terminal for the upper m bits, 8 is a cascade type A/D converter that encodes the lower n bits, 9 is a reference voltage input terminal, and 10a, 10b, and 10c are folding circuits each having n-1 stage cascade. It is connected.

Comparators 11a, 11b, and 11C111d are provided in n numbers. 12 is an output bannofer for lower n bits, 13
a, 13b, and 13C113d are output terminals for the lower n bits, respectively.

As can be seen from the figure, the input signal is input to a parallel A/D converter and a sample-and-hold circuit, and the output of the parallel A/D converter is outputted via the output vanofer of the upper m bits. Connected to A converter. The two inputs of the subtraction circuit are connected to the output of the D/A converter and the output of the sample-and-hold circuit, and the output is the lower n
It is input to the folding circuit at the first stage of the cascade type A/D converter that encodes the bits. The other input terminal of the first-stage folding circuit is connected to a reference voltage terminal, and the second-stage folding circuit and subsequent stages are cascade-connected to the first-stage folding circuit. The comparators are connected to the inputs of each stage and the output of the final stage of the folding circuit, and the outputs of these comparators are outputted via the output buffer 7 of the lower n pins.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, an analog input signal input from terminal 1 is converted into a digital signal with its upper m bits encoded by an m-bit parallel A/D converter. The upper m bits of the digital signal are outputted via the output buffer 6.

On the other hand, the output of the parallel A/D converter 2 is m-bit D/D/
The A converter 3 regenerates it into an analog signal. The accuracy at this time is (m1n) bits. The analog input signal is, on the other hand, input to the sample and hold circuit 4, where it is delayed in the same way as the signal delay shifted by the parallel A/D converter 2 and D/A converter 3.
The phase of the output signal of the D/A converter 3 and the phase of the output of the sample/hold circuit 4 are aligned. Next, when the subtraction circuit 6 takes the difference between these two signals, the amplitude of this signal becomes the maximum bit size (=V, n/2") of the high-order m bits of the parallel A/D converter, and this signal By performing A/D conversion of n more bits, it is possible to complete A/D conversion of m+n bits in total.Therefore, the output of the subtraction circuit 6 is converted into a cascade type A/D converter that encodes the lower n bits.
It is input to converter 8.

Here, the operation of the cascade type A/D converter 8 will be explained. As shown in FIG. 2, the n-bit cascaded A/D converter 8 has n-1 stages of cascaded folding circuits I.
It consists of Qa~10c and n comparators 11a~11d. The folding circuit is configured to have input/output characteristics as shown in FIG. In other words, the relationship between input A and output B is that as input signal A increases, output A increases with a gain of 1 up to % of the input dynamic range, and conversely decreases after that, as shown in the figure. The characteristics are as follows. - force output B is complementary to output A; Input B forms a differential input with input A.

If folding circuits with such characteristics are connected in cascade, an analog signal is input to one input of the first stage, and a voltage of % of the full range of the analog signal is applied as a reference to the other differential input, the input signal Each time the signal passes through a folding circuit, the signal is folded back, and a predetermined polarity relative to the reference voltage of the first stage is generated at the output point of each folding circuit. Therefore, when these signals are compared by the comparators 11a to 11d, a coded output can be obtained by converting the signals to 0, that is, the lower n bits.

As explained above, in the A/D converter of the embodiment, the upper m bits are processed by the parallel A/D converter, and the lower n bits are processed by the parallel A/D converter.
The bits will be converted by a cascade type A/D converter. What should be noted here is that the gain of the subtraction circuit 6 does not need to be exact. Now, suppose that the output of the subtraction circuit 5 is set to Ov when the two inputs match, and has bipolar output characteristics depending on the magnitude of the input, and the reference voltage is also set to Ov. On the other hand, the relationship between the input signal and the reference voltage of the cascade type A/D converter 8 is sufficient if the reference voltage is a voltage of % of the full scale of the input signal, and the magnitude of the input amplitude does not matter. Therefore, it is sufficient that the output amplitude of the subtraction circuit 6 is also positive and negative symmetrical about oV, and the strictness of the gain is not critical.

Next, a subtraction circuit and a reference voltage generation circuit in an embodiment of the present invention will be explained. FIG. 4 shows an embodiment of the subtraction circuit according to the present invention.

In FIG. 4, blocks A and B are the same differential amplifier circuit, block A is a subtraction circuit, and block B is a reference voltage generation circuit. 21゜22 are differential input terminals,
23 is an output terminal, 24 is an output terminal, and 25 is a power supply.

26, 27, 32° 33 are load resistors, 28.29 and 34.35 are differential transistor pairs, 30, 3
1.36.37 is an electric feedback resistor for gain adjustment, 38 is a reference input voltage source, and 39.40 is a constant current source.

The output terminal of the D/A converter 3 in FIG. 2 is connected to 21 in FIG. The output terminal 24 will be connected to the input terminal of the converter 8 and to the reference voltage terminal 9 of FIG.

Next, the operation of the circuit shown in FIG. 4 will be explained using the characteristic diagram shown in FIG. Difference input signal v1n=(v2
1-v22), an output voltage appears at the output 23 in accordance with the input/output characteristic straight line shown by the solid line in FIG. Furthermore, if the differential circuit of block B is constructed of elements having the same characteristics as the differential circuit of block A, block B will have the same input/output characteristics as block A. Here, if a voltage of % of the maximum input voltage of block A is applied to the differential input voltage of the differential circuit of block B, as shown in FIG.
4 voltage V. u, 24 is the output voltage V of 23. % of the maximum value of U23. Therefore, the voltage of the voltage source 38 is now set to the bit size (
LSB), that is, %LSB, the full scale output of the subtraction circuit is 1LsB, so the cascade type A
The reference voltage input to the /D converter 8 is 1/2 of the full scale of the input signal. Moreover, block A and block B
are formed of exactly the same circuit, so if they are integrated into an integrated circuit, their characteristics will almost match, and the above relationship will always be maintained, so there is no need to precisely match the gains of the subtraction circuits. .

Effect of the invention The effects of the present invention will be described below.

(2) As described in the description of the embodiment, since it is not necessary to precisely match the gain of the subtracting circuit, the design of the subtracting circuit is easy, and a highly accurate A/D controller can be realized.

■ Since the upper bits are processed by a parallel type A/D converter, compared to forming all bits in series, it is faster and easier to increase the precision of the upper bits, making it possible to use a high-resolution A/D converter. A converter can be realized.

■ Combines the small number of elements, which is a feature of a cascaded A/D converter, with the high speed of a parallel A/D converter.
A monolithic A/D converter with low power consumption and high speed can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional serial-parallel A/D converter, Fig. 2 is a preliminary block diagram illustrating an embodiment of the present invention, and Figs. Explanatory diagram of input/output characteristics of a folding circuit used in an A/D converter, No. 4
The figure is a circuit diagram showing one embodiment of the subtraction circuit and reference voltage generation circuit of the present invention, and FIG. 5 is a diagram illustrating the characteristics of the subtraction circuit and reference voltage generation circuit of the present invention. 2... Upper bit parallel type A/D converter,
3...D/A converter, 4...Sunflue hold circuit, 6...Subtraction circuit, 8...
...Cascade type A/D converter for lower bits, 10a
, 1 ob, 10a... loopback circuit, 11&, 11b, 11C911d... comparator. Name of agent: Patent attorney Toshio Nakao and one other person
2 Figure 3

Claims (2)

[Claims] (1) A parallel A/D converter that encodes the upper m bits, an m-bit D/A converter that regenerates the output of the parallel A/D converter into an analog signal, and delays the analog input signal. A subtraction circuit including a delay circuit, a differential amplifier circuit that subtracts the output signals of the D/A converter and the delay circuit to create a difference signal, and a plurality of folding circuits provided continuously to the subtraction circuit. A cascade form A/ encoding the lower n bits consisting of and a comparator
A D converter and a reference voltage generation circuit formed of the same differential amplifier circuit as the subtraction circuit and whose output voltage is used as a reference voltage of the first-stage folding circuit of the cascaded A/D converter. A/D conversion device. (2) A according to claim 1, characterized in that a voltage corresponding to 1/2 of the bit size of the parallel A/D converter is applied as the differential input voltage of the reference voltage generation circuit. /D conversion device.