JPS58104525A - Analog-to-digital converter circuit - Google Patents

Abstract

PURPOSE:To eliminate errors at a joint between lower-order and upper-order bits, by forming a reference voltage of a converter for the lower-order bit based on the output of a converter for the upper-order bit and providing an offset corresponding to the upper-order bit for this reference voltage. CONSTITUTION:A 3-bit parallel A/D converter 1 converts an analog input signal Vin into 3-bit digital signals H2-H6. In this case, a 68V upper limit reference voltage is applied to the converter 1 from a reference power supply 2 and a 4V lower limit reference voltage from a reference power supply 3. The signals H2- H0 are applied to a D/A converter 4, where the signals are converted into an analog voltage V4 having a value equal to 8 times the signals except for H2- H0=(111) and the analog voltage is applied to a converter 5 as a lower limit reference voltage. The V4 is offset at a DC power supply by 2 LSB of the signals H2-H6, i.e. 16V to from an analog signal V6, which is applied to the converter 5 as a upper limit reference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The Aa mu/D converter includes a parallel type and a series/parallel type.

However, with a covered A/D converter, when converting an analog input voltage to a digital output of 1/n pinpoints, (2
For example, in the case of m-8, a 2551i voltage comparison circuit is required, which increases the number of elements, increases power consumption, and increases I
When converted to C, the chip size becomes large.

On the other hand, in a series-parallel type A/D converter, the number of voltage comparison circuits may be 2 (2"" -1), for example, if the ratio is 8, the number of voltage comparison circuits may be 30. Therefore, power consumption can be reduced and K , the chip size when integrated into an IC can also be reduced. However, in Jin's [parallel type A/D converter, the upper focus and lower bit of the digital output are obtained by separate λ/D conversion. When the value increases, the digital output does not increase monotonically, but shows dips and peaks.

This invention aims to improve the accuracy of this series-parallel A/D converter.

An example of this will be explained below. In this example, the digital output Ds = Do K ) of the analog input terminal Vint/Pinto is subjected to t/D conversion. In addition, the human power voltage Vin is θ~64 (V), and 1
It is assumed that [v] corresponds to 1L8BK of digital output, ,D,.

In FIG. #11, an analog input voltage Via is supplied to a 3-pin I1 type A/D converter (1)K, and 3-bit digital signals H2-no are output.

However, in this case, this converter (11 is supplied with the reference voltage for the upper limit of 611 [V) from 1 quasi voltage * i21, and the reference voltage for the lower limit of 4 [■] from 1 reference kick pressure #f3). is supplied. That is, the converter (
1) should originally be 114, corresponding to the input voltage VinK.
(V) and 0 [V] reference voltages should be supplied, but an offset of 4 [V] is given to these reference voltages.

Therefore, the input voltage v1 and the signal H1-4 are
A, B [as shown, signals H2 to HO#] LSIi corresponds to input terminal Vin 8 [■], and signals H2 to HO#
Ho is offset by -IJB.

Then, these signals H2 to Ho are sent to the D/mu converter (4).
K is supplied and as shown in the third factor %H2~)io-'''
9 analog voltages V4KD/M with a value equal to 8 times the value of the signals H2 to Ho except for "1ll" and "11" are converted, and this voltage V4 is converted into a 4-bit parallel layer M/D converter (51 has a lower limit value). Supplied as a reference voltage.

In addition, the voltage V4 is kg to m (signals H1 to H from 67K).
2L8B of 0, that is, 16[Vl is offset to form an analog voltage v with the relationship shown in FIG. Supplied as.

Then, the input voltage Via is supplied to the converter (5) through the delay 1g circuit (7) for compensating for phase C (time lag), and 4-bit digital signals L3 to Lo are taken out.

The signals H1-)io and L1-Lo are connected to the correction circuit (8).
), and as shown in Fig. 4, the focus Ho and Ls
The signal H! ~Peng and L3~Lo
are fully added and 6-bit signals Di to Do are extracted.

? :, f) At 15ft mklt, H,t kl
Assume that Win = 25.5 (V). Then, from stripes A and B, H2~Ho! E'''O1O'' and then from K1831m V4==Muro (V).

V・-32 [Vl. Then, in the converter (57), the input voltage Vin is converted into signals @L3~Lo using this voltage v4.v as a reference voltage, so at this time, the voltage Vjn and the signals L3~Lo The relationship between the two is shown in Figure 2 A and C.

In other words, if converter (5) simply performs 4-pin A/D conversion, the reference voltage of converter (5) is 4 bits, so it is O (V) and 16 (V), but in this case The reference voltages are 1a (V) and 3
2 (V) is offset by 16 (V), so from the converter (5)'s perspective, Vizen = 25.
5-141=9.5 (Vl.

Since 95='''1001'' (fraction is rounded down), L3-LO-'1001' is obtained.

The signals H2 to Ho and L3 to Lo are connected to the correction circuit (8
) is fully added as shown in FIG.

Also, if Vin −so,s (V), then $
Figure 2 A, B color H9 ~ HQ = @101”K, and from Figure 3 v4 = 40 [Vl, V
s = 56 (V). Therefore, the converter (5
) means that the reference voltage is offset by 40 [Vl, so from the perspective of Compa-I (5), it is Vin -5
0,5-40=IO,5(V) Te'jb Luca P:s,
It becomes L3~Lo-'101o''.

And like this, KH2~Ho="lOI'", L3~
L.

= "1010", K is ~D from Figure 4.

= "110010" (=50) is obtained.

When the input voltage Vin is at another level, a voltage equal to the voltage V4 K acts as an offset voltage of the converter (5), and the 6-bint digital output D5 to D
o is taken out.

In this way, according to the present invention, A/D conversion can be performed, but in this case, especially according to this output, the outputs H8 to H0 of the converter (3) for the upper focus are used for the lower focus. Compa-# (5) no jijllll & pressure v4
．． This reference voltage ■4°V, K
gives an offset corresponding to the upper focus, so
High-precision A/D conversion can be performed without causing a link FAK error between the upper bit and the lower focus.

Also, since the 6-pin digital output ~Do is obtained from the 7-bit signals H8~Ho and L3~L, that is, it has 1 pin redundancy, and the lower pins Ls-Lo "oooo~" 1111″ is the upper biy) Hl ~
Since it is compatible with HO's 2-stencil 7', even if there is some damage to the A/D f conversion of the converter 11J or the reference voltage of the voltage source +21, f3), the digital outputs D1 to D
ot) 8 degrees can be made higher.

In addition, the above-mentioned smell [is converter (5) K Ili
The difference between the reference voltages (4) and (8) is 16 (V), but this value can be set to any value by, for example, providing the uniform circuit (7) with a gain, and the converter ( 5) The sensitivity can be increased.

In addition, when the signals H2~H@#Lj~L do not have redundant bits, the converter (5) is set to 3 bits, and the voltage 4 is 8 times the value of the signals H2~Ho, and the voltage ki is set to 3 bits.
V@ should be 8 [■] larger than the voltage v4, and no offset should be given to the reference voltage of one converter (4).
) or (1) K equivalently 111 times the voltage V can also be generated inside the converter (4) or (6).

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 4 are diagrams for explaining the same. ill , (51 is the A/D converter, (4) is the D/D converter,
(8) is a correction circuit. Figure 3

Claims (1)

[Claims] The analog input terminal is supplied to the 11th F) A/D converter and the upper bits of the digital output are taken out, and the upper bits are also supplied to the D/A converter and output
This analog voltage is then converted to gummy pressure, and this analog voltage is applied to the second A/
The analog input voltage is supplied to the D converter as a reference voltage, and this reference voltage is given an offset of a magnitude corresponding to the upper bin (K), and the analog input voltage is supplied to the second A/D converter to convert the digital A/D converter that takes out the lower focus of the output! circuit.