JPH03215764A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH03215764A
JPH03215764A JP2011411A JP1141190A JPH03215764A JP H03215764 A JPH03215764 A JP H03215764A JP 2011411 A JP2011411 A JP 2011411A JP 1141190 A JP1141190 A JP 1141190A JP H03215764 A JPH03215764 A JP H03215764A
Authority
JP
Japan
Prior art keywords
converter
digital data
input
comparator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011411A
Other languages
Japanese (ja)
Inventor
Hitoshi Sugano
菅野 齋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2011411A priority Critical patent/JPH03215764A/en
Publication of JPH03215764A publication Critical patent/JPH03215764A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To test an A/D and a D/A converter at the same time by applying data generated by a digital data generator to the input of the D/A converter and the output of the D/A converter to the input of the A/D converter, and comparing the output of the A/D converter with the input of the D/A converter by a comparator. CONSTITUTION:The parallel data consisting of specific (n) bits generated by the digital data generator 21 is applied to the comparator 22 and D/A converter 18 through a switch 20 and a digital data bus 17. The analog signal obtained by the converter 18 is applied to the A/D converter 12 through a switch 23. The (n)-bit parallel digital data obtained by the converter 12 is applied to the other input of the comparator 22. The comparator 22 compares the data generated by the generator 21 with the data outputted by the converter 12 and the comparison output is outputted from an output terminal 19 through the switch 23. Thus, linearity as basic characteristics of the converters 12 and 18 can be tested.

Description

【発明の詳細な説明】 産業上の利用分野 A/D変換器とD/A変換器を内蔵したデジタル方式の
半導体集積回路、特にそのテスト回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital semiconductor integrated circuit incorporating an A/D converter and a D/A converter, and particularly to a test circuit thereof.

従来の技術 一般に、A/D変換器およびD/A変換器のテストには
アナログ・デジタル混在集積回路用テスト装置を必要と
する。また、第3図のように、1チップ内にA/D変換
器2とD/A変換器8および或る機能を持つデジタル回
路5等を1チップに内蔵した半導体集積回路においては
、A/D変換器2およびD/A変換器8を単独にテスト
するためのテスト回路およびテスト用A/D変換器出力
端子4およびテスト用D/A変換器入力端子6が必要で
ある。なお、第3図において、1,9はアナログ入力端
子,アナログ出力端子である。
BACKGROUND OF THE INVENTION Generally, testing of A/D converters and D/A converters requires test equipment for mixed analog and digital integrated circuits. Furthermore, as shown in FIG. 3, in a semiconductor integrated circuit in which an A/D converter 2, a D/A converter 8, a digital circuit 5 with a certain function, etc. are built into one chip, A test circuit, a test A/D converter output terminal 4, and a test D/A converter input terminal 6 are required to test the D converter 2 and the D/A converter 8 individually. In addition, in FIG. 3, 1 and 9 are analog input terminals and analog output terminals.

発明が解決しようとする課題 前述のアナログ・デジタル混在集積回路用テスト装置は
非常に高額な設備である。また、テスト用端子4と6は
取扱うデジタルデータのビット数に相当する個数が必要
である。これを他の既存の端子と共用したり、あるいは
デジタルデータを並列一直列変換して取り扱う等が考え
られるが、どちらも関連のテスト回路が必要である。こ
れらの課題解決には全て半導体集積回路のコスト・アッ
ブにつながる。
Problems to be Solved by the Invention The aforementioned test equipment for analog/digital mixed integrated circuits is extremely expensive equipment. Further, the number of test terminals 4 and 6 is required to correspond to the number of bits of digital data to be handled. It is conceivable to share this with other existing terminals, or to handle digital data by converting it from parallel to serial, but both require related test circuits. Solving these issues will all lead to increased costs for semiconductor integrated circuits.

本発明はこのような問題を解決する半導体集積回路を提
供するものである。
The present invention provides a semiconductor integrated circuit that solves these problems.

課題を解決するための手段 この目的を達成するために、本発明は、本来の機能に必
要な回路以外に、テスト回路としてデジタルデータ発生
器と比較器およびスイッチを1チップに内蔵し、D/A
変換器の出力をA/D変換器の入力に加え、さらにD/
A変換器の入力とA/D変換器の出力比較することによ
り、A/D変換器およびD/A変換器の実動作に近いテ
ストを行なうものである。
Means for Solving the Problems In order to achieve this object, the present invention incorporates a digital data generator, a comparator, and a switch as a test circuit in one chip, in addition to the circuits necessary for the original function. A
Add the output of the converter to the input of the A/D converter, and
By comparing the input of the A converter and the output of the A/D converter, a test close to the actual operation of the A/D converter and D/A converter is performed.

作用 このように構成すれば、半導体集積回路に内蔵したA/
D変換器およびD/A変換器を同時に安価にテストする
ことが可能になる。
Function: With this configuration, the A/
It becomes possible to simultaneously test D converters and D/A converters at low cost.

実施例 以下、本発明を図面を参照して説明する。Example Hereinafter, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例における半導体集積回路のブ
ロック図である。
FIG. 1 is a block diagram of a semiconductor integrated circuit in one embodiment of the present invention.

第1図において、A/D変換器12,或る機能を持つデ
ジタル回路15.D/A変換器18は第3図の従来例と
全《同一であり、これら12,15.18およびデジタ
ルデータバス13.17はすべてnビットの並列デジタ
ルデータを取り扱っているものとする。21はA/D変
換器12およびD/A変換器18をテストするためのn
ビットの並列デジタルデータ発生回路、22はD/A変
換器12の入力およびA/D変換器18の出力デジタル
データを入力とする比較器、23はA/D変換器12の
入力およびD/A変換器18の出力アナログ信号を標準
時aとテスト時bに切り換えるアナログスイッチ、20
は標準時にデジタル回路15から、テスト時にデジタル
データ発生器21からそれぞれデジタルデータをD/A
変換器18の入力に加えるための切換回路である。なお
、第1図において、11はアナログ入力端子、19はア
ナログ出力端子およびテスト結果出力端子である。
In FIG. 1, an A/D converter 12, a digital circuit 15 having a certain function. It is assumed that the D/A converter 18 is completely the same as the conventional example shown in FIG. 3, and these 12, 15, 18 and digital data bus 13, 17 all handle n-bit parallel digital data. 21 is n for testing the A/D converter 12 and the D/A converter 18;
bit parallel digital data generation circuit; 22 is a comparator that receives the input of the D/A converter 12 and the output digital data of the A/D converter 18; 23 is the input of the A/D converter 12 and the D/A an analog switch 20 for switching the output analog signal of the converter 18 between standard time a and test time b;
D/A converts digital data from the digital circuit 15 during standard time and from the digital data generator 21 during test.
This is a switching circuit for adding to the input of the converter 18. In FIG. 1, 11 is an analog input terminal, and 19 is an analog output terminal and a test result output terminal.

以下、テスト時の動作について説明する。デジタルデー
タ発生器21で発生した所定のnビットの並列デジタル
データが切換回路21およびデジタルデータバス17を
介して比較器22とD/A変換器18に加えられる、D
/A変換器18で変換されたアナログ信号をスイッチ2
3を介してA/D変換器12に加える。A/D変換器1
2で変換されたnビットの並列デジタルデータを前記比
較器22の他方の入力に加える。デジタルデータ発生器
21で発生されたデータとA/Dコンバータ12から出
力されたデータの差を比較器22で検出し、その出力は
スイッチ23を介して出力端子19から取り出される。
The operation during testing will be explained below. Predetermined n-bit parallel digital data generated by the digital data generator 21 is applied to the comparator 22 and the D/A converter 18 via the switching circuit 21 and the digital data bus 17.
/A converter 18 converts the analog signal to switch 2
3 to the A/D converter 12. A/D converter 1
The n-bit parallel digital data converted in step 2 is applied to the other input of the comparator 22. A comparator 22 detects the difference between the data generated by the digital data generator 21 and the data output from the A/D converter 12, and its output is taken out from the output terminal 19 via the switch 23.

以上の説明で明らかなように、D/A変換器18および
A/D変換器12の直線性が良ければ比較器22の両入
力は一致する。逆にD/A変換器18とA/D変換器1
2のどちらか一方または両方の直線性が悪ければ比較器
22の2つの入力の間に差が生じる。すなわちこれでA
/D変換器12およびD/A変換器18の基本特性であ
る直線性がテストできる。
As is clear from the above description, if the linearity of the D/A converter 18 and A/D converter 12 is good, both inputs of the comparator 22 will match. Conversely, D/A converter 18 and A/D converter 1
If the linearity of one or both of the two inputs is poor, a difference will occur between the two inputs of the comparator 22. In other words, this is A
The linearity, which is a basic characteristic of the /D converter 12 and the D/A converter 18, can be tested.

さらにデジタルデータ発生器21で発生するデジタルデ
ータの繰返し速度を高めれば、両変換器の動作速度もテ
ストすることが可能である。
Furthermore, by increasing the repetition rate of the digital data generated by the digital data generator 21, it is possible to test the operating speed of both converters.

方、両変換器の直線性の精度を緩める場合は比較器22
のオフセットを大きくすることで対応可能である。
On the other hand, if you want to loosen the linearity accuracy of both converters, use comparator 22.
This can be handled by increasing the offset.

なお、高ビットのA/D変換器とD/A変換器のテスト
で第1図のスイッチ23における電圧降下が問題になる
場合は、第2図のようにD/A変換器38の出力を直接
に出力端子39に取り出し、この半導体集積回路の外部
でA/D変換器32の入力端子31に接続する構成にす
れば解決することができる。なお、第2図において、3
3.37はデジタルデータバス、35はデジタル回路、
40はD/A変換器入力切換回路、41はデジタルデー
タ発生回路、42は比較器、44は比較出力端子である
If the voltage drop at switch 23 in Figure 1 becomes a problem when testing high-bit A/D converters and D/A converters, change the output of D/A converter 38 as shown in Figure 2. This can be solved by taking out the signal directly to the output terminal 39 and connecting it to the input terminal 31 of the A/D converter 32 outside the semiconductor integrated circuit. In addition, in Figure 2, 3
3.37 is a digital data bus, 35 is a digital circuit,
40 is a D/A converter input switching circuit, 41 is a digital data generation circuit, 42 is a comparator, and 44 is a comparison output terminal.

発明の効果 本発明によれば、従来のように高価なテスト装置を必要
とせず、わずかな回路とわずかなテスト用端子を追加す
るだけで、半導体集積回路に内蔵したA/D変換器およ
びD/A変換器をテストすることができる。
Effects of the Invention According to the present invention, an A/D converter and a D /A converter can be tested.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
本発明の第2の実施例のブロック図、第3図は従来のA
/D変換器とD/A変換器を内蔵したデジタル方式の半
導体集積回路のブロック図である。 1・・・・・・アナログ入力端子、3,7・・・・・・
nビットの並列デジタルデータバス、9・・・・・・ア
ナログ出力端子、11・・・・・・アナログ入力端子、
33.37・・・・・・nビットの並列デジタルデータ
バス、35・・・・・・或る機能を持つデジタル回路、
40・・・・・・D/A変換器入力切換回路、41・・
・・・・デジタルデータ発生回路、42・・・・・・比
較器。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional A
1 is a block diagram of a digital semiconductor integrated circuit incorporating a D/D converter and a D/A converter; FIG. 1...Analog input terminal, 3,7...
n-bit parallel digital data bus, 9...analog output terminal, 11...analog input terminal,
33.37...n-bit parallel digital data bus, 35...digital circuit with a certain function,
40...D/A converter input switching circuit, 41...
...Digital data generation circuit, 42...Comparator.

Claims (1)

【特許請求の範囲】[Claims] デジタル動作の機能を持つ回路と、A/D変換器と、D
/A変換器に加え、テスト回路としてデジタルデータ発
生器と比較器とスイッチを1チップに内蔵し、前記デジ
タルデータ発生器で発生されたデータを前記D/A変換
器の入力に加え、前記D/A変換器の出力を前記A/D
変換器の入力に加え、前記A/D変換器の出力と前記D
/A変換器の入力を前記比較器で比較することにより、
前記A/D変換器および前記D/A変換器のテストを行
なうことを特徴とする半導体集積回路。
A circuit with a digital operation function, an A/D converter, and a D
In addition to the D/A converter, a digital data generator, a comparator, and a switch are built into one chip as a test circuit, and the data generated by the digital data generator is applied to the input of the D/A converter. /A converter output to the A/D
In addition to the input of the converter, the output of the A/D converter and the D
By comparing the input of the /A converter with the comparator,
A semiconductor integrated circuit characterized in that the A/D converter and the D/A converter are tested.
JP2011411A 1990-01-19 1990-01-19 Semiconductor integrated circuit Pending JPH03215764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011411A JPH03215764A (en) 1990-01-19 1990-01-19 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011411A JPH03215764A (en) 1990-01-19 1990-01-19 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH03215764A true JPH03215764A (en) 1991-09-20

Family

ID=11777284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011411A Pending JPH03215764A (en) 1990-01-19 1990-01-19 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH03215764A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017359A (en) * 2007-07-06 2009-01-22 Denso Corp Semiconductor integrated circuit
JP2012039423A (en) * 2010-08-09 2012-02-23 Nippon Signal Co Ltd:The Analog signal input device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364419A (en) * 1986-09-05 1988-03-22 Nippon Telegr & Teleph Corp <Ntt> Testing method for encoding and decoding device
JPH01156683A (en) * 1987-12-15 1989-06-20 Nec Corp Self-diagnosing system for electronic circuit package
JPH01260375A (en) * 1988-04-12 1989-10-17 Fujitsu Ltd Lsi circuit with monitoring function
JPH028760A (en) * 1988-06-27 1990-01-12 Nec Corp Semiconductor integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364419A (en) * 1986-09-05 1988-03-22 Nippon Telegr & Teleph Corp <Ntt> Testing method for encoding and decoding device
JPH01156683A (en) * 1987-12-15 1989-06-20 Nec Corp Self-diagnosing system for electronic circuit package
JPH01260375A (en) * 1988-04-12 1989-10-17 Fujitsu Ltd Lsi circuit with monitoring function
JPH028760A (en) * 1988-06-27 1990-01-12 Nec Corp Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017359A (en) * 2007-07-06 2009-01-22 Denso Corp Semiconductor integrated circuit
JP2012039423A (en) * 2010-08-09 2012-02-23 Nippon Signal Co Ltd:The Analog signal input device

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