JPH0611662Y2 - Digital analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a digital-analog converter, and more particularly to a deglitching circuit thereof.

[Conventional technology]

So-called glitch noise is a problem in digital-to-analog converters. For example, consider a 6-bit digital signal, and consider the case where the left end changes to MSB and the right end changes to LSB from "011111" to "100000". The amount of change at this time is a small change represented by "000001", but in the transient state of conversion in the digital-analog converter (hereinafter abbreviated as D / A), it is a short time, but the relationship of the operation timing of circuit elements Then, only the MSB changes from "0" to "1" and the other bits remain "--11111", ie, the analog voltage corresponding to the digital signal "1111".
In some cases, an analog voltage, which is the maximum D / A output voltage corresponding to 11 ”, may be output, and this may be a glitch noise that has a large output level, so it may not be possible to remove it with a low-pass filter.

A deglitch circuit removes the glitch noise, and the present invention relates to a deglitch circuit.

FIG. 3 is a block diagram showing a conventional circuit of this type, in which the data D and the sample pulse T are input from the outside, the data D is converted into an analog voltage VD by D / A (1), and a track / hold circuit is provided. (The drawing symbol is T / H) It is switched by (3) and becomes analog voltage VH.
(4) The high frequency components are removed and the output signal V
It becomes F.

The sample pulse T triggers the track and hold controller (the drawing symbol is CNT) (2) to switch signal TD.
To control the track and hold circuit (3).

FIG. 4 is a waveform diagram showing the waveform of each part of FIG.
(a) shows the waveform of the data D, and the intersection of the two parallel lines shows the change in the data. FIG. 4 (b) shows the waveform of the sample pulse T, and as shown in the figure, the sample pulse T showing the change timing of the data D at each change point of the data D.
Is given. FIG. 4 (c) shows the output VD of the D / A (1), and a glitch occurs at the change point of the data D. Fig. 4
(d) is the output TD of the track hold controller (2)
The "H" level portion is hold and the "L" level portion is tracking. FIG. 4 (e) shows the output VH of the track and hold circuit (3), and changes in the output VD of D / A (1) while the signal TD (FIG. 4 (d)) is at “H” level. Output the analog voltage that holds the conventional value immediately before
While TD is at "L" level, the output VD of the new D / A (1) is output as it is, so that the waveform VH from which glitch is removed is obtained. When the signal VH is passed through the LPF (4), it becomes the signal VF shown in FIG. 4 (f).

[Problems to be solved by the invention]

Since the conventional digital-analog converter is configured as described above, there is a problem that it is necessary to have both the data D and the sample pulse T be sent from the external circuit without fail.

The present invention has been made to solve the above problems, and an object thereof is to obtain an analog-digital converter capable of deglitching without sending a sample pulse from an external circuit.

[Means for solving problems]

In this invention, a comparator that compares the output of a latch holding an input digital signal with the input digital signal and outputs a pulse signal when they do not match, a track hold controller triggered by this pulse signal, A converter for D / A converting the output of the latch and a track / hold circuit for removing the glitch of the output are provided.

[Operation] The input digital signal is input to the latch and the comparator, the output of the latch is converted to an analog value by the converter,
The hold circuit is controlled by the track and hold controller and outputs the held signal value just before the glitch does not occur during the glitch occurrence period of the converter output due to the change of the input digital signal. Are removed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same symbols as in FIG. 3 indicate the same or corresponding parts, (5) is a latch, L is its load signal input terminal, and (6) is a comparator. Q is its signal output terminal, and in this specification, latch (5) and comparator (6)
The circuit constituted by is referred to as a comparison device and corresponds to a differentiation circuit for analog signals.

The conventional value of the data D is stored in the latch (5).
That is, at the time of initialization, when a load signal (probably loaded at the time of changing from the level "L" to "H") is applied to the terminal L, the data D is input to the latch (5), and thereafter. Each time the data D changes, the pulse signal of the comparator (6) outputs the data D at that time to the latch (5).

FIG. 2 shows the data D of FIG. 1, the output of the latch (5) and the comparator.
In the operation time chart showing the relationship with the output of (6), the comparator (6) compares the data D and the output of the latch (5) for each corresponding bit, and if all the bits match, the logic " The L "signal outputs a logic" H "output to the terminal Q if any of the bits is different. The data D in FIG. 2 (a) is from D ₁ to D
At the time of changing to ₂ , the data D is D ₂ and the output of the latch (5) is D ₁ , so the signal of the terminal Q changes from the level “L” to “H”, and this is the terminal L of the latch (5). Is input to the latch (5) and the data D ₂ is input to the comparator (6).
The signal at the terminal Q of becomes the level "L" again, and FIG. 2 (b)
The output of the latch is changed to the output of the comparator in FIG. 2 (e), and the pulse signal as shown in FIG. 2 (c) is output from the comparator. Comparing FIG. 2 and FIG. 4, it can be seen that the output of the terminal Q of the comparator (6) can be used as the sample pulse T in FIG.

The waveforms of signals VD, TD, VH, and VF in Fig. 1 are VD and VD in Fig. 4 (c).
It is not necessary to explain that it changes like TD in FIG. 6D, VH in FIG. 8E, and VF in FIG.

If the noise in the signal VH does not cause a problem, the LPF (4) can be omitted.

[Effect of device]

As described above, according to the present invention, since the sample pulse can be generated internally, the sample pulse can be sent from the outside regardless of whether it is the most significant bit or not. It is possible to obtain a digital-analog converter capable of deglitching in response to changes in the input digital signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation time chart showing the relationship between the data D of FIG. 1 and the output of the latch and the output of the comparator, and FIG. 3 is the conventional circuit. And FIG. 4 is a waveform diagram showing the waveform of each part of FIG. (1) is D / A, (2) is track and hold controller,
(3) is a track and hold circuit, (5) is a latch, and (6) is a comparator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] 1. A latch for holding conventional data of an input digital signal to be converted into an analog voltage,
The output of this latch is compared with the digital signal, and a pulse signal is output only if the result of the comparison is no match.
A comparator for latching the digital signal in the latch by the pulse signal, a converter for converting the digital signal output from the latch into an analog voltage, and generated in the transition period of the digital signal change of the digital-analog conversion in the converter. A track and hold circuit for switching the output to eliminate the glitch, and a track and hold controller for generating a switching signal for controlling the track and hold circuit triggered by the pulse voltage of the output of the comparator. Digital-to-analog converter.