JPS6120891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital equipment, and more particularly to digital word recognizers.

BACKGROUND OF THE INVENTION With the development of integrated circuits (ICs), devices in various industries are increasingly being controlled, especially using digital technology. Digital
Computers are a good example of digital devices that use IC technology. With the development of various digital devices, various digital service devices have been developed for the purpose of designing and repairing these devices.

Observing the waveform of a digital signal during design or troubleshooting is more complicated than that of an analog signal for the reasons described below. That is, digital signals are generally aperiodic, and a large number of signals with mutually different time relationships are generated at the same time, and are generated in different logic circuits, such as TTL (transistor-transistor logic). This is because logic circuits such as ECL (emitter coupled logic) and CMOS (complementary metal oxide semiconductor) have different logic levels. Another factor is that logic errors occur intermittently due to various causes.

By the way, generally word recognizer (hereinafter referred to as
Digital equipment known as WR (abbreviated as WR) is widely used for maintenance of various digital equipment. The WR generates an output pulse when a plurality of applied digital input signals match a preselected combination of input signals.
The combination of input signals is selected by a plurality of switches provided in the WR, and the output pulses are applied as trigger signals to maintenance equipment such as logic analyzers and oscilloscopes.

Before describing embodiments of the present invention, an example of a conventional WR will be described with reference to the block diagram of FIG.
WR in FIG. 1 compares the input signals applied to input terminals 1, 2, 3, ..., n with respective threshold values V _th ,
Comparators C ₁ , C ₂ , C ₃ , ..., _Co that output ECL signals
and a switch to select logic low level "L ₀ ", logic high level "Hi", or ignore logic level "X".
S ₁ , S ₂ , S ₃ ,..., S _o and ECL and gate
AND, ECL-TTL converter CONV, and output terminal
It consists of OUT. The value of the threshold V _th applied to the comparators C ₁ -C _o can be varied independently to select the desired logical combination. Since digital maintenance equipment generally receives TTL signals, an ECL-TTL converter CONV is provided.

Since the number of bits in digital devices varies from device to device, and complex, high-speed devices generally have more bits, a general-purpose WR must have a large amount of bit processing capability that is not normally used. Therefore, such a general-purpose WR is not practical from an economic standpoint, so the number of bits of the WR should be limited to an appropriate value per unit, for example, 8 bits, and when used with devices with a large number of bits, multiple bits may be used. It is common practice to connect several units in series. However, in this conventional method of using the trigger output pulse of each unit as an extended signal, TTL
Since the delay when converting to level cannot be ignored,
The disadvantage is that the operating frequency can be kept low.

Accordingly, an object of the present invention is to avoid the delay that has been a problem with conventional WR by performing bit expansion at the ECL level.

Another object of the present invention is to have multiple input terminals, and
The object of the present invention is to provide a WR with a high operating frequency that can form a NAND, OR, or NOR gate.

Hereinafter, the configuration and operation of embodiments of the present invention will be described based on the accompanying drawings, but the embodiments described in this specification are merely illustrative and do not limit the present invention.

FIG. 2 is a simple block diagram of the main parts of WR 10 having a bit expansion circuit according to the present invention, and the WR unit of this embodiment has 18 bits. First and second nine-channel data are applied to first and second comparator/select circuits 11A and 11B, respectively. The first and second comparator/selection circuits 11A,
11B each comprises, for example, the comparator C shown in FIG. 1, the selection switch S, and the AND gate AND. first and second comparator/selection circuits 11A,
The output terminals of 11B are the input terminals 1 and 2 of the ECL NOR gate 12 of the WR section, and the input terminals of the bit expansion section.
It is connected to input terminals 1 and 2 of ECL NOR gate 13. The input terminals 3 of each of the gates 12 and 13 are
It is connected to an input terminal 14 designated as EXP IN, and input terminals 1, 2, and 3 are connected to a suitable power source (not shown) via a terminating resistor R _T and maintained at a constant voltage V _TT . The output terminal of the gate 12 is connected to the output terminal 16 (TTL TRIG
OUT), and the output terminal of gate 13 is connected to output terminal 18 (EXP
OUT). Note that the output end of the gate 13 is connected to a suitable power source (not shown) via a terminating resistor _RT , and its voltage is maintained at _VTT .

The operation of the embodiment shown in FIG. 2 will be described below. The data applied to the first and second comparators/selection circuits 11A and 11B is
If it matches the logic combination selected by word selection switches (not shown) in 1A and 11B, a logic low level "L ₀ " is output. Gate 12, 13
In order for the output of gate 12 to change from low level to high level, the inputs to gates 12 and 13 must all go to low level. However, if there is no input to the input terminal 14, when the logic levels to the input terminals 1 and 2 both go low, the outputs of the gates 12 and 13 change to high level, but when the bit expansion signal is input to the input terminal 14, If applied, this bit expansion signal must also go to low level before gate 1 is applied.
The outputs of 2 and 13 do not change to high level. That is,
It can be seen that an output pulse is generated from output terminals 16 and 18 only when the data of the 18 channels match a preset logical combination and the bit expansion signals go low at the same time. Note, however, that while the output at output terminal 16 is significantly delayed due to the ECL-to-TTL conversion circuitry, the output at output terminal 18 (ie, the bit magnified signal) is delayed only slightly.

An embodiment of the present invention will be described with reference to FIG. 3 regarding the above-mentioned bit expansion signal. Figure 3 shows three WR units 10A, 10B, 10 connected in series.
FIG. 2 is a block diagram of a 54-bit WR using C.
Each of the WR units 10A to 10C is the same as the WR shown in FIG. 2, and the terminals (14B, 14B,
14C), 16C, (18A, 18B) are the second
This corresponds to the output terminals 14, 16, and 18 in the figure. 1st
18-bit data is applied to the input of the first unit 10A. No signal is applied to the input terminal 14 (see FIG. 2) of the first unit 10A, and the output terminal 18A is connected to the input terminal 14 of the second unit 10B.
Connected to B. A second 18-bit data is applied to the input of the second unit 10B. The output end 18B of the second unit 10B is connected to the third unit 10.
It is connected to input terminal 14C of C. Third 18-bit data is applied to the input terminal of the third unit 10C, and the output pulse from the output terminal 16C is 54
It is used as a bit logical combination match output signal (ie, word recognition output).

In other words, the first unit 10A receives the applied 18
If the data of the channel matches the selected logical combination, an output is produced at the output terminal 18A, and the second unit 10B is connected to the first and second units 10A and 10B.
If the data of the 36 channels to B match the selected logical combination, an output is produced at the output terminal 18B;
The third unit 10C is 54 to the first to third units.
If the channel data matches the selected logical combination, a logical combination matching signal is output to the output terminal 16C.

As explained above, by expanding the bits at the ECL level, the signal propagation delay is minimized, and it is possible to obtain a WR in which each unit operates at a high speed of 50 MHz or higher. As another embodiment of the present invention, if one WR unit is added to the block of FIG.
It is possible to determine logical combinations of 72 channels of data at a clock frequency of 15 MHz or higher. Of course, it is also possible to add two or more WR units to determine logical combinations of even more channel data. In FIG. 3, connections between each unit may be made using, for example, a 50Ω coaxial cable.

FIG. 4 is a block diagram showing essential parts of a modification of the embodiment of the invention shown in FIG. 2. The embodiment of FIG. 4 replaces the first gate 12 of FIG. 2 with an ECL gate 12' having a complementary output terminal, and
A phase inversion switch 19 is inserted between the ECL-TTL converter 15 and the ECL-TTL converter 15.

In the block diagram of FIG. 4, when the logic combinations match, all the logic levels of the multiple inputs to the gate 12' become low level, and the outputs of the upper and lower output terminals of the gate 12' are logic low and logic low, respectively. Becomes a high level. In the normal case with the phase inversion switch 19 in the illustrated position, the logic levels of the inputs applied to the inverting and non-inverting inputs of the ECL-TTL converter 15 are low and high, respectively. Therefore, a rising TTL signal pulse is generated from the output terminal 16. On the other hand, when the switch 19 is switched from the above-mentioned normal state, the output of the ECL-TTL converter becomes a logic high level before and after the logical combinations match, and becomes a logic low level while the logic combinations match. Therefore, the falling signal from output terminal 16 is
A TTL signal pulse is generated.

As explained above, the basic functions of WR are:
Applying a trigger signal to other circuits or equipment when a plurality of input data matches a selected logical combination, especially by using the phase inversion switch 19 shown in FIG. Since the phase of the trigger output can be easily reversed, the embodiment of FIG. 4 is suitable as a WR for use with equipment that specifies either a falling or falling trigger pulse. That is, by providing the switch 19, the range of applications of WR can be expanded. As described above, according to the present invention, signal delay can be minimized by providing a circuit that performs bit expansion at the ECL level. It is possible to obtain a WR that can quickly determine whether logical combinations of bits match. Furthermore, by using a phase inversion switch, this WR can be used as a multi-input AND, NAND, OR, or NOR gate, making it possible to use the WR in a wide range of applications.

In the present invention, a plurality of word recognizers are connected in sequence, and an output signal is obtained from the first word recognizer only when input data supplied to the first word recognizer matches a predetermined word. Further, an output signal is obtained from the output terminal of the second word recognizer in the next stage only when the input data respectively supplied to the first and second word recognizers coincide with the respective predetermined words at the same time. Furthermore, from the output terminal of the third word recognizer in the third stage, the first, second and third
An output signal is obtained only when the input data respectively supplied to the word recognizers coincide with the respective predetermined words. That is, by the output of the first output terminal of each word recognizer, it is possible to easily detect that various combinations of words have been supplied as input data, and the second output terminal can be used for expansion to perform conventional word recognition. This has the effect of eliminating the delay that has been a problem with recognizers and realizing a word recognizer with a high operating frequency.

Although the preferred embodiments of the present invention have been described above, those skilled in the art will easily be able to modify and modify the embodiments described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional word recognizer, FIG. 2 is a simple block diagram of a word recognizer according to the present invention, and FIG. 3 is a block diagram of a word recognizer according to the present invention. A block diagram showing an embodiment of the present invention in which word recognizers are connected in series. FIG. 4 is a block diagram showing a main part of a modification of the embodiment of FIG. 2. 11A, 11B...word selection circuit, 12...
ECL gate, 15...ECL-TTL converter, 17...
ECL line converter.

Claims (1)

[Claims] 1. A word selection circuit that outputs a predetermined logic level of an ECL signal when input data of a plurality of bits matches a selected digital word, and an output of the word selection circuit at one input terminal. first and second ECL gates each receiving a logic level;
and an auxiliary input terminal connected to the other input terminal of the second ECL gate, an ECL-TTL converter receiving the output logic level of the first ECL gate, and the ECL-
at least first and second word recognizers each having a first output terminal receiving the output logic level of the TTL converter and a second output terminal receiving the output logic level of the second ECL gate; When the output logic level of the word selection circuit provided respectively and the logic level of the signal supplied to the auxiliary input terminal are a predetermined logic level combination, a predetermined logic level of the TTL signal is output from the output terminal, and the second outputting a predetermined logic level of the ECL signal from an output terminal; connecting the second output terminal of the first word recognizer to the auxiliary input terminal of the second word recognizer; A digital device, characterized in that a predetermined logic level is obtained from the first and second output terminals of the second word recognizer when the input data supplied to the second word recognizer respectively match the selected digital word.