JPH0683071B2 - A / D converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device for converting an analog signal into a digital code, and more particularly to a structure suitable for integrating a means for converting at high speed into an integrated circuit.

(Conventional technology and its problems) Conventionally converted analog signals into digital codes at high speed (A / D
2 ^N-1 when the resolution is N bits
A fully parallel A / D converter has been used that uses a single voltage comparator. However, if the resolution is increased, the number of voltage comparators required becomes too large, which is not practical.

Therefore, a cascade connection type A / D converter as shown in FIG. 1 is used. Regarding this method, "Electronic" by H. Schmid
Analog / Digital Converters "(VAN NOSTRAND REIN
The details are omitted because it is described in detail on page 318 (published by HOLD), but in FIG. 1, a 3-bit parallel A / D converter is AD.
1, AD2, AD3 3 pieces, 3-bit D / A converter 2 pieces DA1, DA2 are used, and the input signal input from the input terminal a is first
A / D converter AD1 encodes the output code of the upper 3 bits
This output code is obtained from 4,5,6 and the first D / A converter
The signal is reproduced by DA1 and the input signal is reduced, and this is amplified by amplifier A1 by a factor of 2 ^3, that is, input to the second A / D converter AD2 to obtain the next 3-bit output code. Add this code further
D / A convert and subtract from the input voltage of AD2, further increase by 8 times by A2, and apply to the third A / D converter AD3 to obtain a 3-bit code to obtain a total 9-bit code. There is. In this case, the number of comparators required for the 3-bit A / D converter is 7, so a total of 21 comparators are required. The parallel type has 511 units, and it can be seen that the cascade type can significantly reduce hardware compared to this.

However, particularly in the cascade type, both the first A / D converter and the D / A converter require an accuracy equal to or higher than the final resolution, in this example, 9-bit accuracy. Otherwise, the error of the output code of the second and subsequent converters will be large. Such constraints can be solved by selecting components when assembling on a printed circuit board, but if the whole is to be an integrated circuit, it is not suitable for an integrated circuit because it will result in a significant reduction in part retention. There wasn't.

As a method of repeatedly using the same comparator, there is an example shown in FIG. The present invention is the 1977 ISSCC Digest of Tec
It was published by RH Mccharles et al. on page 96 of the hnical paper, and a detailed explanation is omitted here. The present invention applies the input voltage Vim to the input terminal 21, and applies the reference voltage V _REF that is the maximum voltage when performing A / D conversion to the terminal 22,
A ground voltage, which is a central voltage for A / D conversion, is applied to the terminal 23. These voltages are connected to one electrode of the capacitor C21 via the switch S21, and the other electrode of C21 uses the adder composed of the first operational amplifier A21 and the capacitor C21 and C25 switch S22, The second operational amplifier A22, the capacitors C24 and C23, and the voltage held by the holding circuit by the switch S23 are added, and the result is compared using a third operational amplifier and a comparator composed of the capacitor C26 and the switch S24. Is done. With this structure C21, C22, C23,
C24 is made equal, C25 is selected twice, and the switch timing is chosen. By selecting the timing of the switch, the input voltage is first transmitted to the comparator and compared with the ground potential to obtain the sign of MSB 1 bit. Next, this voltage is held by the holding circuit. Next, if the comparison result is positive, S21 is switched from the ground side of the terminal 23 to the reference voltage of the terminal 22, and if negative, it is switched from the reference voltage to the ground side to output 2 × Vin as the output of the adder. ± V
_REF is calculated. This voltage is compared by the comparator to obtain the second bit. If this operation is repeated N times, N-bit A / D conversion can be performed.

This method is simple in hardware and can configure an A / D converter, but if it is 10 bits, it needs to be repeated 10 times. Although the analog addition is repeated, the accuracy of the analog addition is largely limited by the gain and bandwidth of the operational amplifier used. Since the error of the first addition result becomes larger and larger by repeating the calculation, the resolution is determined by the first addition accuracy. Further, the calculation time required for one calculation becomes longer as the accuracy is increased. Moreover, since the number of calculations increases proportionally, it is impossible to perform high-speed and high-precision A / D conversion.

(Object of the Invention) The present invention provides means for eliminating the drawbacks of the various A / D converters described above and realizing a high-speed and highly accurate A / D converter with a relatively small amount of hardware.

(Structure of the Invention) The present invention provides a parallel type A / D converter provided with two signal input terminals, and a first code which is smaller than the output code of the A / D converter by the minimum resolution. Means for subtracting a corresponding voltage from the input voltage, and amplifying the reduced voltage by 2 ^N-1 times when the resolution of the A / D converter is N bits, and the amplified voltage is A / D converted. Means for supplying to another input terminal of the converter, and a second code obtained by causing the A / D converter to act on the code obtained by multiplying the first code by 2 ^N-1 and the amplified voltage. An A / D converter having means for adding and.

(Embodiment) Next, an embodiment of the present invention will be described with reference to FIG. 3 as an implementation example of a 5-bit precision A / D converter.

In this embodiment, the switch S connected to the signal input terminal 101 is
Switch S102 connected to 101 and the output 104 of the operational amplifier
Has two input terminals to be switched by, in series between the two terminals of the terminal 103 Toko applying the maximum voltage reference voltage V _GND is added terminal 102 and the minimum voltage -V _R give when performing A / D conversion Eight comparators CP1 to CP8 that compare the input voltage with the connected resistors R1 to R9 and the connection points of these resistors
A bit parallel type A / D converter constituted by the above, and a terminal 101 whose switch point applies the input voltage depending on the state of the comparator which constitutes this A / D converter and the external timing.
And the negative input point of the give V _GND terminal 102, and the eight switches S111~S118 and output points of the switches with three contacts are connected to some terminal 103 giving -V _R and operational amplifier A101 The capacitors C101 to C108 having the same capacity connected between them and the capacitor C1 connected in parallel between the input point and the output point of the operational amplifier A101.
C109 and switch S with double capacity for one of 01-108
The voltage corresponding to the first code, which is smaller than the output code of the A / D converter constituted by 103 by the minimum resolution, is subtracted from the input voltage, and this voltage is set to 3 bits of the resolution of the A / D converter. To the switch S10, which is amplified by 2 ² or 4 times and the amplified voltage is input to the A / D converter.
For the means given to 2 and the first code of the A / D converter
It is composed of means 105 for adding and outputting the code multiplied by 2 ^N-1 and the second code obtained by operating the A / D converter again to the output of the operational amplifier. Wherein the resistance value R1~R9 the A / D converter from R2 R8 are the same value, R1 and R9 is selected from R ₂ to 1/2 of the resistance value of R _8.

Next, the operation of this circuit will be described. First, S101 and S103 are on, S
111 to S118 are connected to signal input terminals. At this time S102
Turn off. Here, the voltage comparators CP1 to CP8 are operated. If the input voltage Vi is negative and V _GND = 0, for example, Suppose If there is no offset voltage in the comparator, CP1 to CP5 will be logic 1 and CP6 to CP8 will be logic zero, but A little less, that is, in the 3-bit A / D converter of this example With a little less offset, Then CP5 may take a logical zero. Also In that case, CP6 may take the logic 1. In the conventional method, a normal output cannot be obtained in these two cases. Now, assume that CP1 to CP6 are logic 1 with an input voltage satisfying the above conditional expression. That assumed to be _{-10 / 16V R ef>Vi>} -11 / 16V R ef. Then, the output of the parallel A / D converter becomes "110" when it should be "110" when full scale is taken in the negative direction. At this time, a code "101" which is obtained by subtracting 1 from the output code is stored in the addition means 105 as the first code for adding. This conversion can be easily performed by means such as PLA and ROM logic circuits and flip-flops. When the result of each of the above comparators is sent to the addition means 105,
Switch to match each ending number after opening S112 to S1
18 is driven to V _GND for logic 1 and for logic zero −
Control to switch to V _REF . At this time, only S111 is always switched to V _GND . When CP1 to CP6 are logic zero S112
~S116 is connected to -V _R ef S117, S118 are connected to V _GND. Then the output voltage of A101 can be calculated using the law of conservation of charge. Output is obtained. In other words, in the case of this example, the input voltage is kept negative, so the first code corresponds to "101". A voltage that is four times the voltage higher than the input voltage is output. That is, the output voltage is Becomes Therefore, S101 is opened, S102 is closed, the A / D converter is acted again to obtain the second code 3 bits, and the first code is added to the binary code "10100" multiplied by 4 to add the 5-bit A The / D conversion can be obtained by operating the 3-bit precision A / D converter twice. The second input voltage is 0> 4
_{(Vin + 5 / 8V R ef} )> - 1 / 4V R because it is ef MSB of the output code according to a second round of transformation is always becomes zero, never carry occurs to the upper in addition result, the correct conversion Done. Quadrupling the first code can be accomplished by providing the add input to the upper 3 bits of the 5-bit adder.

(Effects of the Invention) According to the present invention, not only a 3-bit precision A / D converter but generally a n-bit precision parallel A / D converter
A 1-bit precision A / D converter can be configured by repeating conversion twice.

Therefore, it is difficult to improve the normal accuracy, but it is possible to improve the accuracy of the parallel type A / D converter, which has the characteristic of being high speed, nearly twice as much, and the number of repetitions is 2 times, so errors can be introduced. There is little property and high speed is maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional example in which a parallel type A / D converter is continuously connected to improve the resolution. AD1 to AD3 are 3-bit parallel type
A / D converters DA1 to DA3 are 3-bit D / A converters A1 and A2 are operational amplifiers. FIG. 2 is a circuit diagram of a conventional example in which the same comparison circuit is repeatedly used to improve the resolution. A21 and A22 are operational amplifiers A23
Is a comparator. FIG. 3 is a circuit diagram of an embodiment for performing A / D conversion with 5-bit precision according to the present invention. CP1 to CP8 are comparators, A101 is an operational amplifier, and 105 is a means for binary-coding the result of the comparator and performing addition.

Claims (1)

[Claims] 1. A parallel type A / D converter provided with two signal input terminals, and a voltage corresponding to a first code which is smaller than the output code of the A / D converter by the minimum resolution. Means for subtracting from the input voltage, and this subtracted voltage is amplified by 2 ^N-1 times when the resolution of the A / D converter is N bits, and the amplified voltage is added to the other of the A / D converter. A means for supplying to one input terminal, a code obtained by multiplying the first code by 2 ^N-1 times and a second code obtained by causing the amplified voltage to act on the A / D converter are added. A / D converter having means for performing.