JPH0590964A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH0590964A
JPH0590964A JP27504791A JP27504791A JPH0590964A JP H0590964 A JPH0590964 A JP H0590964A JP 27504791 A JP27504791 A JP 27504791A JP 27504791 A JP27504791 A JP 27504791A JP H0590964 A JPH0590964 A JP H0590964A
Authority
JP
Japan
Prior art keywords
converter
circuit
input
signal
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27504791A
Other languages
Japanese (ja)
Other versions
JP2626352B2 (en
Inventor
Shiro Nakagawa
士郎 中川
Atsuko Tsuchida
敦子 土田
Eiji Takahashi
栄司 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP3275047A priority Critical patent/JP2626352B2/en
Priority to US07/897,152 priority patent/US5305005A/en
Priority to EP92305475A priority patent/EP0520662B1/en
Priority to DE69219216T priority patent/DE69219216T2/en
Publication of JPH0590964A publication Critical patent/JPH0590964A/en
Application granted granted Critical
Publication of JP2626352B2 publication Critical patent/JP2626352B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To easily and a dither signal to an analog input signal by providing an integration circuit including a time constant circuit to an input section of an analog signal of the A/D converter circuit and applying a ramp potential to the integration circuit via a capacitor of the time constant circuit. CONSTITUTION:A capacitor C01 is inserted between an analog signal input terminal 16 and a ground point and the input terminal is connected to an input of an A/D converter 10 via a resistor R11. One terminal of a capacitor C11 is connected to the input of the A/D converter 10 and the other terminal connects to an output of an integration circuit 60 comprising resistors R21, R22 and capacitors C21, C22. Moreover, a time constant circuit comprising a resistor R11 and the capacitor C11 forms an integration circuit 70 with respect to an analog input signal. Then the A/D converter 10 receives an analog input signal via the integration circuit 70 comprising a time constant circuit consisting of the resistor R11 and the capacitor C11. Furthermore, a dither signal is fed to one terminal of the capacitor C11 forming the integration circuit 70 and added to the analog input signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はアナログ信号をディジタ
ル信号に変換するA/D変換装置に関し、特に簡単な構
成で高精度のディジタル出力を提供するA/D変換装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter that converts an analog signal into a digital signal, and more particularly to an A / D converter that provides a highly accurate digital output with a simple structure.

【0002】[0002]

【従来の技術】アナログ信号をディジタル信号に変換す
る技術として積分型と逐次比較型が従来から知られてい
る。前者は所定間隔のクロック信号をカウンタで計数す
ると共に、該クロック信号を積分して傾斜電位を発生
し、該傾斜電位が入力アナログ信号のレベルに等しくな
る瞬間にカウンタによる計数を停止し、その時のカウン
タの内容をディジタル出力とする。
2. Description of the Related Art As a technique for converting an analog signal into a digital signal, an integration type and a successive approximation type are conventionally known. The former counts clock signals at predetermined intervals with a counter, integrates the clock signals to generate a gradient potential, and stops counting by the counter at the moment when the gradient potential becomes equal to the level of the input analog signal. The contents of the counter are digital output.

【0003】逐次比較型の場合は所定間隔のクロック信
号をカウンタで計数すると共に、カウンタの内容をD/
Aコンバータによりアナログ信号に変換し、その値を入
力のアナログ信号と比較して、両者のレベルが等しくな
った瞬間にカウンタによる計数を停止して、その時のカ
ウンタの内容をディジタル出力とする。最近のマイコン
に内蔵されているA/D変換器は後者の逐次比較型が多
い。
In the case of the successive approximation type, clock signals at predetermined intervals are counted by a counter, and the contents of the counter are D /
It is converted into an analog signal by the A converter, the value is compared with the input analog signal, the counting by the counter is stopped at the moment when both levels become equal, and the contents of the counter at that time are digitally output. The latter successive approximation type is often used as the A / D converter built into recent microcomputers.

【0004】A/D変換の精度はカウンタ及びD/A変
換器の桁数により決定され、現在の4ビットマイコンに
内蔵されるA/D変換器はカウンタ及びD/A変換器が
8ビットのものが多い。この場合の分解能は0.4%
(=1/256)である。
The accuracy of the A / D conversion is determined by the number of digits of the counter and the D / A converter. The A / D converter built in the present 4-bit microcomputer has a counter and a D / A converter of 8 bits. There are many things. The resolution in this case is 0.4%
(= 1/256).

【0005】一方、A/D変換器のひとつの応用例とし
て、気温、又は相対湿度などのセンサ出力をディジタル
表示する場合について考えてみると、0.1度又は0.
1%の精度での表示を行なうには少なくとも0.1%
(1/1000)の分解能が必要であり、従来の8ビッ
トのA/D変換器では不十分である。
On the other hand, as one application example of the A / D converter, consider the case where the sensor output such as temperature or relative humidity is digitally displayed.
At least 0.1% to display with 1% accuracy
A resolution of (1/1000) is required, and the conventional 8-bit A / D converter is insufficient.

【0006】分解能を上げるためにカウンタ及びD/A
変換器の桁数を増やすことは、装置のコスト上昇につな
がり好しくない。
A counter and D / A for increasing the resolution
Increasing the number of digits in the converter increases the cost of the device and is not desirable.

【0007】そこで、A/D変換器のビット数で定まる
分解能を越える分解能をもつA/D変換装置として、ア
ナログ入力に傾斜電位を加算するとともに、A/D変換
器の出力に演算回路を接続して、複数回のA/D変換の
平均値を該演算回路により与え、該演算回路の分解能で
定まるA/D変換出力を与える装置が特願平03−18
1623により提案されている。
Therefore, as an A / D converter having a resolution exceeding the resolution determined by the number of bits of the A / D converter, a gradient potential is added to the analog input and an arithmetic circuit is connected to the output of the A / D converter. Then, an apparatus for giving an average value of A / D conversions of a plurality of times by the arithmetic circuit and giving an A / D conversion output determined by the resolution of the arithmetic circuit is Japanese Patent Application No. 03-18.
Proposed by 1623.

【0008】図2によりこの技術を説明する。This technique will be described with reference to FIG.

【0009】図2において、10は8ビットのA/D変
換器、12は加算器、14は演算回路、16はアナログ
信号Ainの入力端子、18は10ビットのディジタル出
力端子、20はディザ入力信号(傾斜電位)である。デ
ィザ入力信号は鋸歯状波又は三角波で、その振幅はA/
D変換器10の最小分解能の値(例えば10mV)とす
る。
In FIG. 2, 10 is an 8-bit A / D converter, 12 is an adder, 14 is an arithmetic circuit, 16 is an input terminal for the analog signal A in , 18 is a 10-bit digital output terminal, and 20 is dither. It is an input signal (gradient potential). The dither input signal is a sawtooth wave or a triangular wave, and its amplitude is A /
The minimum resolution value of the D converter 10 (for example, 10 mV) is set.

【0010】アナログ入力信号とディザ信号20とは加
算器12により加算されて、A/D変換器10により8
ビット精度のA/D変換が行なわれる。A/D変換の動
作はディザ信号の傾斜時間内に複数回(N回)行なわ
れ、その度毎に、ディジタル出力は演算回路14で累積
加算される。複数回のA/D変換及び累積加算の終了
後、演算回路14は、その内容を数値Nで割算し、結果
の商を10ビット精度で出力端子18に出力する。Nの
値は、本実施例では16が適当である。つまり演算回路
14はA/D変換器の16回の出力の平均値を算出して
いる。
The analog input signal and the dither signal 20 are added by the adder 12 and then added by the A / D converter 10.
A / D conversion with bit precision is performed. The operation of A / D conversion is performed a plurality of times (N times) within the dither signal inclination time, and the digital output is cumulatively added by the arithmetic circuit 14 each time. After the completion of A / D conversion and cumulative addition a plurality of times, the arithmetic circuit 14 divides the contents by the numerical value N and outputs the resulting quotient to the output terminal 18 with 10-bit precision. A value of 16 is suitable in this embodiment. That is, the arithmetic circuit 14 calculates the average value of the 16 outputs of the A / D converter.

【0011】ディザ信号の瞬時値をΔVとすると、A/
D変換器10へのアナログ入力はAin+ΔVであり、Δ
Vの値はディザ信号の傾斜に従ってしだいに増加(又は
減少)する。
When the instantaneous value of the dither signal is ΔV, A /
The analog input to the D converter 10 is A in + ΔV, and Δ
The value of V gradually increases (or decreases) according to the slope of the dither signal.

【0012】8ビットのディジタル出力のm回はAin
ディジタル変換出力(AinA/D に等しくN−m回は
(AinA/D +1となる。(ΔVは最小分解能の範囲を
変動するので)N−mの値は、Ain−(AinA/D が最
小分解能の巾のうちどの辺にあるかで変化する。例えば
最小分解能を10mVとし、Ain−(AinA/D が7m
VであればΔV>3mVでディジタル出力は1増加する
し、3mVであればΔV>7mVにならなければ増加し
ない。つまりディジタル出力が(AinA/D +1となる
回数N−mは、Ain−(AinA/Dの値に比例する。そ
して(N−m)/Nは、Ain−(AinA/D の値をlog2
NビットでA/D変換した値となる。
[0012] 8-bit digital output of the m times is equal N-m times to the digital conversion output of the A in (A in) A / D becomes (A in) A / D +1 . The value of Nm (since ΔV varies over the range of minimum resolution) varies depending on which side of the width of the minimum resolution A in − (A in ) A / D is. For example the minimum resolution and 10mV, A in - (A in ) A / D is 7m
If V, ΔV> 3 mV, the digital output increases by 1, and if 3 mV, it does not increase unless ΔV> 7 mV. That is, the number of times N−m when the digital output becomes (A in ) A / D + 1 is proportional to the value of A in − (A in ) A / D. And (N−m) / N is the value of A in − (A in ) A / D log 2
The value is A / D converted with N bits.

【0013】従って、入力アナログ信号にディザ信号を
加算したアナログ信号を8ビットのA/D変換器で16
回A/D変換し、各ディジタル出力の累積和を16で除
した商を10ビット精度で得ることにより、10ビット
精度のA/D変換出力を得ることができる。
Therefore, the analog signal obtained by adding the dither signal to the input analog signal is converted into 16 bits by the 8-bit A / D converter.
It is possible to obtain an A / D converted output with 10-bit precision by performing A / D conversion twice and obtaining a quotient obtained by dividing the cumulative sum of each digital output by 16 with 10-bit precision.

【0014】なお、必要な測定回数(上記説明では1
6)は、増加する桁数をKとするとき、2K で十分で、
K=2なら4となるが、傾斜電位の直線性やノイズによ
る誤差の影響を除くために上記値の2〜4倍とすること
が好ましい。
The required number of measurements (1 in the above description)
In 6), when K is the number of digits to be increased, 2 K is sufficient,
If K = 2, it will be 4, but it is preferably 2 to 4 times the above value in order to eliminate the influence of the linearity of the gradient potential and the error due to noise.

【0015】又、入力アナログ信号にディザ信号を加算
することにより出力レベルがシフトすることを補償する
ため、出力ディジタル信号から所定値を減算するか、又
は、ディザ信号を0を中心として正負の両極性信号とす
る必要がある。
Further, in order to compensate for the shift of the output level by adding the dither signal to the input analog signal, a predetermined value is subtracted from the output digital signal, or the dither signal is positive and negative with 0 as the center. Must be a sex signal.

【0016】[0016]

【発明が解決しようとする課題】ところで、ディザ信号
(傾斜電位)を注入する加算器12は次の様な条件を満
足することが要求される。 (a)加算器の存在がアナログ入力信号に影響を与えな
いこと。 (b)アナログ入力信号に対し無限大に近いインピーダ
ンスをもつこと。 (c)雑音の発生や誘起をしないこと。 (d)加算器による電力消費がないこと。 (e)出来るだけ回路が簡単で安価なこと。
The adder 12 for injecting the dither signal (gradient potential) is required to satisfy the following conditions. (A) The presence of the adder does not affect the analog input signal. (B) It has an impedance close to infinity with respect to the analog input signal. (C) Do not generate or induce noise. (D) There is no power consumption by the adder. (E) The circuit should be as simple and inexpensive as possible.

【0017】従来用いられる加算器として、ラダー抵抗
型、ラダー抵抗とオペアンプとの組合せなどがある。
Conventionally used adders include a ladder resistance type and a combination of a ladder resistance and an operational amplifier.

【0018】ラダー抵抗型は、アナログ入力とディザ入
力とを、各々、抵抗を介して接続するもので、抵抗のた
めに、アナログ入力レベル及びディザ入力レベルが共に
減衰し好ましくない。
The ladder resistance type is a type in which an analog input and a dither input are connected via a resistor, respectively, and both the analog input level and the dither input level are attenuated due to the resistance, which is not preferable.

【0019】又、オペアンプを用いる加算器は、オペア
ンプによる雑音、温度ドリフト、オフセットなどの問題
が発生する他、回路が複雑となり消費電力が大きくなっ
て好ましくない。
Further, an adder using an operational amplifier is not preferable because noise, temperature drift, offset and other problems due to the operational amplifier occur, and the circuit becomes complicated and power consumption increases.

【0020】従って、本発明の目的は、従来の技術の上
記欠点を改善し、ディザ信号により分解能を改善したA
/D変換装置におけるディザ信号の注入回路の改良を提
供することにある。
Therefore, the object of the present invention is to improve the above-mentioned drawbacks of the prior art and to improve the resolution by the dither signal.
An object of the present invention is to provide an improvement of a dither signal injection circuit in a D / D converter.

【0021】[0021]

【課題を解決するための手段】本発明の特徴は、入力の
アナログ信号に対し、予じめ定められる桁数のディジタ
ル出力を与えるA/D変換器と、アナログ入力信号又は
該A/D変換器の入力端子にA/D変換器の最小分解能
にほぼ等しい振幅の傾斜電位を加える手段と、A/D変
換器の桁数より大きな桁数を有し、A/D変換器の複数
回のディジタル変換出力の平均値を与える演算回路とを
有し、該演算回路の桁数により定まる精度のディジタル
出力を与えるA/D変換装置において、前記A/D変換
回路はアナログ信号の入力部にコンデンサと抵抗による
時定数回路をふくむ積分回路を有し、前記傾斜電位は該
時定数回路のコンデンサを介して印加されるA/D変換
装置にある。
The features of the present invention are: an A / D converter for giving a digital output of a predetermined number of digits to an input analog signal; and an analog input signal or the A / D conversion. Means for applying a gradient potential having an amplitude substantially equal to the minimum resolution of the A / D converter to the input terminal of the A / D converter, and a number of digits greater than the number of digits of the A / D converter. In an A / D conversion device that has an arithmetic circuit that gives an average value of digital conversion outputs and that gives a digital output with an accuracy determined by the number of digits of the arithmetic circuit, the A / D conversion circuit has a capacitor at an input portion of an analog signal. And an A / D converter having an integrator circuit including a time constant circuit formed of a resistor, and the gradient potential is applied via a capacitor of the time constant circuit.

【0022】[0022]

【実施例】図1は本発明によるA/D変換装置を示し、
図2と同じ参照番号は同じものを示す。
1 shows an A / D converter according to the present invention,
The same reference numbers as in FIG. 2 indicate the same.

【0023】図1において、アナログ信号入力端子16
と接地点の間にコンデンサC01が挿入され、入力端子は
抵抗R11を介してA/D変換器10の入力に結合する。
A/D変換器10の入力にはコンデンサC11の一端が接
続され、その他端は、抵抗R21、R22及びコンデンサC
21、C22による積分回路60の出力に接続される。積分
回路60の入力端子50には矩形波(a)が印加され
る。
In FIG. 1, an analog signal input terminal 16
A capacitor C 01 is inserted between the input terminal and the ground point, and the input terminal is coupled to the input of the A / D converter 10 via the resistor R 11 .
One end of a capacitor C 11 is connected to the input of the A / D converter 10, and the other ends have resistors R 21 , R 22 and a capacitor C 11.
21 and C 22 are connected to the output of the integrating circuit 60. A rectangular wave (a) is applied to the input terminal 50 of the integrating circuit 60.

【0024】抵抗R11とコンデンサC11の時定数回路は
アナログ入力信号に対し積分回路70を構成し、この積
分回路は市販のA/D変換器の入力回路にノイズ吸収の
ために備えられていることが多い。その場合、コンデン
サC11の一端は接地されている。
The time constant circuit of the resistor R 11 and the capacitor C 11 constitutes an integrator circuit 70 for an analog input signal, and this integrator circuit is provided in the input circuit of a commercially available A / D converter for noise absorption. Often In that case, one end of the capacitor C 11 is grounded.

【0025】コンデンサC01はアナログ信号の出力イン
ピーダンスが積分回路70の時定数を変動させることを
防止するために挿入される。
The capacitor C 01 is inserted to prevent the output impedance of the analog signal from changing the time constant of the integrating circuit 70.

【0026】ディザ信号は積分回路60の入力端子50
に矩形波として印加される。積分回路60は2重積分回
路で、1度目の積分出力は(b)のごとき三角波とな
り、2度目の積分出力は(c)のごとき波形となる。
The dither signal is input to the integrating circuit 60 at the input terminal 50.
Is applied as a rectangular wave to. The integrating circuit 60 is a double integrating circuit, and the first integrated output has a triangular wave as shown in (b) and the second integrated output has a waveform as shown in (c).

【0027】積分回路60の出力((c)の波形)は、
積分回路70を構成するコンデンサC11の一端80に図
示のごとく印加され、該コンデンサC11を介してA/D
変換器10の入力に印加される。このとき、回路70は
アナログ入力信号に対しては積分回路として働くが、端
子80からのディザ信号に対しては微分回路として働
く。従って、A/D変換器10の入力におけるディザ信
号は図の(d)に示す三角波で、これは(b)の波形と
同じである。
The output of the integrating circuit 60 (waveform of (c)) is
The voltage is applied to one end 80 of the capacitor C 11 which constitutes the integrating circuit 70 as shown in the figure, and the A / D is applied via the capacitor C 11.
Applied to the input of transducer 10. At this time, the circuit 70 acts as an integrating circuit for the analog input signal, but acts as a differentiating circuit for the dither signal from the terminal 80. Therefore, the dither signal at the input of the A / D converter 10 is a triangular wave shown in (d) of the figure, which is the same as the waveform of (b).

【0028】コンデンサ及び抵抗の数値例は次のとおり
である。 C01=1μF R11=100KΩ R21=510KΩ R22=1MΩ C11=0.1μF C21=0.47μF C22=0.1μF
Numerical examples of capacitors and resistors are as follows. C 01 = 1 μF R 11 = 100 KΩ R 21 = 510 KΩ R 22 = 1 MΩ C 11 = 0.1 μF C 21 = 0.47 μF C 22 = 0.1 μF

【0029】結局、矩形波のディザ波形(a)は、2重
積分回路60と微分回路を介して、波形(d)の三角波
となる。
After all, the rectangular dither waveform (a) becomes a triangular wave of the waveform (d) through the double integrating circuit 60 and the differentiating circuit.

【0030】なお、ディザ波形(a)のデューティ比を
50%とすると、三角波(d)のディザ信号の平均値は
A/D入力に対し自動的に0になるので、ディザ信号の
ための回路の初期設定は不要である。
If the duty ratio of the dither waveform (a) is 50%, the average value of the dither signal of the triangular wave (d) automatically becomes 0 for the A / D input, so the circuit for the dither signal is No initial setting is required.

【0031】時定数回路70は市販のA/D変換器にも
ともと備わっていることが多いので、ディザ信号の注入
のために必要な回路は積分回路60のみで、極めて安価
で、電力消費がなく、又、受動素子のみで構成されるの
で動作が安定である。又、アナログ入力信号に対し、積
分機能による雑音防止作用を有し、ディザ注入のための
回路はアナログ入力信号に対し充分に高インピーダンス
で入力信号に影響を与えることはない。
Since the time constant circuit 70 is often originally provided in a commercially available A / D converter, the circuit required for injecting the dither signal is only the integrating circuit 60, which is extremely inexpensive and has no power consumption. Moreover, the operation is stable because it is composed of only passive elements. Further, the analog input signal has a noise prevention effect by the integration function, and the circuit for dither injection has a sufficiently high impedance with respect to the analog input signal and does not affect the input signal.

【0032】複数チャネルのアナログ入力を扱かう場合
には、積分回路60は全チャネルに共通に1個だけもう
け、その出力を、各チャネルの時定数回路70のコンデ
ンサC11の一端80に供給する。
When handling analog inputs of a plurality of channels, only one integrating circuit 60 is provided for all channels, and its output is supplied to one end 80 of the capacitor C 11 of the time constant circuit 70 of each channel. ..

【0033】なお、入力のディザ信号が矩形波でなく、
三角波で供給される場合には、積分回路60は2重積分
ではなく、単一積分回路とする。
Note that the input dither signal is not a rectangular wave,
When the triangular wave is supplied, the integrating circuit 60 is not a double integrating circuit but a single integrating circuit.

【0034】本発明をマイコンにより実現する場合に
は、A/D変換器10、演算回路14、矩形波(a)等
は市販のマイコン自身に実装されていることが多い。
又、積分回路70は雑音防止のため通常挿入は必須であ
る。
When the present invention is implemented by a microcomputer, the A / D converter 10, the arithmetic circuit 14, the rectangular wave (a), etc. are often mounted on a commercially available microcomputer itself.
Further, the integration circuit 70 is usually required to be inserted to prevent noise.

【0035】[0035]

【発明の効果】本発明によると、ディザ信号を極めて簡
単にかつ好適にアナログ信号に加算することができ、低
精度のA/D変換器により高精度のA/D変換を行なう
ことができ、特に、日常生活で需要の多い0.1%精度
の変換を市販の4ビットマイコンにより行なうことがで
きるので、本発明の適用領域は広い。
According to the present invention, the dither signal can be added to the analog signal very easily and preferably, and the high precision A / D conversion can be performed by the low precision A / D converter. In particular, since the conversion of 0.1% accuracy, which is in great demand in daily life, can be performed by a commercially available 4-bit microcomputer, the applicable range of the present invention is wide.

【0036】[0036]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるA/D変換装置の実施例である。FIG. 1 is an embodiment of an A / D conversion device according to the present invention.

【図2】従来のA/D変換装置である。FIG. 2 is a conventional A / D conversion device.

【符号の説明】[Explanation of symbols]

10 A/D変換器 12 加算器 14 演算回路 16 アナログ信号入力端子 18 ディジタル信号出力端子 50 ディザ信号入力端子 60,70 積分回路 10 A / D converter 12 Adder 14 Arithmetic circuit 16 Analog signal input terminal 18 Digital signal output terminal 50 Dither signal input terminal 60, 70 Integration circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力のアナログ信号に対し、予じめ定め
られる桁数のディジタル出力を与えるA/D変換器と、 アナログ入力信号又は該A/D変換器の入力端子にA/
D変換器の最小分解能にほぼ等しい振幅の傾斜電位を加
える手段と、 A/D変換器の桁数より大きな桁数を有し、A/D変換
器の複数回のディジタル変換出力の平均値を与える演算
回路とを有し、該演算回路の桁数により定まる精度のデ
ィジタル出力を与えるA/D変換装置において、 前記A/D変換回路はアナログ信号の入力部にコンデン
サと抵抗による時定数回路をふくむ積分回路を有し、 前記傾斜電位は該時定数回路のコンデンサを介して印加
されることを特徴とするA/D変換装置。
1. An A / D converter that provides a predetermined number of digits of digital output to an input analog signal, and an analog input signal or an A / D converter at an input terminal of the A / D converter.
A means for applying a gradient potential whose amplitude is almost equal to the minimum resolution of the D converter and a digit number larger than the digit number of the A / D converter, and the average value of the digital conversion outputs of the A / D converter at a plurality of times. In an A / D conversion device having an arithmetic circuit for giving a digital output with an accuracy determined by the number of digits of the arithmetic circuit, the A / D conversion circuit includes a time constant circuit composed of a capacitor and a resistor at an analog signal input portion. An A / D converter having an integrating circuit including the gradient electric potential is applied via a capacitor of the time constant circuit.
JP3275047A 1991-06-27 1991-09-27 A / D converter Expired - Fee Related JP2626352B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP3275047A JP2626352B2 (en) 1991-09-27 1991-09-27 A / D converter
US07/897,152 US5305005A (en) 1991-06-27 1992-06-11 Analog to digital converter system
EP92305475A EP0520662B1 (en) 1991-06-27 1992-06-15 Analog to digital converter with increased resolution
DE69219216T DE69219216T2 (en) 1991-06-27 1992-06-15 Analog-digital converter with increased resolution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3275047A JP2626352B2 (en) 1991-09-27 1991-09-27 A / D converter

Publications (2)

Publication Number Publication Date
JPH0590964A true JPH0590964A (en) 1993-04-09
JP2626352B2 JP2626352B2 (en) 1997-07-02

Family

ID=17550118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3275047A Expired - Fee Related JP2626352B2 (en) 1991-06-27 1991-09-27 A / D converter

Country Status (1)

Country Link
JP (1) JP2626352B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05276042A (en) * 1992-03-27 1993-10-22 Isao Takahashi A/d converter
JP2012019320A (en) * 2010-07-07 2012-01-26 Tanita Corp A/d conversion device, a/d conversion method, and electronic apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5148262A (en) * 1974-10-23 1976-04-24 Sony Corp DEIJITARU SHINGOHOSHIKI
JPS63252015A (en) * 1987-04-09 1988-10-19 Nippon Precision Saakitsutsu Kk D/a converting device
JPH02260821A (en) * 1989-03-31 1990-10-23 Mitsubishi Motors Corp A/d conversion system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5148262A (en) * 1974-10-23 1976-04-24 Sony Corp DEIJITARU SHINGOHOSHIKI
JPS63252015A (en) * 1987-04-09 1988-10-19 Nippon Precision Saakitsutsu Kk D/a converting device
JPH02260821A (en) * 1989-03-31 1990-10-23 Mitsubishi Motors Corp A/d conversion system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05276042A (en) * 1992-03-27 1993-10-22 Isao Takahashi A/d converter
JP2012019320A (en) * 2010-07-07 2012-01-26 Tanita Corp A/d conversion device, a/d conversion method, and electronic apparatus

Also Published As

Publication number Publication date
JP2626352B2 (en) 1997-07-02

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