JPH07101223B2 - Peak value detection circuit - Google Patents

Description

The present invention relates to a circuit for detecting the peak value of a pulse wave that is repeatedly input.

[Prior Art] As is well known, a group of pulse waves of P wave, R wave, and T wave appear periodically in the electrocardiogram waveform. To detect the peak value of this pulse wave (the R wave has the highest peak value, the peak value of the R wave), a peak value detection circuit as shown in FIG. 2 is used.

In FIG. 2, A ₁ and A ₂ are differential amplifiers, R _{1 to} R ₃ are resistors, D is a diode, and C is a capacitor. 3rd at input terminal T ₁
A pulse wave such as W in the figure is repeatedly input. T represents the repetition period of the pulse wave W, and t represents the pulse width of the maximum amplitude pulse in the pulse wave (pulse group) W. Amplifier A _{2 in} Figure ₂
Since is negatively fed back 100%, the gain is 1, and it works as a mere buffer. The capacitor C is charged with the output of the amplifier A ₁ via the diode D, and its terminal voltage is taken out to the output terminal T ₂ via the buffer A ₂ . This capacitor voltage is fed back to the amplifier A ₁ through the resistor R ₃ and
The to A ₁ input signal (pulse wave W) is applied via a resistor R _1, therefore the amplifier A ₁ and exceeds the voltage input signal is fed back from the output terminal T ₂ side (the voltage of the capacitor C) output Occurs and charges the capacitor C with the output voltage via the diode D.

[Problems to be solved by the invention]

In this way, the voltage of the capacitor C shows the peak value of the input signal, which is output to the terminal T ₂ via the buffer A ₂ , but its waveform fluctuates as shown by the curve C ₁ in FIG. . That is, the capacitor C is charged with the voltage of the amplifier A ₁ , has a peak value PK at the peak of the input signal pulse, but gradually decreases after that due to self-discharge, etc., is charged again to the peak value at the input of the next pulse, and then gradually decreases again. Go through the process of doing. Therefore, if monitored with an instrument that displays the average value, the peak value becomes the chain line level L in Fig. 4,
It will be lower than the actual peak value.

When the period T of the input signal is large, the decrease in the capacitor voltage increases, and the decrease in the level L becomes large. The decrease of the capacitor voltage can be suppressed by increasing the capacitance of the capacitor. Therefore, it is preferable to increase the capacitance of the capacitor C for an input signal having a long period T. On the other hand, in order to detect the peak value of a pulse having a small pulse width t, it is preferable that the capacitance of the capacitor C is small (if the capacitance is large, the pulse disappears before being fully charged). It is an antinomy issue. Therefore, in the conventional circuit as shown in FIG. 2, the peak value that can be detected without unavoidable decrease of the capacitor voltage is the average value L,
It is lower than the actual peak value PK, and it is difficult to keep these deviations within 1%.

An object of the present invention is to provide a circuit that detects the peak value of a signal that is repeatedly input with good linearity and accuracy even if the width of the peak pulse is small.

[Means for solving problems]

The present invention provides a comparator in which an input signal whose peak value is detected is input to one input terminal and a reference voltage is input to the other input terminal, and an ON signal output by the comparator while the input signal exceeds the reference voltage. A counter for counting signals; and a digital / analog converter for D / A converting the count value of the counter and inputting the D / A converted value to the other input terminal of the comparator as the reference voltage, From the converter and an analog output from the converter.

[Action]

In the present invention, the monotonicity of the counter and the highly accurate linearity of the output of the D / A converter are used, and the high accuracy and responsiveness of the comparator are used to make the high frequency input repeatedly in a long cycle. The peak value of the signal is detected with higher linearity and higher accuracy. The output may be analog or digital, and the output value can be maintained unchanged over a long period of time.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and FIG. 3 shows a waveform diagram for explaining its operation. 10 is a counter, 12 is a D / A converter, and 14 is a comparator. 16 is an amplifier. The above-mentioned input signal pulse enters the input terminal Ta, and after being amplified by the amplifier 16,
It is input to one input terminal of the comparator 14. This input signal is shown in FIG. The output of the D / A converter 12 is input to the other input terminal of the comparator 14 as a reference voltage. This reference voltage is shown by the dotted line in FIG. The output of the amplifier 16 of the comparator 14 is D / A
When the reference voltage of the output of the converter 12 is exceeded, FIG. 3 (b)
Produces an ON signal output as shown in. The output (ON signal) of the comparator 14 is input to the counter 10 and counted. The counter 10 is generally composed of a T flip-flop or a JK flip-flop and operates at the falling edge of the input pulse. In this case, therefore, the output of the comparator 14 changes to the falling edge of the ON signal, that is, the OFF signal. The counting operation is performed at the time point. FIG. 3 (C) shows the counting waveform. The count value of the counter 10 is digital-analog converted by the converter 12, and the D / A converted value becomes the other input of the comparator 14 and is used as a reference voltage.

The counter 10 is reset to the initial value 0, so that the D / A
The output of the converter 12 is initially 0. Therefore, when a signal pulse is input to the terminal Ta, the comparator 14 generates an ON signal and sets the count value of the counter 12 to 1. This count value 1 is converted by the converter 12.
If the next pulse that is D / A converted and fed back to the comparator 14 and is input to the terminal Ta (specifically, the peak value of the pulse multiplied by the gain of the amplifier 16) exceeds this D / A converted value, the comparator 14 Generates an ON signal again, and sets the count value of the counter 12 to 2. The same applies hereinafter, and the counter 12 increments by 1 each time an input signal enters the terminal Ta and increases the count value.
The output V _{2 of the} D / A converter 12 is the input signal (more specifically, V of the amplifier 16).
₁ ) The above-mentioned comparator 14 does not generate an ON signal, and the counter 10 stops counting. This state is illustrated in the right part of FIG. In the illustrated example, the count value (n + 1) of the counter 10 indicates the digital value of the peak value of the input signal,
The output of the D / A converter 12 in FIG. 1 shows the D / A conversion value. Tc
Is a terminal for taking out the digital output, and Tb is a terminal for taking out the analog output.

Comparator 14 V _1> resulting output (positive pulse) when V _2, no output at V ₁ V _2. The voltage difference ΔV = V ₁ −V ₂ when the comparator 14 produces an output is closer to zero as the gain of the comparator 14 is higher. However, since the gain is limited, ΔV = 0 is not satisfied. This voltage difference ΔV can be compensated by the amplifier 16. That is, assuming that the peak value of the input signal is V ₃ and the gain of the amplifier 16 is G, V ₁ = GV _{3 and} therefore ΔV = G
Since a V ₃ -V ₂ can produce an output to the comparator 14 until V ₃ = V ₂ if the _{G = 1 + ΔV / V 3} .
Since V ₃ is an unknown value, the gain G cannot be correctly set to the desired value, but can be adjusted to a value in the vicinity thereof. If the gain of the comparator 14 is increased to the extent that it can be regarded as ΔV = 0, the amplifier 16 is unnecessary or can be a simple buffer with G = 1.

In this circuit, the counter count value can be held at that value permanently, so that the digital output and analog output can be kept unchanged, and there is no attenuation due to discharge as shown by C ₁ in FIG. Also, after the counter 10 stops counting,
Since the value is incremented only when an input signal having a larger peak value is input, the count value of the counter and therefore the digital and analog outputs show the maximum peak value during the measurement period. The measurement period can be newly started by resetting the counter 10. Therefore, although not shown, the counter 10 is provided with a reset circuit. The output line of the counter 10 is shown as one line in the figure, but of course, it is composed of a plurality of lines according to the number of stages of the counter.

The input signal pulse input to the terminal Ta is not limited to the electrocardiogram waveform as a matter of course, and may be any arterial signal or AC signal.

〔The invention's effect〕

As described above, according to the present invention, since the peak value can be represented by the value of the counter that monotonically and linearly increases, the precision is high and the output can be represented by multi-bits such as 8 to 9 bits. It is possible to obtain a result with excellent linearity, and it is possible to obtain the peak value of both digital value and analog value.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, and FIGS. 3 and 4 are waveform diagrams for explaining the operation. In the drawing, 10 is a counter, 12 is a D / A converter, and 14 is a comparator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-50-160079 (JP, A) JP-A-51-146869 (JP, A) Actual development-Sho 53-42652 (JP, U) JP-B 57- 12235 (JP, B2)

Claims (1)

[Claims] 1. A comparator in which an input signal whose peak value is detected is input to one input terminal and a reference voltage is input to the other input terminal, and the comparator outputs while the input signal exceeds the reference voltage. A counter for counting the ON signal; and a digital / analog converter for D / A converting the counter count value and inputting the D / A converted value to the other input terminal of the comparator as the reference voltage, A peak value detection circuit, wherein a digital output is taken out from a counter and an analog output is taken out from the converter.