KR0119811Y1 - Multi-mode distinction circuit - Google Patents
Multi-mode distinction circuitInfo
- Publication number
- KR0119811Y1 KR0119811Y1 KR2019940016029U KR19940016029U KR0119811Y1 KR 0119811 Y1 KR0119811 Y1 KR 0119811Y1 KR 2019940016029 U KR2019940016029 U KR 2019940016029U KR 19940016029 U KR19940016029 U KR 19940016029U KR 0119811 Y1 KR0119811 Y1 KR 0119811Y1
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- mode
- synchronous signal
- frequency
- horizontal synchronous
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/63—Generation or supply of power specially adapted for television receivers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
본 고안은 다중모드모니터의 모드판별회로에 관한 것으로, 수평동기신호와 수직동기신호의 주파수비로 모드를 판별함으로써 2모드만을 판별할 수 있었던 종래와는 달리, 외부로부터 입력된 정극성 수평동기신호 또는 부극성 수평동기신호를 부극성동기신호로 변환하는 극성보정수단과, 상기 극성보정수단의 변환으로 얻어진 부극성 수평동기신호의 주파수에 대응하는 직류전압을 발생하는 주파수/직류전압변환수단과, 상기 파수/직류전압발생수단이 발생한 직류전압을 소정의 기준전압과 비교판단하여 모드를 판별하는 비교수단으로 구성되어, 수평동기신호와 수직동기신호의 주파수비 대신에 수평동기신호의 주파수만을 이용하여 3모드판별을 할 수 있도록 한 것이다.The present invention relates to a mode discrimination circuit of a multi-mode monitor, and unlike the conventional method in which only two modes can be determined by discriminating modes by the frequency ratio of the horizontal synchronous signal and the vertical synchronous signal, the positive horizontal synchronous signal inputted from the outside or Polarity correction means for converting the negative horizontal synchronous signal into a negative synchronous signal, frequency / DC voltage converting means for generating a DC voltage corresponding to a frequency of the negative horizontal synchronous signal obtained by the conversion of the polarity correction means; Comprising a comparison means for determining the mode by comparing the DC voltage generated by the wave number / DC voltage generating means with a predetermined reference voltage, using only the frequency of the horizontal synchronous signal instead of the frequency ratio of the horizontal synchronous signal and the vertical synchronous signal 3 The mode can be determined.
Description
제1도는 본 고안 다중모드모니터의 모드 판별회로도.1 is a mode discrimination circuit diagram of a multi-mode monitor of the present invention.
제2도는 본 고안에서 부극성 수평동기신호를 입력받은 극성보정부의 각단 파형도.2 is a waveform diagram of each stage of the polarity correction unit receiving the negative horizontal synchronization signal in the present invention.
제3도는 본 고안에서 정극성 수평동기신호를 입력받은 극성보정부의 각단 파형도.3 is a waveform diagram of each stage of the polarity correction unit receiving the positive horizontal synchronization signal in the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101: 극성보정부 102: 주파수/직류전압변환부101: polarity correction 102: frequency / DC voltage conversion unit
103: 비교부103: comparison unit
본 고안은 다중모드모니터에 관한 것으로, 특히 수평동기신호만을 이용하여 3모드를 정확히 판별할 수 있는 다중모드모니터의 주파수 판별회로에 관한 것이다.The present invention relates to a multi-mode monitor, and more particularly, to a frequency discrimination circuit of a multi-mode monitor capable of accurately determining three modes using only horizontal synchronization signals.
일반적으로 주파수판별회로는 다중모드모니터에 있어 필수적인 회로로써, 종래에는 다중모드모니터의 주파수판별회로를 게이트 어레이 집적회로(Gate Arry IC)를 이용하여 구성하고, 수평동기신호와 수직동기신호의 주파수비로서 모드(31KHz 모드, 35KHz 모드, 38KHz 모드)판별을 하였다.In general, a frequency discrimination circuit is an essential circuit for a multi-mode monitor. In the related art, a frequency discrimination circuit of a multi-mode monitor is constructed using a gate array IC, and a frequency ratio of a horizontal synchronous signal and a vertical synchronous signal is used. The mode (31KHz mode, 35KHz mode, 38KHz mode) was discriminated.
이와같이 수평동기신호와 수직동기신호의 주파수비로서 모드를 판별하는 종래 다중모드모니터의 주파수판별회로의 문제점은, 수평동기신호와 수직동기신호의 주파수비가 서로 다른 35KHz 모드와 38KHz 모드간에는 모드구분이 되지만, 수평동기신호와 수평주파수의 주파수비가 동일한 31KHz 모드와 35KHz 모드간에는 모드구분이 되지 않으므로, 결국 2모드밖에 판별할 수 없다는 것이다.The problem of the frequency discrimination circuit of the conventional multi-mode monitor that determines the mode as the frequency ratio of the horizontal synchronous signal and the vertical synchronous signal is that the mode is divided between the 35 kHz mode and the 38 kHz mode where the frequency ratios of the horizontal synchronous signal and the vertical synchronous signal are different. Therefore, since the mode is separated between the 31KHz mode and the 35KHz mode where the horizontal synchronous signal and the horizontal frequency have the same frequency ratio, only two modes can be determined.
따라서, 본 고안의 목적은, 수평동기신호와 수직동기신호의 주파수비를 이용하지 않고 수평동기신호의 주파수만을 이용함으로써 3모드를 판별할 수 있는 다중모드모니터의 주파수판별회로를 제공하는 것이다.Accordingly, an object of the present invention is to provide a frequency discrimination circuit of a multi-mode monitor capable of discriminating three modes by using only the frequency of the horizontal synchronous signal without using the frequency ratio of the horizontal synchronous signal and the vertical synchronous signal.
상기 목적에 따른 본 고안 다중모드모니터의 주파수판별회로는, 외부로부터 입력된 정극성 또는 부극성 수평동기신호를 부극성 수평동기신호로 변환하는 극성보정부와, 상기 극성보정부에서의 변환으로 얻어진 부극성 수평동기신호의 주파수에 대응하는 직류전압을 발생하는 주파수/직류전압변환부와, 상기 주파수/직류전압변환부에서 발생한 직류전압을 소정의 기준 전압과 비교하여 모드를 판별하는 비교부로 구성된다.The frequency discrimination circuit of the present invention multi-mode monitor according to the above object comprises a polarity correction unit for converting a positive or negative horizontal synchronization signal input from the outside into a negative horizontal synchronization signal, and a conversion in the polarity correction unit. A frequency / DC converter for generating a DC voltage corresponding to the frequency of the negative horizontal synchronous signal, and a comparator for discriminating a mode by comparing the DC voltage generated by the frequency / DC converter with a predetermined reference voltage. .
이와같이 구성된 본 고안에 대하여 하나의 실시예를 나타낸 제1도 내지 제3도를 참조하여 본 고안의 작용 및 효과를 상세히 설명한다.The operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 3 showing one embodiment of the present invention configured as described above.
외부로부터 제2도 (a)와 같은 부극성 수평동기신호(정극성 수평동기신호도 무관)가 본 실시예 다중모드모니터의 주파수판별회로에 입력되면, 그 부극성 수평동기신호는 극성보정부(101)의 제1배타적오아게이트(XOR1)의 일측 입력단자에 입력되는데, 이때 제1배타적오아게이트(XOR1)의 다른 입력단자는 그라운드에 접지되어 있으므로 그 제1배타적오아게이트(XOR1)에서는 (b)와 같은 부극성 수평동기신호가 그대로 출력되어 적분동작하는 저항(R1)과 콘덴서(C1)로 적분되어 (c)의 파형을 갖는 수평동기신호로 변환된다.When a negative horizontal synchronizing signal (regardless of the positive horizontal synchronizing signal) as shown in Fig. 2 (a) from the outside is input to the frequency discrimination circuit of the multi-mode monitor of this embodiment, the negative horizontal synchronizing signal is subjected to polarity correction ( The input signal is input to one input terminal of the first exclusive ogate XOR1 of 101. At this time, the other input terminal of the first exclusive ogate XOR1 is grounded to the ground, so that the first exclusive ogate XOR1 is connected to (b). Negative polarity horizontal synchronizing signal such as) is output as it is and integrated into the resistor R1 and condenser C1 integrating operation and converted into a horizontal synchronizing signal having a waveform of (c).
이처럼 저항(R1)과 콘덴서(C1)의 적분으로 얻어진 (c)의 수평동기신호는 바로 제2배타적오아게이트(XOR2)의 일측 입력단자에 인가되며, 이에 따라 그 제2배타적오아게이트(XOR2)는 그 (c)의 수평동기신호와 다른 입력단자에 인가된 (a)의 수평동기신호에 대해 배타적오아연산(두 입력신호가 다를 경우에만 하이신호 출력하는 연산)을 수행하여 (d)와 같은 정극성의 수평동기신호를 만들어 내고, 레벨을 시프트시키는 콘덴서(C2), 저항(R2)(R3) 및 트랜지스터(Q1)를 통해 (e)와 같은 반전된 수평동기신호를 만들어낸다.Thus, the horizontal synchronizing signal of (c) obtained by the integration of the resistor R1 and the capacitor C1 is applied directly to one input terminal of the second exclusive ogate XOR2, whereby the second exclusive ogate XOR2. (C) performs an exclusive error operation (operation that outputs a high signal only when the two input signals are different) with respect to the horizontal synchronous signal of (a) applied to the other terminal. An inverted horizontal synchronization signal such as (e) is generated through the capacitor C2, the resistors R2, R3, and the transistor Q1 which produce a positive horizontal synchronization signal and shift the level.
한편, 주파수/직류전압변환부(10)의 단안정멀티바이브레이터(102a)는 극성보정부(101)가 만들어 낸 (e)의 수평동기신호를 입력단자(IN)를 통해 입력받아 제3도의 (f)와 같은 펄스신호를 발생하며, 이 펄스신호는 적분동작을 하는 저항(R4)과 콘덴서(C4)로 적분되고 역시 적분동작을 하는 저항(R5)과 콘덴서(C5)로 다시 한번 적분되어 직류전압이 된다. 이때, 이 직류전압의 크기는 외부로부터 극성보정부(101)에 입력된 수평동기신호의 주파수에 따라 달라진다.On the other hand, the monostable multivibrator 102a of the frequency / DC voltage converter 10 receives the horizontal synchronization signal of (e) generated by the polarity compensator 101 through the input terminal IN, and f) generates a pulse signal, which is integrated into the resistor R4 and the capacitor C4, which are integrated, and integrated once again into the resistor R5 and C5, which is also integrated. It becomes a voltage. At this time, the magnitude of the DC voltage varies depending on the frequency of the horizontal synchronization signal input to the polarity correction unit 101 from the outside.
한편, 비교부(103)에서는 상기 주파수/직류전압변환부(102)에서의 변환으로 얻어진 직류전압이 증폭기(OP1)로 증폭되어 비교가능한 크기의 직류전압이 되면, 제1비교기(OP2)와 제2비교기(OP3)의 비반전입력단자(+)에 입력하여 반전단자(-)에 인가되어 있는 제1기준전압(Vref1)과 제2기준전압(Vref2)과 비교되도록 한다.On the other hand, in the comparison unit 103, when the DC voltage obtained by the conversion in the frequency / DC voltage conversion unit 102 is amplified by the amplifier OP1 and becomes a DC voltage of comparable magnitude, the first comparator OP2 and the first comparator It is input to the non-inverting input terminal (+) of the second comparator OP3 to be compared with the first reference voltage V ref1 and the second reference voltage V ref2 applied to the inverting terminal (−).
즉, 제1비교기(OP2)는 증폭기(OP1)에서 증폭된 직류전압이 저항(R9-R11)으로 분압되어 반전단자(-)에 인가된 제1기준전압(Vref1)보다 크면 하이상태의 제1모드판별신호를 작으면 로우상태의 제1모드판별신호를 출력하고, 제2비교기(OP3)는 증폭기(OP2)에서 증폭된 직류전압이 저항(R9-R11)으로 분압되어 반전단자(-)에 인가된 제2기준전압(Vref2)보다 크면 하이상태의 제2모드판별신호를 작으면 로우상태의 제2모드판별신호를 출력한다.That is, the first comparator OP2 has a high state when the DC voltage amplified by the amplifier OP1 is divided by the resistors R9-R11 and is greater than the first reference voltage Vref1 applied to the inverting terminal-. When the mode discrimination signal is small, the first mode discrimination signal in a low state is output, and the second comparator OP3 divides the DC voltage amplified by the amplifier OP2 into the resistors R9-R11 to the inverting terminal (-). If the second mode discrimination signal in the high state is smaller than the applied second reference voltage Vref2, the second mode discrimination signal in the low state is output.
여기서,here,
이다.to be.
이때, 제1비교기(OP2)에서 로우상태의 제1모드판별신호가 출력되고 제2비교기(OP3)에서도 로우상태의 제2모드판별신호가 출력되면 31 KHz 모드이며, 제1비교기(OP2)에서 로우상태의 제1모드판별신호가 출력되고 제2비교기(OP3)에서 하이상태의 제2모드판별신호가 출력되면 35 KHz 모드이고, 반대로 제1비교기(OP2)에서 하이상태의 제1모드판별신호가 출력되고 제2비교기(OP3)에서 하이상태의 제2모드판별신호가 출력되면 38 KHz 모드임을 나타낸다.At this time, when the first mode discrimination signal in the low state is output from the first comparator OP2 and the second mode discrimination signal in the low state is also output from the second comparator OP3, the mode is 31 KHz. When the first mode discrimination signal in the low state is output and the second mode discrimination signal in the high state is output from the second comparator OP3, it is in 35 KHz mode, and conversely, the first mode discrimination signal in the high state is operated by the first comparator OP2. Is output and the second mode discrimination signal of the high state is output from the second comparator OP3, indicating that the mode is 38 KHz.
제3도는 외부로부터 정극성 수평동기신호가 입력되는 경우에 그 정극성 수평동기신호를 부극성 수평동기신호로 변환하는 상기 극성보정부(101)의 각단 파형도로서, 제2도의 경우와 동작이 동일하므로 그 동작설명은 생략한다.FIG. 3 is a waveform diagram of each stage of the polarity compensator 101 which converts a positive horizontal synchronous signal into a negative horizontal synchronous signal when a positive horizontal synchronous signal is input from the outside. Since the operation is the same, a description of the operation is omitted.
이상에서 상세히 설명한 바와같이, 본 고안은 수평동기신호와 수직동기신호의 주파수비로 모드를 판별함으로써 2모드만을 판별할 수 있었던 종래와는 달리, 모드판별 수평동기신호의 주파수만을 이용함으로써 3모드판별을 할 수 있다는 효과를 갖늦다.As described in detail above, the present invention is different from the conventional method in which only two modes can be determined by determining modes by the frequency ratio of the horizontal synchronous signal and the vertical synchronous signal. It has the effect that it can be done.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940016029U KR0119811Y1 (en) | 1994-06-30 | 1994-06-30 | Multi-mode distinction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940016029U KR0119811Y1 (en) | 1994-06-30 | 1994-06-30 | Multi-mode distinction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960003421U KR960003421U (en) | 1996-01-22 |
| KR0119811Y1 true KR0119811Y1 (en) | 1998-07-15 |
Family
ID=19387303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019940016029U KR0119811Y1 (en) | 1994-06-30 | 1994-06-30 | Multi-mode distinction circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0119811Y1 (en) |
-
1994
- 1994-06-30 KR KR2019940016029U patent/KR0119811Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960003421U (en) | 1996-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH057154A (en) | A/d converter circuit | |
| JP2007121189A (en) | Peak detection circuit and radiation measuring apparatus | |
| JP2000009409A (en) | Circuit for detecting variation of inductance | |
| KR0119811Y1 (en) | Multi-mode distinction circuit | |
| JPS5925267B2 (en) | optical character reader | |
| JP2856787B2 (en) | Binarization circuit, intermediate level detection circuit, and peak envelope detection circuit | |
| US6445219B1 (en) | Method and circuit configuration for converting a frequency signal to a DC voltage | |
| JPH10190463A (en) | Signal processor | |
| JPH0775336B2 (en) | Optical receiver circuit | |
| KR0120585B1 (en) | Sp/lp mode detection circuit | |
| SU995356A1 (en) | Bi-pulse signal-to-binary signal converter | |
| US7224193B2 (en) | Current-voltage conversion circuit | |
| JP2754540B2 (en) | Pulse counting type detector | |
| JPH07101223B2 (en) | Peak value detection circuit | |
| JPS6290550A (en) | Method for detecting peak value | |
| JPH0566235A (en) | Peak holding circuit, peak detecting circuit and peak-position detecting circuit | |
| SU1465938A1 (en) | Multivibrator | |
| KR100204614B1 (en) | Indicating circuit for adjusting direction of satellite signal receiving antenna | |
| RU2018137C1 (en) | Voltage-time interval transducer | |
| JPH07131489A (en) | Receiving circuit for light signal | |
| JPH05215850A (en) | Ultrasonic range finder | |
| JP3423150B2 (en) | Level detection circuit | |
| JPH04193165A (en) | Ultrasonic diagnostic device | |
| JPS6258717A (en) | Receiving circuit for optical binary signal | |
| JPS6381289A (en) | Distance measuring equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20080218 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |