JPS6151451B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention converts two systems of digital quantities into pulse signals having an active level period that changes according to the digital quantities, and then
The present invention provides a digital-to-analog conversion device that synthesizes pulse signals of the two systems and generates a pulse signal whose active level period changes in accordance with changes in either of the two systems of digital quantities.

Conventionally, as a method of converting two systems of digital quantities into pulse signals having an active level period that changes according to the digital quantities, and then synthesizing the converted two systems of pulse signals, for example, Tamura et al. ：“Digital Signal
Processing LSI for Home VTR Servo
Circuit”IEEE Transactions on Consumer
Electronics, Vol.CE−25 PP429−438 (1979)
The method shown in is often used. The circuit configuration of the main part is shown in FIG. To explain this, 1 is a frequency division counter that counts clock pulses applied to the CL terminal, and the outputs Q ₁ to Q _o of the frequency division counter 1 are connected to one input terminal group A ₁₁ to one of the first digital comparators 2. A _1o , input terminal group A ₂₁ to _{A 2o} of the second digital comparator 3,
It is applied to the input terminal of NOR gate 4 for count start detection.

First digital data D ₁₁ -D _1o are applied to the other input terminal group B ₁₁ -B _1o of the first digital comparator 2, and the other input terminals B ₂₁ -B of the second digital comparator 3 are applied. Second digital data D ₂₁ to D _2o are applied to _2o .

Further, the output terminal _C1 of the first digital comparator 2 is connected to the reset terminal Rx of the first RS flip-flop 5, and the output terminal _C2 of the second digital comparator 3 is connected to the reset terminal Rx of the second RS flip-flop 6. Connected to terminal Ry.

Further, a first smoothing circuit consisting of a resistor 7 and a capacitor 8 is connected to the output terminal Qx of the first RS flip-flop 5, and the output of the first smoothing circuit is connected to the output terminal Qx of the first RS flip-flop 5. The signal is applied to the output terminal OUT via an attenuation circuit.

On the other hand, a second smoothing circuit consisting of a resistor 11 and a capacitor 12 is connected to the output terminal Qy of the second RS flip-flop 6, and the output of the second smoothing circuit is connected to the output terminal Qy of the second RS flip-flop 6.
is applied to the signal output terminal OUT via an attenuation circuit.

In this device, the first input digital data
D ₁₁ ~D _1o and second input digital data D ₂₁ ~D
The pulse signal waveform having an active level period corresponding to each of the _2o values is converted into a so-called PWM signal, and each PWM signal is applied to a smoothing circuit separately to convert it to a DC level, and then a resistor circuit converts it into a DC level. It is being synthesized.

Therefore, the level of the output signal appearing at the signal output terminal OUT changes corresponding to both the first and second input digital data.

By the way, such a device is a monolithic IC.
In this case, the input/output terminals that are originally required are the clock terminal CL and the first and second input digital terminals D11 to _D11 .
_1o and D ₂₁ to D _2o (However, in many cases, the block that generates the signal corresponding to the input digital data is also housed within the same IC chip, so this terminal goes inside the IC and is different from the external connection terminal. ) This is the signal output terminal OUT, but it is generally difficult to insert a smoothing capacitor inside the IC, and the total cost of the system will be lower if it is an external component.

Therefore, the output terminals Qx and Qy of the first and second RS flip-flops usually serve as external terminals, resulting in an increase in the number of terminals beyond what is originally required.

This number of IC terminals naturally leads to an increase in the size of the IC package, which impedes the miniaturization of devices and the reduction in the amount of resin material used in the IC manufacturing process.

Furthermore, by configuring a smoothing circuit and a resistance attenuation circuit outside the IC, the synthesis ratio of the two signal systems can be freely and continuously adjusted. This presents an inconvenience in that the composition ratio changes due to changes or the like.

The present invention provides a digital-to-analog converter that can solve the above problems.

Hereinafter, the present invention will be explained based on illustrated embodiments. FIG. 2 is a block diagram of a logic circuit according to an embodiment of the present invention. In the same figure, T flip-flop 1
4, 15, 16, 17, 18, and 19 constitute a 6-bit down counter 71, and the clock terminal T of the T flip-flop 14 is connected to the clock pulse input terminal CL.

The input terminal of an AND gate 20 is connected to the inverting output terminal ₅ of the T flip-flop 18 and the non-inverting output terminal Q ₅ of the T flip-flop 17, _respectively . are connected to the input terminals of the AND gate 21, respectively, and the output terminals of the AND gate 21 and the inverting output terminal ₂ of the T flip-flop 15 are connected to the input terminals of the AND gate 21, respectively.
The input terminal of the AND gate 22 is connected to the
The output terminal of the AND gate 20 and the inverting output terminal ₃ of the T flip-flop 16 are connected to each other.
The input terminal of the AND gate 23 is connected, and the T
The input terminal of an AND gate 24 is connected to the inverting output terminal ₄ of the flip-flop 17 and the inverting output terminal ₅ of the T flip-flop 18, respectively.

Further, the input terminal of a NAND gate 25 is connected to the output terminal of the AND gate 22 and the digital input terminal D ₁₁ , respectively.
The input terminal of the NAND gate ₂₆ is connected to the output terminal of 3 and the digital input terminal D12, respectively.
The input terminal of a NAND gate 27 is connected to the output terminal of the AND gate 24 and the digital input terminal _D13 , respectively, and the input terminal of the T flip-flop 18 is connected to the output terminal of the AND gate 24 and the digital input terminal D13.
The input terminals of a NAND gate 28 are connected to the non-inverting output terminal Q ₅ and the digital input terminal D ₁₄ , respectively, and the output terminals of the NAND gates 25 to 28 are respectively connected to the input terminals of an AND gate 29. .

Furthermore, the inverting output terminal ₆ and digital input terminal D ₁₅ of the T flip-flop 19 are connected to each other.
The input terminals of the NAND gate 30 and the NOR gate 31 are connected, the output terminal of the NOR gate 31 and the output terminal of the AND gate 29 are respectively connected to the input terminal of an OR gate 32, and the output terminal of the NAND gate 30 A NAND gate 33 is connected to the output terminal of the OR gate 32, respectively.
input terminal is connected.

On the other hand, the input terminal of an AND gate 34 is connected to the non-inverting output terminal Q ₆ of the T-flip-flop 19 and the non-inverting output terminal Q ₅ of the T-flip-flop 18, respectively.
The input terminal of an AND gate 35 is connected to the inverting output terminal ₃ of the T flip-flop 6 and the inverting output terminal ₂ of the T flip-flop 15, respectively.
AND gate 3 is connected to non-inverting output terminal Q ₁ of
The input terminal of an inverter 37 is connected to the clock pulse input terminal CL, and the input terminal of an AND gate 38 is connected to the output terminal of the AND gate 36 and the output terminal of the inverter 37, respectively. and the output terminal of the AND gate 35 and the T flip-flop 14
The inverting output terminal ₁ of the T-flip-flop 16 is connected to the input terminal of an AND gate 39, and the inverting output terminal ₃ of the T-flip-flop 16 and the inverting output terminal ₂ of the T-flip-flop 15 are connected, respectively.
The input terminal of AND gate 40 is connected.

Further, the input terminal of a NAND gate 41 is connected to the output terminal of the AND gate 38 and the digital input terminal _D21 , respectively, and the input terminal of the NAND gate 38 is connected to the digital input terminal D21.
The input terminal of the NAND gate 42 is connected to the output terminal D 9 and the digital input terminal D ₂₂ , respectively.
The input terminal of the NAND gate 43 is connected to the output terminal of the AND gate 40 and the digital input terminal _D23 , respectively, and the input terminal of the T flip-flop 16
The input terminals of a NAND gate 44 are connected to the non-inverting output terminal Q ₃ and the digital input terminal D ₂₄ , respectively, and the input terminals of an AND gate 45 are connected to the output terminals of the NAND gates 41 to 44, respectively. There is.

Further, a NAND gate 46 and a NOR gate 47 are connected to the inverting output terminal ₄ and the digital input terminal _D25 of the T flip-flop 17, respectively.
The input terminal of an OR gate 48 is connected to the output terminal of the NOR gate 47 and the output terminal of the AND gate 45, respectively.
The input terminals of NAND gates 49 are connected to the output terminals of the gates 48, respectively. .

Also, the output terminal of the T flip-flop 19
The _clock terminals _C7 and _C8 of the D flip-flop 50 and the D flip-flop 51 are connected to Q6, and the input terminal of the NAND gate 52 is connected to the output terminals _Q7 and _Q8 of the D flip-flop 50 and 51, respectively. The output terminal of the NAND gate 52 is the delay terminal D ₇ of the D flip-flop 50.
The output terminal Q ₇ of the D flip-flop 50 is connected to the delay terminal D ₈ of the D flip-flop 51 and the AND gate 53
is connected to the first input terminal of the same inverting output terminal.
₇ is connected to the first input terminal of the AND gate 54. The output terminal of the AND gate 34 is connected to the second input terminal of the AND gates 53 and 54, and the third input terminal of the AND gate 53 is connected to the inverting output terminal of the T flip-flop 17.
₄ , and the third input terminal of the AND gate 54 is connected to the output terminal of the NAND gate 49. Furthermore, the AND gates 53 and 54
The input terminals of the OR gates 55 are connected to the output terminals of the OR gates 55 and 55, respectively.
The output terminals of the NAND gate 33 each have an OR
The input terminal of the gate 56 is connected, and the output terminal of the OR gate 56 is connected to the signal output terminal OUT.

Now, in FIG. 2, the AND gate 22 is T
The first circuit that generates an output when the output of the 6-bit down counter constituted by flip-flops 14 to 19 is [X0110X] (however, X is undefined).
It constitutes a decoding gate for AND
Gate 23 constitutes a second decoding gate that generates an output when the output of the down counter is [X010XX], and AND gate 24 constitutes a second decoding gate that generates an output when the output of the down counter is [X00XXX].
It constitutes a third decoding gate that generates an output when .

Further, both the AND gate 20 and the AND gate 21 constitute auxiliary gates for the decoding gates 22 to 24.

Furthermore, the AND gate 38 constitutes a fourth decoding gate that generates an output when the output of the down counter is [XXX011] and the level of the clock pulse is "0".
9 constitutes a fifth decoding gate that generates an output when the output of the down counter is [XXX010], and an AND gate 40 generates an output when the output of the down counter is [XXX00X]. It constitutes the sixth decoding gate.

Furthermore, both AND gates 35 and 36 constitute auxiliary gates for the decoding gates 38 to 40.

The first decoding gate 22 generates an output twice when the down counter output is from [101101] to [101100] and once from [001101] to [001100]. The output period is equal to twice the period of the clock pulse, and the second decoding gate 23 receives the output of the down counter from [1010111] to [101000], and
The output from [001011] to [001000] is generated twice, and one output period is equal to four times the period of the clock pulse, and the third decoding gate 24 outputs the output from [001000]. between [100111] and [100000], and [000111]
to [000000], one output period is equal to eight times the period of the clock pulse, and the fourth decoding gate 3
8 is from when the down counter output is [111011] and the clock pulse level is “0” [000011]
8 until the clock pulse level is “0”.
The fifth decoding gate 39 generates an output over a number of times, and one output period is equal to one half of the period of the clock pulse, and the fifth decoding gate 39 outputs an output when the output of the down counter is from [111010] to [000010]. The output period is equal to the period of the clock pulse, and the sixth decoding gate 40 generates the output eight times from when the down counter output is [111001] to [000001]. The output period is equal to twice the period of the clock pulse.

That is, the second decoding gate
The third decoding gate is bit weighted with respect to its output generation period with respect to the second decoding gate, and similarly, the third decoding gate is bit weighted with respect to its output generation period with respect to said second decoding gate. ing. On the other hand, the fifth
The decoding gates are bit-weighted with respect to the fourth decoding gate, and the sixth decoding gate with respect to the fifth decoding gate, respectively, with respect to their output generation periods.

Also, NAND gates 25, 26, 27, 28,
41, 42, 43, and 44 constitute an AND gate that generates an output when the level of both input terminals becomes "1", and AND gates 29 and 45 each constitute an AND gate. It constitutes a negative logic OR gate that generates an output when any of its input terminals becomes "0".

On the other hand, the NAND gate 30, the NOR gate 31, the OR gate 32, and the NAND gate 33 are connected to a first selector that determines the effective operating region of the AND gate 29 according to the value of the MSB ( _D15 ) of the first input digital code. configuring the gate, NAND gate 46,
NOR gate 47, OR gate 48, and NAND gate 49 are the MSB of the second input digital code.
A second selection gate is configured to determine the effective operating region of the AND gate 45 according to the value of (D ₂₅ ).

When the level of the MSB (maximum bit) of the first input digital code is "1", the output of the NOR gate 31 is fixed to "0", and the MSB (Q ₆ ) of the 6-bit down counter is fixed. When the level is "0", the output of the NAND gate 30 becomes "0", and the output level of the NAND gate 33 becomes "1".

When the level of the MSB of the 6-bit down counter is "1", the output of the NAND gate 30 is uniquely "1", so the output of the AND gate 39 is inverted to the output terminal of the NAND gate 33. What you do will appear.

When the level of the MSB of the first input digital code is "0", the output of the NAND gate 30 is uniquely fixed to "1", and the output terminal of the NAND gate 33 receives the inverted output of the OR gate 32. What you do will appear.

Further, when the level of the MSB of the second input digital code is "1", the NOR gate 47
The output of the NAND gate 49 is uniquely fixed at "0", and when the level of _Q4 of the 6-bit down counter is "0", the output of the NAND gate 46 becomes "0" and the output level of the NAND gate 49 becomes "0". It becomes 1”.

When the level of _Q4 of the 6-bit down counter is "1", the output of the NAND gate 46 is uniquely "1", so the output terminal of the NAND gate 49 has an inverted output from the AND gate 45. What you do will appear.

When the level of the MSB of the second input digital code is "0", the output of the NAND gate 46 is uniquely fixed to "1", and the output terminal of the NAND gate 49 is supplied with the inverted output of the OR gate 48. What you do will appear.

By the way, in FIG. 2, the D flip-flops 50, 51 and the NAND gate 52 constitute a ternary ring counter, and when the level of the output terminal _Q6 of the T flip-flop 19 changes as shown in _Q6 in FIG. Each output level is shown in Figure 3.
Q ₇ , Q ₈ , and change as shown in 52'.

This ternary ring counter and AND gate 3
4, 53, 54, and OR gates 55 and 56 constitute switching synthesis means, and when the MSB and _Q5 of the 6-bit down counter are both "1", the level of the inverting output terminal ₇ of the D flip-flop 50 is "1". The output signal of the NAND gate 49 is outputted to the signal output terminal OUT via the OR gates 55 and 56 only when the output signal is "1", and when both the MSB and _Q5 of the 6-bit down counter are "1", When the level of the output terminal _Q7 of the D flip-flop 50 is "1", the output signal of the NAND gate 49 is output to the inverted output terminal of the T flip-flop 17.
The device is configured to switch to a dummy signal obtained from ₄ and output it to the signal output terminal OUT, and to inhibit both signals when the output of the 6-bit down counter is other than [11XXXX].

In the end, the first input digital code [D ₁₅ ,
D ₁₄ , D ₁₃ , D ₁₂ , D ₁₁ ] and the second input digital code [D ₂₅ , D ₂₄ , D ₂₃ , D ₂₂ , D ₂₁ ] are varied, the active level period of the output signal is Fourth
The active level period per reference period changes as shown in the figure, and the active level period per reference period changes in response to the change in the numerical value of the first or second input digital code (the fourth
In the figure, the hatched section is the active level period. ).

In Fig. 4, CL is the signal waveform of the clock pulse, Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆
are flip-flops 14, 15, 16, 17, and 1, which constitute a 6-bit down counter, respectively.
8 and 19, the hatched waveform is the output signal waveform appearing at the output terminal OUT, and A-1, A-2, A-3, A-4,
A-5, A-6, and A-7 show the output signal waveforms when the first input digital code is fixed at [100000] and the value of the second input digital code is changed. B-1,
B-2, B-3, B-4, B-5, B-6, B-
7 shows the output signal waveform when the second input digital code is fixed at [100000] and the numerical value of the first input digital code is changed. _Q7 is the output terminal of the D flip-flop 50 that constitutes the ternary ring counter.
This shows the change in the output level of _Q7 .

As is clear from FIG. 4, while the conventional device shown in FIG. 1 performs digital-to-analog conversion by so-called PWM operation, the embodiment of the present invention shown in FIG. The equipment related to BPM
(bit pattern modulation) operation performs digital-to-analog conversion.

That is, in FIG. 2, AND gate 29 and AND gate 45 respectively input first input digital codes [D ₁₄ , D ₁₃ , D ₁₂ , D ₁₁ ] and second input digital codes [D ₂₄ , D ₂₃ , _D22 ,
A bit pattern waveform is generated according to the change in _D21 ].

Therefore, the reference period of the output signal waveforms of the NAND gate 33 and the NAND gate 49, that is, 6
The active level period per count period of the bit down counter changes in accordance with the numerical values of the first and second input digital codes.

Also, the level of the output terminal _Q7 of the D flip-flop 50 constituting the ternary ring counter is “0”.
When , the LSB of the first input digital code
The active level period per reference period of the output signal waveform changes by twice the clock pulse period in response to a change in the (minimum bit), but the output signal waveform changes in response to a change in the LSB of the second input digital code. Since the active level period per reference period changes by only one half of the clock pulse period, and the first and second input digital codes have the same number of bits, the first input digital code is The second input digital code is weighted four times with respect to the active level period per reference period of the output signal waveform.

Furthermore, since the output signal of the NAND gate 49 is output to the signal output terminal OUT only while the level of the output terminal _Q7 of the D flip-flop 50 is "0", the number of changes in the MSB of the 6-bit down counter is The output of the NAND gate 49 is valid only once every three times, and at other times, the same dummy signal as when the second input digital code is [10000] is output.

Therefore, considering one period of the ternary ring counter, the first input digital code is the active level period per reference period of the output signal waveform appearing at the signal output terminal OUT with respect to the second input inverted output terminal. This means that it is weighted 12 times more.

This weighting ratio is determined only by the circuit configuration, and it is possible to make the number of bits of the first input digital code and the number of bits of the second input digital code different, or to change the LSB of the first or second input digital code. Alternatively, the final weighting can be changed by changing the weighting ratio per count period of the MSB down counter or by changing the number of stages of the ring counter (not necessarily limited to ring counters). The ratio can be selected.

Furthermore, the idea of the present invention can be applied not only to the digital-to-analog conversion device using BPM operation shown in FIG. 2, but also to the digital-to-analog conversion device using PWM operation as shown in the conventional device shown in FIG. Needless to say, it is also possible.

As an example, FIG. 5 shows an embodiment in which the present invention is applied to a digital-to-analog converter using PWM operation. In the figure, blocks having the same functions as the blocks explained in FIG. 1 are given the same reference numerals. In the device shown in FIG. 5, a T flip-flop 57, an OR gate 58, AND gates 59, 60, 61, 63, and an OR gate 64 function as the ternary ring counter in FIG.
Gates 34, 53, 54, OR gates 55, 56
In the device shown in FIG. 2, the dummy signal is generated by a 6-bit down counter, whereas in the device shown in FIG.
Based on the wired logic of the input terminals of the OR gate 58 and AND gates 59 to 62, the converter 3
A dummy signal is generated by the RS flip-flop 6 and the RS flip-flop 6.

Of course, it is also possible to obtain a dummy signal from the counter 1 in the same way as in the device shown in FIG.

In the device shown in FIG. 5, the first input digital code is equal to the reference period (2 count periods of the MSB of counter 1) of the output signal waveform appearing at the signal output terminal OUT with respect to the second input digital code. The active level period is weighted 8 times.

As is clear from the embodiments of FIGS. 2 and 5, the digital-to-analog converter of the present invention includes a counter for counting clock pulses and a first
a first signal generating means for generating a first signal whose active level period per counting cycle of the counter changes in response to changes in input digital data; a second signal generating means for generating a second signal whose active level period changes per count period; and an MSB of the counter.
When the change in is repeated a specific number of times, the first signal and the second signal are combined and output to the same output terminal for one count period of the MSB of the counter, and at other times, the first signal and the second signal are combined and output to the same output terminal. 1 and a dummy signal whose active level period is fixed regardless of changes in the second input digital data, and outputs the synthesized signal to the output terminal. In the illustrated embodiment, a ternary ring counter counts the number of changes in the MSB of a 6-bit down counter that counts clock pulses, and a dummy signal and a second signal are switched and outputted depending on the output state of the ternary ring counter. A switching circuit (consisting of AND gates 53, 54 and OR gate 55) constitutes a switching synthesis means.

Therefore, compared to the conventional device shown in Fig. 1, the composition ratio of the first input digital data and the second input digital data to the output signal is determined by the circuit configuration, and is subject to changes in the environment and components used. It is not affected by variations in characteristics, and when converting devices to monolithic ICs, it is possible to reduce the number of external components and the number of external connection terminals.

As is clear from the above description, the digital-to-analog converter of the present invention synthesizes a first signal corresponding to first input digital data and a second signal corresponding to second input digital data. In this case, since the configuration is such that the output obtained by combining the first signal and the second signal and the output obtained by combining the first signal and the dummy signal are alternately applied to the output terminal, This provides an excellent effect in that not only the first signal and the second signal can be synthesized with high precision, but also the synthesis ratio can be selected over a wide range.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional digital-to-analog converter, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, and FIGS. 3 and 4 are signal waveform diagrams of various parts in the circuit of FIG. 2. , FIG. 5 is a circuit diagram of another embodiment of the present invention. 1... Frequency division counter, 2... First digital comparator, 3... Second digital comparator, 5... First RS flip-flop, 6...
...Second RS flip-flop, 14-19,5
7...T flip-flop, 20~24, 34~
36, 38-40, 45, 53, 54, 59-6
3...AND gate, 25-28, 30, 33,
41-44, 46, 49, 52...NAND gate, 4,31,47...NOR gate, 32,4
8, 55, 56, 58, 64...OR gate, 5
0, 51...D flip-flop, 71...down counter.

Claims (1)

[Claims] 1. A counter that counts clock pulses;
a first signal generating means for generating a first signal whose active level period per count period of the counter changes in response to changes in first input digital data; a second signal generating means for generating a second signal whose active level period per counting period of the counter changes; During a count period, the first signal and the second signal are combined and output to the same output terminal, and otherwise the first signal and the second input digital data change. 1. A digital-to-analog converter comprising switching and synthesizing means for synthesizing dummy signals having fixed active level periods irrespective of each other and outputting the synthesized signals to the output terminal. 2. In the description of claim 1, the switching/synthesizing means includes another counter that counts the number of changes in the MSB of the counter, and converts the dummy signal and the second signal according to the output state of the counter. 1. A digital-to-analog conversion device comprising a switching circuit for switching and outputting.