JPH07135469A - D/a converter - Google Patents

Abstract

PURPOSE:To obtain a D/A converter of the PWM system with excellent response in which a cut-off frequency of an LPF is set higher. CONSTITUTION:Bits of an output of a counter making count operation by a received clock CK are reversed as shown in figure and the resulting data are fed to one input terminal of a digital comparator 102. The digital comparator 102 compares data A to be D/A-converted and fed to other input terminal and data B received by the one input terminal and gives an output produced in the case of A>B to a low pass filter(LPF) 103, and a D/A conversion output is obtained from an output terminal of the LPF 103. Since outputs of the counter 101 are bit-reversed, the output pulse of the digital processing 102 is distributed over the entire counter period (PWM period), the object is attained.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a so-called Pulse
The present invention relates to a width modulation (hereinafter referred to as PWM) type D / A converter.

[0002]

2. Description of the Related Art Conventionally, there is a PWM type D / A converter having a structure shown in FIG.

In FIG. 7, reference numeral 701 is a counter that performs a counting operation with a clock CK, 702 is a digital comparator that compares the count value B with the data A that is the object of D / A conversion, and 703 is A of the comparator 702>
An LPF (low-pass filter) that extracts low-frequency components from the B output.

FIG. 8 shows a "9" using a 4-bit counter.
The A> B output of the digital comparator 702 when D / A conversion of (hex) ”is shown.

As is apparent from FIG. 8, the A> B output of the digital comparator 702 has a cycle of 2 ⁴ (= 16) CK.
In minutes, it outputs a pulse with a width of 9 · CK. Therefore, if this is passed through the LPF 703, a value of 9/16 is obtained.

[0006]

However, as can be seen from FIG. 8, in the conventional PWM D / A converter, the "H" pulse and the "L" pulse are PW at the comparator output.
In the M cycle, the left and right clusters, so PW
The carrier component corresponding to the M period is large, and the LPF 70
If the cutoff frequency of 3 is not lowered considerably, carrier suppression will be insufficient and carrier components will appear in the D / A conversion output.

If the cutoff frequency of the LPF 703 is set too low in order to avoid this, when the data value to be D / A converted is changed this time, it takes a long time to stabilize it, which is above a certain level. This becomes a big problem in a device that requires the responsiveness.

Further, these problems are caused by the counter 701.
Although the problem can be solved by increasing the frequency of the clock CK given to the circuit, in this case, there is a problem that the power consumed by the circuit increases.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a D / A converter which can set the cutoff frequency of the LPF to a high value and has a good response. Is.

[0010]

In order to achieve the above object, the present invention provides a conversion means for converting the output of a counter. More specifically, the D / A converter is composed of the following (1) to
It is configured as in (5).

(1) A counter that performs a counting operation with a clock, a conversion unit that converts the output of this counter, a digital comparator that compares the output of this conversion unit with the data to be D / A converted, and this digital A D / A converter having a low-pass filter for extracting only the low-pass component from the output of the comparator, and an output terminal provided on the output side of the low-pass filter.

(2) The conversion means is the MS of the output of the counter.
The D / A converter according to (1) above, which reverses the order of bits from B to LSB.

(3) The D / A converter according to (1), wherein the conversion means sequentially cyclically shifts each bit of the output of the counter by a constant bit.

(4) The D / A converter according to (1), wherein the converting means converts the output of the counter into a table.

(5) The D / A converter according to (1), wherein the conversion means is of a type in which one conversion means is selected from a plurality of different conversion means.

[0016]

With the configurations described in (1) to (5) above, the pulse position of the output of the digital comparator is determined by the counter cycle (P
WM period).

[0017]

EXAMPLES The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 shows a first embodiment "P".
The configuration of a WM type D / A converter "is shown.

In FIG. 1, reference numeral 101 is a counter which performs a count operation by a clock CK, and 102 is a value B obtained by bit-reversing the count value (reversing the order of MSB → LSB) and subject to D / A conversion. A digital comparator 103 for comparing the data A is an LPF.

The effect of such bit reversal is that the generation of "H" and "L" pulses after the comparator 102 is randomly dispersed in the PWM cycle.

FIG. 2 shows, as an example, a waveform of the A> B output of the digital comparator 102 when "9 (hex)" is D / A converted using a 4-bit counter. As shown in the figure, 9 · CK pulse is output.

As compared with the conventional example of FIG. 8, it is apparent that the pulse numbers are the same but the pulse positions are dispersed.

Thus, according to this embodiment, the LP
The cut-off frequency of F103 can be set high, and the responsiveness as a D / A converter can be improved.

(Embodiment 2) FIG. 3 shows a second embodiment "PW".
It is a figure which shows the structure of the M system D / A converter.

In FIG. 3, reference numeral 301 denotes a counter which performs a counting operation by a clock CK, and 302 cyclically shifts the count value by K bits (for example, Q0).
~ In case of 4 bits of Q3, Q0 → Q2, Q1 → Q3, Q
2 → Q0, Q3 → Q1 rearranged value B),
A digital comparator 303 for comparing the data A to be D / A converted is an LPF.

The effect of this bit shift is also "H" and "L" after the comparator as in the case of bit reverse.
The pulse generation will be randomly dispersed in the PWM cycle.

As an example, FIG. 4 shows a waveform of the A> B output of the digital comparator 302 when "9 (hex)" is D / A converted by using a 4-bit counter. Also in this case, when compared with the conventional example of FIG. 8, it is apparent that the pulse numbers are the same but the pulse positions are dispersed.

(Embodiment 3) FIG. 5 is a diagram showing the structure of the third embodiment.

In FIG. 5, reference numeral 501 is a counter which performs a counting operation by a clock CK, 502 is a conversion table which converts the count value of the counter 501 into another value,
Reference numeral 503 is a digital comparator for comparing the value B table-converted by the conversion table 502 with the value A to be D / A converted, and 504 is an LPF.

In this case, unlike the above-mentioned bit reverse or bit shift, the degree of freedom of conversion is large,
For example, it is possible to create an optimum conversion table for the characteristics of the LPF 504.

(Modifications of Embodiments 1, 2 and 3) Although the embodiment using the bit reverse, the bit shift and the conversion table has been described above, conversion may be performed by a combination of these. For example, part of the count value of nbit is bit reverse conversion, and part is bit shift conversion,
And a part may be converted into a table. Moreover, you may change these orders. All of these may be selected and used according to the scale of the circuit and the effect obtained.

(Embodiment 4) FIG. 6 is a diagram showing the structure of Embodiment 4.

In FIG. 6, reference numeral 601 denotes a counter which performs a counting operation by a clock CK, and 602 has K number of the above-mentioned plurality of data converting means, and data converting means 1 to K which can select the effective converting means from the outside. Is. Reference numeral 603 is the conversion data values B and D of the selected conversion means.
A comparator 604 that compares the data value A that is the target of the / A conversion, and 604 is an LPF.

By doing so, it is possible to externally select the conversion means suitable for the characteristics of the LPF 604.

In each of the above embodiments, the A> B output of the comparator is used. However, the present invention is not limited to this, and the same can be carried out by using the A <B output. .

[0036]

As described above, according to the present invention, P
In the WM type D / A converter, it becomes possible to disperse the “H” and “L” pulses of the digital comparator output so as not to be biased in the PWM cycle.

Therefore, the cutoff frequency of the LPF can be set high, and the responsiveness of the D / A converter can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment.

FIG. 2 is a diagram showing a conversion example according to the first embodiment.

FIG. 3 is a diagram showing a configuration of a second embodiment.

FIG. 4 is a diagram showing a conversion example according to the second embodiment.

FIG. 5 is a diagram showing a configuration of a third embodiment.

FIG. 6 is a diagram showing a configuration of a fourth embodiment.

FIG. 7 is a diagram showing a configuration of a conventional example.

FIG. 8 is a diagram showing a conversion example according to a conventional example.

[Explanation of symbols]

 101 Counter 102 Digital Comparator 103 LPF

Claims (5)

[Claims] 1. A counter that performs a counting operation with a clock, a conversion unit that converts the output of this counter, a digital comparator that compares the output of this conversion unit with the data to be D / A converted, and this digital comparator. A D / A converter comprising a low-pass filter for extracting only the low-pass component from the output of the above-mentioned, and an output end provided on the output side of this low-pass filter. 2. The D / A converter according to claim 1, wherein the conversion means reverses the order of bits from the MSB to the LSB of the output of the counter. 3. The D / A converter according to claim 1, wherein the conversion means sequentially cyclically shifts each bit of the output of the counter by a constant bit. 4. The D according to claim 1, wherein the conversion means converts the output of the counter into a table.
/ A converter. 5. The D / A converter according to claim 1, wherein the conversion means is of a type in which one conversion means is selected from a plurality of conversion means different from each other.