JPH01311872A - Pwm signal arithmetic and logic device - Google Patents

Abstract

PURPOSE:To improve the resolving power of PWM signals and to reduce the cost by operating a counter only as an up-(or down-) counter. CONSTITUTION:A PWM signal arithmetic and logic device is composed of a phase voltage command generation circuit 1, digital comparators 2 and 21, a serrate wave generation circuit 3A, an arithmetic circuit 4 and a PWM signal synthesizing circuit 5. The clock generated from a clock generation circuit 31 of the serrate wave generation circuit 3A is counted using an up-counter (or a down-counter) 32 and a count data S0 is outputted. A monitor data S1 is inputted into the arithmetic circuit 4 for designated operation and a PWM signal M1 for one phase component is obtained by forwarding the obtained data S2 and the count data S0 through a digital comparator 21 and the PWM signal synthesizing circuit 5. Since the counter 32 is operated by up-(down-) count only, it can be operated at the maximum clock frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PWM signal calculation device in a pulse width modulation (hereinafter referred to as PWM) type semiconductor power conversion device.

[Prior Art] Conventionally, as a PWM signal calculation device for a PWM type variable voltage variable frequency (VVVF) inverter, a PWM signal is generally obtained by comparing a phase voltage command signal (modulated wave) and a triangular wave signal (carrier wave). things are widely used. For example, the structure shown in FIG. 8 is known as a device that realizes this using a digital circuit. However, this is only for one of the three phases. In the figure, 1 is a phase voltage command generation circuit, 2 is a digital comparator, and 3 is a clock '1EDO path 31.

This is a carrier signal generation circuit consisting of an up/down counter 32 and an up/down switching signal generation circuit 33.

In the figure, the clock C generated from the clock generation circuit 31
The LKi up/down counter 32 counts. However, the output 511iC of the up/down switching signal generation circuit 33 controls whether to count up or down. Assuming that the up-down switching signal generation circuit 33 outputs an up-count command at a certain point in time, it outputs an up-count command until the maximum value emax of the up-down/counter 32 is reached, and when it reaches Cff1aX, it outputs a down-count command. , outputs a down-count command until S12 becomes 0, and then switches to an up-count command when S12 becomes 0, and repeats this operation. In this way, the output data 812 of the carrier signal generation circuit 3 becomes data showing a triangular wave as shown in FIG. 9(a). Further, the phase voltage command generation circuit 1 outputs data S1 obtained by adding an offset amount Cmax/2 to data V'' proportional to the phase voltage,
The digital comparator 2 determines the size of the
From the result, a PWM signal Mo for one phase is formed as shown in FIG. 9(b).

In such a PWM signal calculation device, the resolution of the PWM signal is expressed by the following equation.

FL-2fC/'CLK-...(
1) fo: Carrier frequency fCl, K Input clock frequency of the near-down counter 32. Therefore, it can be seen that in order to reduce the resolution R while the carrier frequency fC is constant, "CLKt" must be increased.

[Problem to be solved by the invention]

However, in such a PWM signal calculation device, as shown in FIGS. There is a delay time t1 from when 812 changes. In particular, in the case of the configuration shown in FIG. 8, the delay time t2 caused by the up-down switching signal generation circuit 33 from when 812 changes to when 811 changes, and the delay time t2 of the up-down switching signal before the next clock of the up-down counter 320 rises. The input clock frequency if of the up/down counter 32 is determined by the setup time t3. LK is limited as shown in equation (2) below.

fcLK<1/(t1+t2+t3) ------
-(21 In other words, the resolution of the PWM signal is 2fc(t1
+12+13) is not possible. Therefore, an object of the present invention is to provide a PWM signal calculation device that can improve the resolution of a PWM signal without changing the carrier frequency.

[Means for solving problems]

In order to generate pulse width change II signals corresponding to each of the three phases from n-bit phase voltage command data and sawtooth wave data varying from 0 to 2n+1, the sawtooth wave data and the phase voltage command data are combined. a first comparing means for determining the magnitude; a subtracting means for subtracting the phase voltage command data from the maximum value of the sawtooth wave data; and a second comparing means for determining the magnitude between the output from the subtracting means and the sawtooth wave data. Comparison means of 1st. Second
A PW consisting of a synthesis means for synthesizing the outputs from the comparison means.
An M signal calculation circuit is provided.

Furthermore, if the above-mentioned PWJ No. 8 arithmetic circuit corresponds to the phase voltage command v'', another PWJ having the same components and generating a PWM signal corresponding to the phase voltage command -■
An M signal calculation circuit is provided.

Furthermore, each of the three phases is determined from the n-bit first phase voltage command data, the second phase voltage command data which has a different polarity and the same magnitude, and the sawtooth wave data which varies from 0 to 2 -1. a first comparison means for determining the magnitude of the first phase voltage command data and the lower n-bit data excluding the most significant bit of the sawtooth wave data in order to generate a two-phase pulse width modulation signal for each; a second comparing means for determining the magnitude of the second phase voltage command data and the lower n-bit data excluding the most significant bit of the sawtooth wave data; Second
A synthesizing means is provided for synthesizing a two-phase PWM signal from each output of the comparing means and the most significant bit of the sawtooth wave data.

[Effect]

By operating the counter only as an up (or down) counter, the operation delay of the logic circuit that conventionally generates the up/down switching signal and the setup time for the up/down switching signal up to the next four counts can be eliminated.
The counter 'frR is set so that it can be operated at a high clock frequency to improve the resolution of the PWM signal. At that time, using the output of the color/re (sawtooth wave data),
Conventionally, in order to obtain the same PWM signal obtained by comparing the triangular wave data and the phase voltage command data, the phase voltage command data and the output of the counter are compared by a first digital comparator, and the output of the counter is The phase voltage command data is subtracted from the maximum value, the subtraction result and the output of the counter are compared by a second digital comparator, and the first. By combining the output signals of the second digital comparator with a logic circuit, the same PWM signal as the conventional one is obtained.

In addition, PWM corresponding to phase voltage commands v'' and 1
By providing a signal calculation circuit, two
Simplification and cost reduction are achieved by devising the circuitry for a device in which a PWM signal calculation circuit ft having the same configuration is provided so as to be able to generate PWM signals of each phase.

〔Example〕

FIG. 1 shows an embodiment of the invention. FIG. 2 is a timing chart of various signals in FIG. 1. This will be explained below with reference to FIGS. 1 and 2. However, this is only for one of the three phases.

The clock generated from the clock generation circuit 31 is counted by an up counter (or down counter) 32 and outputs count data So. S.

The result is data showing a sawtooth wave as seen in Figure 2 (a). In addition, from the phase voltage command generation circuit 1, an offset C is added to n (natural number) bit data V proportional to the phase voltage.
Data s1 with max/2 added is output, and So and 81
is input to the digital comparator 2, and the result is shown in Figure 2 (b).
A magnitude discrimination signal S5 as shown in FIG. The arithmetic circuit 4 has s
Input the data of l, perform the calculation as shown in the following formula, and
get.

Note that when the counter 32' is changed from t-0 to 2-1, (-max becomes 2).

s2n+2cmax-81... (3) This S
2 and count data So are input to the digital/l/comparator 21, and a size discrimination signal S6 shown in FIG.
get. The signals S5 and So are sent to a PWM signal synthesis circuit 5.
and obtain the PWM signal sound for one phase as shown in Figure 12 (d). In addition, Fig. 9 corresponds to (.
) equation, the timing of the intersection B between So and 82 is the same, so the PWM signal MO in FIG. 9(b) and P in FIG.
The WM signal signal tone is equal to 1.

As described above, according to the present embodiment, by providing the second digital f converter 21, the arithmetic circuit 4, and the PWM signal synthesis circuit 5, the counter 32 is operated by counting up (or down). Therefore, there is no restriction as in equation (2). Therefore, since the counter 32fj can be operated at the maximum clock frequency, it has the effect of improving the resolution of the PWM signal compared to the conventional counter.

By the way, if we add a PWM signal processing circuit corresponding to the phase voltage command -V, which has a different polarity and the same magnitude as the phase voltage command V, to the unity shown in Fig. 2
Phase PWM signals can be generated. FIG. 3 is a block diagram of this embodiment, and FIG. 4 is a time chart for fully explaining its operation.

In this system, a similar FIP 16A is provided for the PWM signal boosting circuit 6, and the PWM signal sound 12i corresponding to each of the phase voltage commands ■ and -■ is generated, and its operation is basically the same. Since it is similar to FIG. 1, details will be omitted.

FIG. 5 is a block diagram of a slightly different embodiment 'fc7' of the present invention, and FIG. 6 is a time chart for explaining the entire operation of FIG.

First, in the PWM signal calculation device shown in FIG. 3, the output data S2 of the calculation circuit 4 and the output data S4 of the calculation circuit 4A are configured to calculate the following equation, so 82n+2 Cmax 81 = −=
(4) S4=2Cmax-83-.'' (5) Now, if the first input data S1 and the second input data S3 are expressed by the following formula (where V' is the phase voltage command data). ), 81- V +Cmax/ 2 -- (
6183--V +Cmax/ 2--
・(71 (4) and (6) formulas and (5) and (methods), S
2 and S3 and 81 and S4 have the following relationships.

5z-8s+('rnax・”-(
8) s4': sl+emaX +++
++ (9) Moreover, when Sl and S3 are n-bit data, the binary counter 32 is set from 0 to 2 -1.
Cmax becomes 2.

Therefore, 82 is 1 at the n+1st bit of the data in S3.
Since S4 can also be calculated by setting 1 to the n→-1st bit of the data in Sl, the calculation circuits 4 and 4A- can be omitted. Also, since digital comparators can be connected in cascade, n
Dividing the +1-bit digital comparator into lower n bits and upper 1 bit, digital comparator 2.
! The magnitude discrimination signals of the lower n bits of -21A are each equal to (7
Moreover, since the magnitude discrimination signals of the lower n hits of the digital comparators 21 and 2A are also equal, two of the four digital comparators can be omitted.

FIG. 5 is a further simplified version of FIG. 3 based on this viewpoint. That is, the clock in+1 bit generated from the clock generation circuit 31 is counted by the binary up counter (or down counter) 32, and the most significant bit data MSB and the lower data 84'c as shown in FIG. 6(b) are output ( For example, if counter 3 is 12 bits, S4 is 11 bits data). S4 becomes sawtooth wave data as shown in FIG. 6(a). Also 9
5. As the first input data, 1. Data S1, which is obtained by adding an offset of 2 to the phase voltage command ■, is input manually, and S4 and S
A digital comparator 22 is manually operated to obtain a size discrimination signal S9. In addition, as the second manual data, the polarity of the phase voltage command v4 is completely reversed (~da1) by an offset of 2
This data S3 and the count data S4 are input to the digital converter 23, and a magnitude determination signal 810 is obtained. Said signal MSB, 89
and 810 are input to the PWM signal synthesis circuit 51, and the sixth
Two-phase PW as shown in figures (E) and (F), respectively.
M signal FIG. 7 shows the internal configuration of the PWM signal synthesis circuit 51. This is composed of four 1-bit digital comparators 511A to 511D and PWM signal synthesis circuits 51A and 51B. The 1-bit digital comparators 511A to 511D serve as signal terminals for determining the magnitude of lower bits.

A device that outputs a signal for determining the size of A and B data from 8 data terminals is used. Further, since each B terminal is fixed to 0" and 1", it can be configured with a simple logic circuit.

〔Effect of the invention〕

According to this invention, since the counter is made to operate only by up-counting (or down-counting), there is no delay in the operation of the logic circuit that conventionally generates the up-down switching signal from the output data of the up-down counter, and the next clock The clock frequency of the up/down counter is no longer limited by the setup time of the up/down switching signal before it rises, and the resolution of the PWM signal can be improved compared to the conventional one.

Furthermore, as shown in Fig. 3, by providing PWM signal generation circuits corresponding to the phase voltage commands v'' and 1'',
It is possible to generate two-phase PWM signals for each of the three phases, and by doing so as shown in FIG. 1, it is possible to simplify the configuration and reduce costs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining its operation, Fig. 3 is a block diagram showing another embodiment of the invention, and Fig. 4 is a block diagram showing an embodiment of the present invention. A time chart for explaining the operation, FIG. 5 is a configuration diagram showing still another embodiment of the invention, FIG. 6 is a time chart for explaining the operation, and FIG. 7 is shown in FIG. P.W.
A block diagram showing a specific example of the M signal synthesis circuit, FIG.
A configuration diagram showing a conventional example of a WM arithmetic device, and FIG. 9 is a time chart for explaining its operation. Description of symbols 1... Phase voltage command generation circuit, 2, 2A, 21° 21A, 22, 23, 511A to 511D...
Digital comparator, 3...Carrier signal generation circuit, 3 people...Sawtooth wave generation circuit, 4.4
A... Arithmetic circuit, 5, 5 people, 51.51A, 5
1B...PWM signal synthesis circuit, 6,6A...
... PWM signal calculation circuit, 31 ... Clock generation circuit, 32 ... Counter, 33 ...
・Up/down switching signal generation circuit. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 1 1Δ Figure 2 ゛ (Gravity +14 + L-111111)
Figure 3. Figure 4 (l''''''M・-1-1-1 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Aμ3

Claims (1)

[Claims] 1) n-bit phase voltage command data and 2^n^+^ from 0
A PWM signal calculation device that calculates a pulse width modulation (PWM) signal corresponding to each of three phases from sawtooth wave data that changes from 1 to 1, wherein the sawtooth wave data and the phase voltage command data are a first comparing means for determining the magnitude; a subtracting means for subtracting the phase voltage command data from the maximum value of the sawtooth wave data; and a second comparing means for determining the magnitude between the output from the subtracting means and the sawtooth wave data. A PWM signal calculation device comprising: comparing means; and combining means for combining outputs from the first and second comparing means. 2) n-bit first phase voltage command data, second phase voltage command data with different polarities and the same magnitude, and sawtooth wave data that changes from 0 to 2^n^+^1-1. A PWM signal calculation device that calculates a two-phase pulse width modulation (PWM) signal for each of three phases from first and second comparing means for respectively subtracting first and second phase voltage command data from the maximum value of the sawtooth wave data; first and second subtracting means for subtracting first and second phase voltage command data, respectively; third and fourth comparison means for respectively determining the magnitude of the output from the subtraction means and the sawtooth wave data; and the outputs from the first and third comparison means and the outputs from the second and fourth comparison means, respectively. A PWM signal calculation device comprising: first and second combining means for combining; 3) n-bit first phase voltage command data, second phase voltage command data with different polarity and the same magnitude, and sawtooth wave data that changes from 0 to 2^n^+^1-1. A PWM signal calculation device that calculates two-phase pulse width modulation (PWM) signals for each of three phases from a first comparing means for determining the magnitude of bit data; and a second comparing means for determining the magnitude of the second phase voltage command data and the lower n-bit data excluding the most significant bit of the sawtooth wave data. A PWM signal calculation device comprising: , synthesis means for synthesizing a two-phase PWM signal from each output of the first and second comparison means and the most significant bit of the sawtooth wave data.