JPH02194724A - System and circuit for modulating pulse width - Google Patents

Abstract

PURPOSE:To reduce a phase delay in a control band by means of a low pass filter in a poststage by generating plural high level sections and low level sections in a pulse width modulation period. CONSTITUTION:The subject circuit is constituted with a five-bit counter 7, three-bit counter 9, an eight-bit register 11, a first comparator 16, a half adder 18 and a second comparator 21. The pulse width modulation period is divided into plural numbers, and a pulse having the pulse width corresponding to modulated data which are given at every pulse width modulation period are divided into plural numbers, whereby divided pulses are respectively arranged in respective division periods. Consequently, plural high level sections and the low level sections can be generated in the pulse width modulation period, and the frequency of the pulse width modulation can accordingly be raised. Then, the cut off frequency of the low pass filter can be raised. Thus, the phase delay in the control band by the low pass filter can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation method and a pulse width modulation circuit used in a digital-to-analog converter in a digital control device that controls a servo motor or the like.

[Conventional technology]

In recent years, the pulse width modulation method has come into widespread use as the number of digital control devices increases.

The conventional pulse width modulation method will be explained below.

When pulse width modulating data, conventionally, the pulse width modulation period is set to the pulse width corresponding to the maximum value of the data, and the size of each data is adjusted every pulse width modulation period (sampling period) from the beginning of the pulse width modulation period. A pulse having a pulse width proportional to is generated.

FIG. 4 shows a block diagram of a pulse width modulation circuit implementing the above-mentioned conventional pulse width modulation method.

In FIG. 4, l is a register that launches data 2 in response to a sampling clock 3 generated every pulse width modulation period. 5 is a counter for counting the count clock 4; A comparator 6 compares the output value of the register l and the count value of the counter 5.

The operation of the conventional pulse width modulation circuit configured as described above will be explained below.

Count clock 4 is set to a clock frequency 2R times that of sampling clock 3 when both counter 5 and register 1 are n-pinto binary (n is a positive integer). Then, the counter 5 uses the sampling clock 3
Set the count value to zero in synchronization with the trigger.

With this setting, the value of register 1 that latches data 2 is held while counter 5 is counting up.

On the other hand, comparator 6 compares the output value of register 1 and the count value of counter 5, and outputs a high level signal if the count value of counter 5 is smaller than the output value of register 1, otherwise outputs a low level signal. do. Therefore, the time of the high level signal of the output of the comparator 6 is:
Data 2 is pulse width modulated.

(Problems to be Solved by the Invention) In the conventional pulse width modulation method described above, there is only one pair of high level and low level in the sampling period, that is, the pulse width modulation period, and the modulation frequency is low. In order to obtain a sufficient smoothing effect when smoothing the signal at a later stage and inputting it into the drive circuit, a low-pass filter with a low cutoff frequency is required.

However, when the cant-off frequency of the low-pass filter is lowered, there is a problem in that the phase delay in the control band, which is a lower frequency band, increases.

An object of the present invention is to provide a pulse width modulation method and a pulse width modulation circuit that can reduce the phase delay in a control band caused by a low-pass filter at a subsequent stage.

[Means to solve the problem]

The pulse width modulation method according to claim (1) divides a pulse width modulation period into a plurality of periods, and within each divided period, a plurality of pulses having a pulse width corresponding to modulated data given for each pulse width modulation period are generated. The pulse width modulation method according to claim (2) is characterized in that the pulse width modulation method according to claim (1) is characterized in that divided pulses each divided into 2+s** bits ( m and n are positive integers), the pulse width modulation period is divided into 211, and 2n divided pulses arranged in each of 2n divided periods are set to a pulse width corresponding to the upper m bit data of the modulated data. At the same time, the pulse width of the number of divided pulses corresponding to the lower n bits of the modulated data among the 2n divided pulses is increased by the width corresponding to the least significant bit of the modulated data.

The pulse width modulation circuit according to claim (3) implements the pulse width modulation method according to claim (2), and latches m+n bits of modulated data in accordance with a sampling clock generated every pulse width modulation period. An m + n bit register, an m bit counter that counts a count clock having a period obtained by dividing the pulse width modulation period by 2II''h, an n bit counter that counts the carry output of this m bit counter, and a lower register of the m + n bit register. Compare the n-bit data with the count value of the n-bit counter and get m+
The first one that generates an output when the lower n-bit data of the n-bit register is greater than the count value of the n-bit counter.
a comparator, a half adder that adds the output of the first comparator to the upper m bit data of the m+n bit register as the least significant bit data of the upper m bit data, and a half adder that adds the output data of the half adder and the m bit data. and a second comparator that compares the count value of the counter and generates an output as a pulse width modulation signal when the output of the half adder is larger than the count value of the m-bit counter.

[For production]

In the pulse width modulation method of claim ILL, a plurality of high level sections and low level periods are created within the pulse width modulation period. As a result, the frequency of pulse width modulation increases, making it possible to increase the cutoff frequency of the low-pass filter. Therefore, the phase delay in the control band caused by the low-pass filter is reduced.

In the pulse width modulation method of claim (2), when viewed from the start point of the pulse width modulation period, each divided pulse has the same pulse width until the end of the period if the lower n bit data is "01". The pulse continues. Also, if the lower n bit data is 11" to 21'-1", l to 2'1-1 pulses of the same pulse width continue, and then the minimum pulse width is smaller than that pulse width. The pulse, which is narrower by (corresponding to the smallest bit of mten n-bit data), continues until the end of the period.

In the pulse width modulation circuit of claim (3), the m+n bit register latches m+n bits of modulated data in response to a sampling clock generated every pulse width modulation period. On the other hand, the m-bit counter changes the pulse width modulation period to 2n
``Count a count clock having a period divided into 7,
The n-bit counter counts the carry output of the m-bit counter.

As a result, the count value of the m-bit counter is equal to lI'1Il for each divided period obtained by dividing the pulse width modulation period into 2n pieces.
The I period increases from '09 to '2--1' every count clock. Also, since the count value of the n-bit counter counts the carry output of the m-bit counter, it increases from "0" to "211-1" for each division period from the beginning of each pulse width modulation period. .

The first comparator compares the lower n bit data of the m+n bit register with the count value of the m bit counter, and the lower n bit data of the m+n bit register is
Generates an output when it is greater than the count value of the bit counter. Then, the half adder adds the output of the first comparator to the upper m-bit data of the m + n-bit register as the least significant bit data of the upper m-bit data. The second comparator compares the output of the half adder and the count value of the m-bit counter, and generates an output as a pulse width modulated signal when the output data of the half adder is greater than the count value of the m-bit counter.

As a result, in the pulse width modulation signal, the pulse width of the pulses distributed in the number of division periods corresponding to the lower n bit data of the m+n bit register from the beginning of each pulse width modulation period is the same as the upper m bit data of the m+n bit register. The pulse width corresponding to the minimum bit of the lower n-bit data is added to the pulse width corresponding to the minimum bit of the lower n-bit data. Further, the pulse width of the pulse arranged in the subsequent divided period becomes the pulse width corresponding to the upper m-bit data.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In this pulse width modulation method, the modulated data is m+n pitches.
- (m, n are positive integers), the pulse width modulation period is divided into 2'' periods, and each divided period has a pulse width corresponding to the modulated data given for each pulse width modulation period. Divided pulses obtained by dividing the pulse into two are each arranged.

In this case, the 2n divided pulses arranged in each of the 2^ divided periods are set to a pulse width corresponding to the upper m-bit data of the modulated data, and the pulse width modulation of the 2- divided pulses is The pulse width of the number of divided pulses corresponding to the lower n-bit data of the modulated data is increased by the width corresponding to the least significant bit of the modulated data from the beginning of the cycle.

As a result, when viewed from the starting point of the pulse width modulation period, each divided pulse continues to have the same pulse width until the end of the period if the lower n bit data is "0". Also, the lower n bit data is “1” to 21
In the case of 1-1'', 1 to 2^-1 pulses of the same pulse width follow, and then the width is smaller than the pulse width by the minimum pulse width (corresponding to the minimum focus of m+n bit data). The narrow pulse continues until the end of the period.

According to the pulse width modulation method of this embodiment, the pulse width modulation period is divided into 2n, and the pulse having the pulse width corresponding to the modulated data given for each pulse width modulation period is divided into 2n, and within each division period. Since the divided pulses are arranged respectively in the pulse width modulation period, 2n high level periods and 2n low level periods are created within the pulse width modulation period. As a result, the frequency of pulse width modulation increases by 2n times, making it possible to increase the cutoff frequency of the low-pass filter. Therefore, the phase delay in the control band caused by the low-pass filter can be reduced.

The configuration and operation of a pulse width modulation circuit that implements this pulse width modulation method will be described below.

FIG. 1 is a block diagram showing the configuration of a pulse width modulation circuit in one embodiment of the present invention. In the following embodiments, m=5 and n-3 will be explained, but the values of m and n may be arbitrary integer values.

In FIG. 1, 7 is a 5-bit counter (m-bit counter), for example, and the counter is cleared at a count clock 8. 9 is a 3-pin counter (n-bit counter), for example, which counts up using the carry output 10 of the 5-bit counter 7 as a count clock. 11 is
Data 12 is latched by the sampling clock 13 in an 8-bit register (m+n bit register).

16 is a first comparator, an 8-bit register 11
The lower three bits of data 14 are compared with the count value 15 of the 3-focus counter 9. A half adder 18 adds the data 17 of the upper five bits of the 8-bit register and the output 23 of the first comparator 16. 21 is a second comparator that compares the output 19 of the half adder 18 and the count value 20 of the 5-bint counter.

22 is a pulse width modulation signal which is the output of the second comparator 21.

FIG. 2 is a time chart of each part of the embodiment of FIG. 1 in the case where the lower three bit data 14 of the 8-bit register 11 is, for example, "O". The assigned symbols correspond to the same symbols in FIG. 1. In other words, in FIG. Figure 2 (bl is part I)
(C1 shows the output 19 of the half adder 18 and the count value 20 of the 5-bit counter, respectively. The output pulse width modulated signal 22 is shown in FIG. 2 (el indicates the sampling clock 13).

FIG. 3 is a time chart of the embodiment of FIG. 1 when the lower three bit data 14 of the 8-bit register 11 is "4", and the symbols assigned to each signal ta+ to (e) in FIG. They respectively correspond to the same reference numerals in FIG. 1 and are the same as in FIG. 2. It should be noted that the broken lines in FIG. 3 indicate the case where the lower three bits of data 14 of the 8-bit register 11 are "0" for reference.

The operation of the pulse width modulation circuit of FIG. 1 configured as described above will be explained below.

First, since the carry output lO of the 5-bint counter is the count clock of the 3-pint counter 9,
The combination of bit counter 7 and 3-bit counter 9 functions the same as an 8-bit counter.

In this case, the count clock 8 is set so that the count value of the 5-pin counter 7 and the 3-bit counter 9 becomes 10" at the same time that the data 12 subjected to pulse width modulation is sampled by the sampling clock 13. Specifically, , the frequency of the count clock 8 is set to 2s times that of the sampling clock 13, and the 8-bit counter counts up from 0'' to 21-1'' every sampling period.

As a result, the count value 20 of the 5-bit counter is equal to each divided period T2 obtained by dividing the pulse width modulation period T1 into 23.
is one cycle, and increases from "0" to "2s-1" every count clock shift. Also, since the count value 15 of the 3-bit counter counts the carry output 10 of the 5-bit counter, the count value 15 of the 3-bit counter counts the carry output 10 of the 5-bit counter.
It will increase to 1".

The lower 3-bit data 14 of the 8-bit register 11 is O''
In the case of
count (direct 15 is greater than or equal to the lower 3 bit data 14 of the 8-bit register 11).

Therefore, the output 23 of the first comparator 16 is always 0 (low level)'' as shown in FIG.

As a result, the upper 5 bit data 17 of the 8-bit register 11 is output as is as the output 19 of the half adder 18.

The relationship between the output I9 of the half adder 18 and the count value 20 of the 5-bit counter 7 is as shown in FIG. A second comparator 21 compares them.

Therefore, the pulse width modulation signal 22 which is the output of the second comparator 21 becomes as shown in FIG. 2 (dl). The data is divided into 8 parts and 5-bit data is put into each divided period T2, and the overall pulse width is the 8-bit data pulse-width modulated.

In this case, the pulse widths of the pulses distributed in the number of divided periods T2 corresponding to the lower n-bit data 14 of the 8-bit register 11 from the beginning of each pulse width modulation period T1 are the same as the upper 5-bit data 17 of the 8-bit register 11. The pulse width corresponding to the minimum bit of the lower three bit data 14 is added to the pulse width corresponding to the minimum bit of the lower three bit data 14. Further, the pulse width of the pulse arranged in the subsequent divided period T2 becomes the pulse width corresponding to the upper five bit data 17.

In the above example, since the lower 3-bit data 14 of the 8-bit register 11 is 0'', the width of the pulses input in each division period T2 is all the same, and the pulse width corresponding to the upper 5-bit data 17 of the 8-bit register 11 is the same. becomes.

Next, the lower three bits of the 8-bit register 11 become “03”.
Consider the case where it is not. If we convert the value of the lower 3 bits to 1O base and set it as "4'," and then number each divided period T2, which is obtained by dividing the pulse width modulation period into 23, as 1.2°3, . . . , 23 from the front, the third As shown in the figure [al], from the first to the fourth period, the lower 3 bit data 14 of the 8-bit register II is larger than the count value 15 of the 3-pin counter 9. Therefore, the output 23 of the first comparator 16 is !3 figure f
Like bl, it is "1 (high level)" from the first to fourth periods, and the half adder 18 adds "1" to the upper 5 bit data 17 of the 8-bit register 11 and outputs the result. In each cycle from the 5th cycle to the 2jth cycle, the first
The output 23 of the comparator 16 is “O (low level) 9
Therefore, the half adder 1B outputs the upper 5 bit data 17 of the 8-bit register 11 as it is.

Therefore, the comparator 22 outputs the pulse width modulated signal 22 (solid line) in FIG. Output. +81 in FIG. 3 is a sampling clock. In addition, in FIG. 3 (C1, (dl), the change in the output 19 of the half adder 18 is drawn larger than it actually is for the sake of clarity. The output of the second comparator 21 is The pulse width is “
They are added in increments of 1", and the total pulse width is 8-bit data pulse width modulated.

Note that although this embodiment is configured using hardware, it may also be configured using software.

Further, in the above embodiment, a 5-pin counter 7, a 3-bit counter 9, and an 8-bit register 11 are used, but the number of bits of the counter and register is not limited to the above.

〔Effect of the invention〕

According to this invention, a pulse width modulation period is divided into a plurality of periods, a pulse having a pulse width corresponding to the modulated data given for each pulse width modulation period is divided into a plurality of pulses, and the divided pulse is divided into a plurality of pulses within each division period. , it is possible to create a plurality of high level sections and low level periods within the pulse width variable circular period. As a result, the frequency of pulse width modulation can be increased, the cutoff frequency of the low-pass filter can be increased, and the phase delay in the control band caused by the low-pass filter can be reduced, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pulse width modulation circuit in an embodiment of the present invention, FIG. 2 is a time chart of the embodiment of FIG. 1 when the lower three focus data is "0", and FIG. 3 1 is a time chart of the embodiment of FIG. 1 when the lower 3 bits are "4", and FIG. 4 is a block diagram showing the configuration of a conventional pulse width modulation circuit. 7...5-bit counter, 9...3-bit counter, 11...8-bit register, 16...first comparator, 18...half adder, 21...second comparator 1゜Figure 1 Figure 2

Claims (3)

[Claims] (1) The pulse width modulation period is divided into a plurality of periods, and within each division period, a divided pulse is obtained by dividing into a plurality of pulses having a pulse width corresponding to the modulated data given for each pulse width modulation period. A pulse width modulation method that is characterized by the following: (2) The modulated data is m+n bits (m and n are positive integers), and the pulse width modulation period is divided into 2^n,
The 2^n divided pulses arranged in each of the 2^n divided periods are set to a pulse width corresponding to the upper m-bit data of the modulated data, and the The pulse width of a number of divided pulses corresponding to the lower n bits of the modulated data is increased by a width corresponding to the least significant bit of the modulated data from the beginning of a pulse width modulation period. Pulse width modulation method. (3) An m+n bit register that latches m+n bits of modulated data according to a sampling clock generated every pulse width modulation period, and
an m-bit counter that counts a count clock having a period divided by m^+^n; an n-bit counter that counts the carry output of this m-bit counter;
a first comparator that compares lower n-bit data of the +n-bit register with a count value of the n-bit counter and generates an output when the lower n-bit data of the m+n-bit register is greater than the count value of the n-bit counter; , a half adder that adds the output of the first comparator to the upper m bit data of the m+n bit register as the least significant bit data of the upper m bit data, and the output data of the half adder and the m bits. a second comparator that compares the count value of the counter and generates an output as a pulse width modulation signal when the output data of the half adder is larger than the count value of the m-bit counter.