JPH044775B2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a high-precision, high-bit D/A (digital/analog) converter, and includes devices equipped with various D/A converters, For example, it is used in speech synthesizers, CD (compact disc) players, etc.

(b) Prior Art Various types of D/A converters have been put into practical use. Japanese Unexamined Patent Publication No. 57-23321 discloses a D/A converter that combines the advantages of amplitude modulation (AM) type and pulse width modulation (PWM) type, does not require high precision resistors, and has high conversion speed. ing. However, the PWM type D/A converter had the drawback of high harmonic distortion.

In order to solve this problem, a patent application was made in the 1980s.
It is number 14032. This is a conventional PWM type D/
Unlike A converters, which change the pulse width within one conversion cycle depending on the content of digital data,
Since the analog signal is output so that the two potentials are widely dispersed within one conversion cycle period according to the input digital data, the harmonic spectrum of the analog signal that is the output of this D/A converter is large in the high range. It becomes small in the low range, and by band limiting, harmonic distortion is aimed at low range.

Recently, equipment that requires D/A converters, such as those used in the digital audio field, is required to be lower in price, lower in power consumption, and smaller in size.
Similar demands are made for D/A converters as well.

In order to reduce the size and cost of the D/A converter that combines the AM type and PWM type described in the above-mentioned patent application No. 14032/1980, it is sufficient to reduce the chip size. It is effective to reduce the size of the voltage divider circuit in the AM type D/A conversion section, which occupies a large portion of the power supply. In other words, AM type D/
It is sufficient to reduce the number of bits processed by the A converter. However, if the number of bits processed by the AM type D/A converter is reduced, the number of bits processed by the PWM type D/A converter increases, so the clock pulses in the PWM type D/A converter must be counted. The base number of the counting circuit increases, and the conversion speed decreases accordingly. In order to avoid this, it is possible to increase the frequency of the clock pulse, but this increases power consumption, which is not preferable for battery drive. In addition, if the frequency of the clock pulse is high, switching noise will increase and unnecessary radiation will occur during mounting, resulting in
The performance as an A converter will deteriorate.

On the other hand, it is known that ordinary D/A converters generate glitch noise during data conversion due to mismatching delay times in decoding circuits. To deal with such glitch noise, a sample and hold circuit is provided after the D/A converter.
Although it is effective to perform sampling when the output of the D/A converter becomes stable,
If the converter is highly accurate, the sample-and-hold circuit itself must also be highly accurate and must be constructed from expensive, high-precision elements.

(c) Problems to be Solved by the Invention As mentioned above, there are various difficulties in reducing the chip size of a D/A converter that combines an AM type and a PWM type, and the present invention is intended to solve the problems of a small and low-cost D/A converter. /
This is an attempt to solve the problem that has made it difficult to realize an A converter. Furthermore, it is an object of the present invention to avoid the influence of the glitch noise without using a sample-and-hold circuit using expensive high-precision elements.

(d) Means for Solving the Problems The present invention provides a digital/digital converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data.
A converter, in order to solve the above problems,
A decoder that decodes the upper bits of N-bit digital data, a voltage divider circuit that divides the voltage between the first reference potential and the second reference potential using ^2M resistors, and an output from the decoder from the voltage divider circuit. A first device comprising a means for selectively extracting two adjacent potentials according to the
a D/A conversion circuit, a clock generating means for generating clock pulses provided for the middle K bits of the N bits of digital data, and a 2 ^K -ary counting circuit for counting the clock pulses from the clock generating means; A pulse forming circuit receives digital data of the middle K bits among the N bits and the count output of the counting circuit and outputs a pulse signal according to the contents of the digital data of the middle K bits, and the output of the pulse forming circuit is means for selecting and combining one of two adjacent potentials output from the first D/A conversion circuit in response to a certain pulse signal; a second D/A conversion circuit provided with means for forming a period in which the output terminal is in a high impedance state; first and second resistor networks connected respectively between one end of the voltage divider circuit and between the second reference potential and the other end of the voltage divider circuit; The resistance values of the first and second resistance networks are varied while keeping the sum of the resistance values of the first resistance network and the second resistance network constant according to the content of the digital data. and a third D/A conversion circuit having means.

(E) Effect The lower J bit data of the N bit digital data is given to the third conversion circuit, and the voltage is applied to both ends of the voltage dividing circuit in the first D/A conversion circuit according to the J bit data. The potential is changed while the potential difference is constant, and the potential divided and taken out from this voltage dividing circuit is changed. Then, the first D/A converter circuit selects and outputs the two adjacent potentials taken out from this voltage divider circuit according to the data of the upper M bits, and the second D/A converter circuit selects and outputs them. One of these two adjacent potentials is selected and combined in accordance with the middle K-bit data, and an analog signal corresponding to the N-bit digital data is output. Furthermore, the second D/A conversion circuit includes means for forming a period in which the output end of the combining means is in a high impedance state, so that:
Data conversion can be performed during this period.

(F) Embodiment FIG. 1 is a schematic diagram of a D/A converter according to the present invention. Reference numeral 1 designates a first D/A conversion circuit, which is composed of a decoder 11 that decodes the upper M bits of digital data of input N (=M+K+J) bits, and ^2M resistors R. It consists of a voltage dividing circuit 12 that divides the potential difference between the potentials applied to both ends, and a switching circuit 13 that selects and extracts two adjacent potentials V ₁ and V ₂ from the voltage dividing circuit 12 in accordance with the output of the decoder 11. 2 is a second D/A conversion circuit, which includes a clock pulse generator 21 that generates clock pulses and counts clock pulses from the clock pulse generator 21;
2 ^K -ary counting circuit 22, a pulse forming circuit which takes as input the middle K bit data of the N bits and the output from the counting circuit 22, and outputs a pulse signal having a pulse width corresponding to the K bit data. 23 and
A gate circuit 24 that gates the pulse output of the pulse forming circuit 23, and two switching transistors 25a and 25 that perform complementary switching operations.
b, selects and synthesizes one of the two adjacent potentials V ₁ and V ₂ output from the first D/A conversion circuit 1 according to the pulse signal that has passed through the gate circuit 24. a selection synthesis circuit 25 for
RC integration circuit 26 Low pass filter 2 with _RC
It consists of 6. 3 is a level shift circuit as a third D/A conversion circuit, and the first reference potential Vref1
and one end of the voltage dividing circuit 12, a second reference potential
It is provided between Vref2 and the other end of the voltage dividing circuit 12. This level shift circuit 3 is input with data of the lower J bits among the N bits.
In accordance with this data, the potential applied to both ends of the voltage dividing circuit 12 is changed while maintaining the potential difference.

Below, N=16 and the input data a ₁₅ , a ₁₄ ,
..., a ₀ , the upper one to the first D/A conversion circuit 1
8 bits of a ₁₅ , a ₁₄ , ..., a ₈ (M = 8), 4 bits of medium a ₇ , a ₆ , a ₅ , a ₄ (K = 4) to the second D/A conversion circuit 2 , a case will be described in which the lower 4 bits a ₃ , a ₂ , a ₁ , a ₀ (J=4) are provided to the third D/A conversion circuit 3.

FIG. 2 is a circuit configuration diagram of the level shift circuit 3, which is the third D/A conversion circuit. This level shift circuit 3 includes a voltage dividing circuit 12 of the first D/A conversion circuit 1, a first reference potential Vref1, and a second reference potential Vref1.
It is provided between Vref2 and the lower J bits of data a ₃ , a ₂ , a ₁ , a ₀ are given. Voltage divider circuit 12
Resistors R ₁ , R ₂ , R ₃ , R ₄ are connected between one end of Vref1 and Vref1.
are connected in series in this order, and voltage divider circuit 1
Resistors R ₅ , R ₆ , R ₇ ,
R ₈ are connected in series in this order. A resistor _R9 and a switching transistor _T1 are connected across the resistor _R1 .
The series circuit is connected to the voltage dividing circuit 12 side. Similarly, resistors R ₂ , R ₃ , R ₄ ,
Resistors R _{10 ,} R _{11 , R 12 ,}
A series circuit of R ₁₃ , R ₁₄ , R ₁₅ , R ₁₆ and switching transistors T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , T ₇ , T ₈ is formed by a resistor that divides the voltage. It is connected so that it is on the circuit 12 side. And J (=4)
Each of the bit data a ₀ , a ₁ , a ₂ , and a ₃ is directly connected to the respective gates of the switching transistors T ₁ , T ₂ , T ₃ , and T ₄ , and also to the switching transistors T ₅ ,
The signal is applied to each gate of T ₆ , T ₇ , and T ₈ via an inverter 40 .

Assuming that the resistance values of the resistors R ₁ to R ₁₆ and the resistor R of the voltage dividing circuit 12 are as indicated by the symbols, each resistance value is determined so as to satisfy the following relational expression.

R ₁ , ~, R ₃ = R R ₉ = R ₁₃ = 255 x R = (2 ^K+J -1) x R R ₁₀ = R ₁₄ = 127 x R = (2 ^K+J-1 -1) x R R ₁₁ = R ₁₅ = 63 x R = (2 ^K+J-2 -1) x R R ₁₂ = R ₁₆ = 31 x R = (2 ^{K+ J-3} -1) x R If the resistance value between one end A and Vref1 is R _A and the resistance value between the other end B and Vref2 is R _B , when switching transistor T ₁ or T ₅ is turned on, R _A or R _B is R-255R×R/
(255R+R) = R/256 smaller. Similarly T ₂
Or if T ₆ is on, R _A or R _B is R/128 If T ₃ or T ₇ is on, R _A or R _B is R/64 If T ₄ or T ₈ is on, R _A or R _B becomes smaller by R/32.

Due to the presence of the inverter 40, the switching transistors T ₁ to T ₄ and T ₅ to _{T 8} are turned on and off in a complementary manner, so that Vref1 does not depend on the values of a ₀ to _{a 3} .
The resistance value Rj between and Vref2 is maintained at Rj=(2 ¹⁶ +8−15/256)R. That is, while the potential difference between point A and point B is kept constant, _{R A} , R _A ,
Since R _B is changed to 0, R/256, 2R/256, ..., 15R/256, the level of the voltage dividing output terminal of the voltage dividing circuit 12, that is, V ₁ and V ₂ , is changed to 16 gradations (4 bits). Can be shifted.

Here, a case will be described in which one bit of the minimum resolution (1LSB) among N (=16) bits of data changes.

J = 4 bits of data a ₀ , a ₁ , a ₂ , a ₃ are a ₀ = a ₁
When = a ₂ = a ₃ = 0, R _A = 4R R _B = 4R - 15R/256, and the potential V _B (0) at point B is V _B (0) = (Vref1 - Vref2) x ( 4R−15R/
256)/Rj.

Next, when a ₀ = 1, a ₁ = a ₂ = a ₃ = 0, R _A = 4R-R/256 R _B = 4R-14R/256, and the potential V _B (1) at point B is V _B (1) = (Vref1−Vref2)×(4R−14R/256)
It becomes Rj. Therefore, the potential difference between V _B (0) and V _B (1)
E _LSB is E _LSB = {(Vref1−Vref2)×R/Rj}/256. Since the voltage step e _M between the divided voltage output terminals of the voltage dividing circuit 12 is e _M = (Vref1 - Vref2) x R/Rj, E _LSB is the potential divided by the voltage dividing circuit 12. /256 (=1/2 ⁸ ).

In other words, the level shift circuit 3, which is the third D/A conversion circuit, shifts the potential divided and output from the voltage dividing circuit 12 according to the input J=4 bit data _a3 to _a0 . are doing.

In the first D/A conversion circuit 1, the input M=
The 8-bit data a ₁₅ to _{a 8} are decoded by the decoder 11, and among the level-shifted divided voltage outputs of the voltage dividing circuit 12, two adjacent potentials V ₁ and V ₂ are converted into decoded results by the switching circuit 13. It is selectively output based on.

Now, in the second D/A conversion circuit 2, while the 2K counting circuit 22 counts ^2K clock pulses output from the clock generator 21 (one conversion period), ^the number of K bits input is A pulse signal corresponding to the data a ₇ to a ₄ is output from the pulse forming circuit 23 . FIG. 3 shows a schematic circuit diagram of the pulse forming circuit 23 corresponding to K=4 bits.

The pulse forming circuit 23 inputs the count outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ of the counting circuit 22 and the clock pulse CLK from the clock generator 21, receives each clock pulse CLK at the clock input terminal, and outputs the clock pulse CLK to the D input terminal. The first one inputs the counting outputs Q ₂ , Q ₃ , and Q ₄ at the ends, respectively.
2nd and 3rd D flip-flops 27, 28, 29
and a first AND gate 30 whose inputs are bit data _a7 of the K-bit data and count output _Q1 ,
A second AND gate 31 inputs the bit data a ₆ , _the counting output Q ₂ , and the Q output of the first D flip-flop ₂₇ ;
The third input terminal inputs the Q output of the flip-flop 28.
AND gate 32, bit data a ₄ and count output
A fourth AND gate 33 receives Q ₄ and the Q output of the 3D flip-flop 29;
2nd, 3rd, and 4th AND gates 30, 31, 3
The OR gate 34 receives the respective outputs C ₁ , C ₂ , C ₃ , and C ₄ of C 2 and 33, and the output C ₀ of the OR gate 34 is output to the gate circuit 24 .

In other words, the high and low digits of the input digital data and the high and low output of the counting circuit 22 are combined in reverse order, and the AND gates 30, 31, 32, 33
Q ₂ , Q ₃ , and Q ₄ other than the least significant digit of the output of the counting circuit 22 are also applied to D flip-flops 27 , 28 , and 29 driven by the clock pulse CLK to be counted, respectively. The outputs of these flip-flops are also applied to AND gates 31, 32, and 33 in the same way as Q ₂ , Q ₃ , and Q ₄ .

FIG. 4 for explaining the typical operation of this pulse forming circuit 23 shows K=4 bits in the first, second, and third periods T ₁ , T ₂ , and T ₃ each corresponding to one conversion period. Data "12" (a ₄ = 0, a ₅ = 0, a ₆ = 1, a ₇ = 1), data "8" (a ₄ = 0, a ₅ = 0, a ₆ = 0, a ₇ = 1), and data “1” (a ₄ = 1, a ₅ = 0, a ₆ = 0, a ₇ =
0) is respectively input to the second D/A conversion circuit 2. In the first period T _C1 , significant information "1" is given to bit data a ₆ and a ₇ , so the first , AND gate outputs C ₁₁ and C ₂₁ appear at the second AND gates 30 and 31, respectively.
On the other hand, since there is no significant information in the third and fourth AND gates 32 and 33, the output C ₀ of the OR gate 34 contains C ₁₁ ,
The logical sum of C ₂₁ , C ₀₁ , appears. This C ₀₁ is a pulse signal that represents "12" as the sum of the pulse widths, that is, the sum of the periods in which it is "1", and is approximately equally "1" and "0" throughout the first period T _C1 . ” are the distributed pulse width and pulse period.

In the second period T _C2 , only bit data a ₇ is input with significant information “1”, so the OR gate 34
A pulse signal C ₀₂ corresponding to the output C ₁₂ of the first AND gate 30 is outputted from. This C ₀₂ is a pulse signal whose total pulse width represents "8", and the pulse width is approximately equal to "1", "1", and "1" throughout the second period T _C2 .
These are the pulse width and pulse period in which each “0” is distributed.

Furthermore, the third
During the period T _C3 , significant information "1" is input only to the bit data _a4 , so the OR gate 34 outputs a pulse signal _C03 that matches the output _C43 of the fourth AND gate 33.

FIG. 5 summarizes the relationship between the pulse signal C ₀ output from the pulse forming circuit 23 and the input 4-bit digital data for one conversion period _TC .

Regardless of the 4-bit digital data that is input in this way, the pulse width and pulse period change depending on the input data so that the pulses are approximately evenly distributed within one conversion period _Tc , and , the sum of the pulse widths is determined. This is true even if the number of bits K of the input digital data is larger or smaller than 4.

The pulse signal C ₀ output in this way is
The signal is input to the gate circuit 24. Gate circuit 24
are a fifth AND gate 24b, a sixth AND gate 24c, to which the pulse signal C ₀ is input complementary to one input terminal of each due to the presence of the inverter 24a, and the fifth and sixth AND gates 24b,
The gate control circuit 24d outputs a gate control signal to the other input terminal of the gate control circuit 24c, and outputs a pulse signal _C0 having a pulse width and a pulse period according to the input data as shown in FIG.
An arbitrary period of the PWM clock cycle generated by the clock generator 21 by the gate control circuit 24d at the end of one conversion period T _C , for example, a period of 2/1 Tni
-z the fifth and sixth AND gates 24b and 2;
Close both gates in 4c. The pulse signals C ₀ and C ₀ that have passed through the gate circuit 24 are applied to the gates of the switching transistors 25b and 25a, respectively, and perform complementary switching operations to change the connection mode of both transistors 25a and 25b to the low-pass filter 26. Connected to obtain analog signal Vout. That is, while the output pulse signal _C0 of the pulse forming circuit 23 is "1", the transistor 25
a is turned on and the first potential V ₁ output from the first D/A conversion circuit 1 is selected, and while the pulse signal is "0", the transistor 25b is turned on and the second potential V ₂ is selected. is selected. These potentials are synthesized in time series, harmonic components are removed by a low-pass filter 26, and then output.

V ₁ output from the first D/A conversion circuit 1,
From the above explanation, V ₂ can be expressed as follows.

V ₂ = {(Vref1−Vref2)/Rj}×{4R−15R/
256+ (a ₁₅ ×2 ⁷ +a ₁₄ ×2 ⁶ +…+a ₈ ×2 ⁰ )R+(a ₃
×2 ³ +a ₂ ×2 ² +a ₁ ×2 ¹ +a ₀ ×2 ⁰ )R/256}
=Vconst+(a ₁₅ ×2 ⁷ +a ₁₄ ×2 ⁶ +…+a ₈ ×
2 ⁰ )×e _M + (a ₃ ×2 ³ +a ₂ ×2 ² +a ₁ ×2 ¹ +a ₀ ×
2 ⁰ )×e _M /256 V ₁ =V ₂ +e _M However, Vconst=(Vref1−Vref2)×(4R−
15R/256)/Rj The output Vout of this D/A converter is the second D/A converter.
In the A conversion circuit 2, the potential of e _M (=V ₁ - V ₂ ) is set to 16
(= ^2K ) is divided and combined and output, so Vout=V ₂ + (a ₇ × 2 ³ + a ₆ × 2 ² + a ₅ × 2 ¹ + a ₄ × 2 ⁰ )
×e ^M /16. Therefore, Vout=Vconst+(a ₁₅ ×2 ⁷ +a ₁₄ ×2 ⁶ +…+a ₈ ×
2 ⁰ ) × e _M + (a ₇ × 2 ³ + a ₆ × 2 ² + a ₅ × 2 ¹ + a ₄ ×
2 ⁰ ) ×e _M /16+(a ₃ ×2 ³ +a ₂ +a ₁ ×2 ¹ +a ₀ ×2 ⁰ )
e _M /256 = (a ₁₅ ×2 ⁷ +a ₁₄ ×2 ⁶ +…+a ₈ ×2 ⁰ +a ₇ ×2 ³
+a ₆ ×2 ² +a ₅ ×2 ¹ +a ₄ ×2 ⁰ +a ₃ ×2 ³ +a ₂ ×
2 ² +a ₁ ×2 ¹ +a ₀ ×2 ₀ ) × e _M /256 + Vconst. In other words, in FIG. 1, it is a 16-bit D/A converter with e _M /256 as the LSB.

Compared to a conventional D/A converter circuit which is a combination of only a first D/A converter circuit and a second D/A converter circuit, in the D/A converter of the present invention, each D/A converter The number of bits input to the conversion circuit is reduced. Second D/A conversion circuit (PWM type)
When the number of input bits in is 8 bits, the clock frequency of the counting circuit is equal to the sampling period.
Requires 11.29MHz or more, which is ²⁸ times 44.1KHz,
If this is 4 bits, the clock period is ²⁴ times
705.6KHz or higher is sufficient. This is D/
As an A converter, it is possible to realize a high performance device that consumes less power and has less switching noise and unnecessary radiation due to high frequency clock pulses.

Furthermore, if the number of bits input to the first D/A conversion circuit (AM type) is reduced, the number of high-precision resistors can be reduced accordingly, and the chip size can be reduced. Especially since the number of resistors is ^2M , the effect is very large.

Note that the resistors used in the level shift circuit, which is the third D/A conversion circuit, are made by connecting low resistance values R ₁ to R ₈ and high resistance values R ₉ to _{R 16} in parallel. Since the resistance values of R 9 to R 16 are digitally converted, high precision is not required for the high resistance values of R ₉ to _{R 16} . For example, resistors R ₁ , R ₅ , R ₉ ,
_R13 represents the minimum resolution (LSB) of 16 bits, but the resistance ratio required for _R1 , _R5 and _R9 , _R13 (within the range of ±1/2LSB) is 1:170.
~511, and R ₉ and R ₁₃ do not require as much precision as the resistors used in voltage divider circuits. Therefore, the amount of increase in chip size due to the addition of the third D/A conversion circuit is small.

On the other hand, the gate circuit 24 is connected to the gate control circuit 24.
At the end of one conversion period T _C by the gate control signal of d,
i.e. the fifth period during the period Tniz, immediately before the next conversion period.
and closes the sixth AND gates 24b and 24c. Therefore, due to the closure of both AND gates 24b and 24c, the switching transistor 25 in the subsequent stage
a and 25b are turned off, and the impedance becomes infinite. Then, when facing the switching transistors 25a and 25b of the preceding stage, the operational amplifier 26 _OP in the low-pass filter 26 _and the capacitor 26c, which constitutes the RC integrating circuit 26 _RC provided before the operational amplifier 26 OP, and whose one end is grounded, ,
Since both of the transistors 25a and 25b are in a high impedance state, they hold the potential immediately before going into a high impedance state, so that they pseudo-function as a sample-and-hold circuit. Here, it is preferable that the potential immediately before being held by the capacitor 26c is the potential (Vlow) at the end of discharging of the capacitor 26c. That is,
By sampling and holding Vlow, the influence of glitch noise can be reliably suppressed. That way
In order to hold the potential of Vlow, it is sufficient to select a CR time constant that allows discharge of the charge accumulated in the capacitor 26c to be completed before the switching transistors 25a and 25b enter the high impedance state as described above. In this way, the RC integrating circuit 26 _RC that constitutes a part of the low-pass filter 26,
The operational amplifier 26 _OP operates as a sampling hold circuit effective against glitch noise because the switching transistors 25a and 25b are in a high impedance state and the discharge of the capacitor 26c is completed at the end of the conversion period _TC .

FIG. 6 shows another example of the third D/A conversion circuit. In FIG. 6, a J-bit data decoder 41 is provided, and a voltage dividing circuit 12 is provided.
The resistors connected in series are one each on each side of R ₂₀ and R ₃₀ , and one or more high resistances are connected in parallel to these resistors R ₂₀ and R ₃₀ depending on the input digital data. It is.

That is, the resistor R ₂₀ has the resistors R ₂₁ , R ₂₂ , R ₂₃ ,...,
A series circuit of Rn and a switching transistor Tn is connected in parallel, and the transistor Tn and a resistor R ₂₀ are connected to a signal line and each resistor R ₂₁ , R ₂₂ , R ₂₃ ,
Switching transistors T ₂₁ , T ₂₂ , T ₂₃ , . . . are connected between the connection modes of . . . , Rn. Similarly, on the resistor R ₃₀ side, there are resistors R ₃₁ , R ₃₂ , R ₃₃ ,
…, Rm and switching transistor T ₃₁ ,
T ₃₂ , T ₃₃ , ..., Tm are connected.

J-bit data is input to a decoder 41. The decoder uses one of switching transistors T ₂₁ , T ₂₂ , T ₂₃ , ...Tn and switching transistors T ₃₁ , T ₃₂ , T ₃₃ , Tn according to input data.
..., Tm, and one or more high resistances R ₂₁ , R ₂₂ , ..., R ₃₁ , R ₃₂ , ..., etc. determined by the turned-on transistor.
It is connected in parallel with each of R ₂₀ and R ₃₀ to level shift the divided voltage output of the voltage dividing circuit 12.

(G) Effects of the Invention As is clear from the above description, the present invention includes an AM type first D/A conversion circuit, a PWM type second D/A conversion circuit, and a third D/A conversion circuit using a level shift circuit.
Since one D/A converter is made up of several D/A conversion circuits, the number of bits of data input to each conversion circuit can be reduced, reducing the chip size of the D/A converter and reducing power consumption. It is possible to reduce the noise and reduce the noise. Furthermore, the second D/A conversion circuit includes means for forming a period in which the output end of the combining means is in a high impedance state, so that
Since the data can be converted during this period, even if glitch noise occurs during conversion, it will not be output from the output end of the synthesizing means, and the D/A conversion output will not be affected by glitch noise.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of the conversion circuit of FIG. 3, and FIG.
FIG. 4 is a time chart explaining the operation of the pulse forming circuit, FIG. 5 is a waveform diagram showing the relationship between the input signal and output signal of the pulse forming circuit, and FIG. 6 is the third D. FIG. 3 is a circuit configuration diagram of another embodiment of the /A conversion circuit. 1... First D/A conversion circuit, 2... Second D/A conversion circuit, 3... Third D/A conversion circuit,
11...Decoder, 12...Voltage dividing circuit, 1...Switching circuit, 21...Clock generator, 22
... Counting circuit, 23 ... Pulse forming circuit, 24 ...
...Gate circuit, 25...Selective synthesis circuit, 26...
low pass filter.

Claims (1)

[Claims] 1 In a D/A converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data, a decoder that decodes the upper M bits of the N bits of digital data, a first standard. Potential and second
A first D/A converter comprising: a ^voltage dividing circuit that divides the voltage between a reference potential of A clock generating means for generating clock pulses provided for the middle K bits of the N bits of digital data, a ^2K counting circuit for counting the clock pulses from the clock generating means, and a clock generating means for generating clock pulses for the middle K bits of the N bits of digital data; A pulse forming circuit receives digital data of the middle K bits and the count output of the counting circuit and outputs a pulse signal according to the contents of the digital data of the middle K bits, and a pulse signal output from the pulse forming circuit is used. said first D/ for a defined period of time.
Means for selecting one of the two adjacent potentials output from the A conversion circuit and selecting the other during the remaining period and synthesizing the same, the synthesizing means selecting neither of the two neighboring potentials, but outputting the synthesizing means a second D/A conversion circuit comprising means for forming a period in which the end is in a high impedance state; first and second resistor networks connected respectively between one end of the voltage divider circuit and between the second reference potential and the other end of the voltage divider circuit; The resistance values of the first and second resistance networks are varied while keeping the sum of the resistance values of the first resistance network and the second resistance network constant according to the content of the digital data. a third D/A converter circuit comprising means, and averages the combined output from the second D/A converter circuit over a predetermined period to obtain an analog output. A converter. 2. The pulse forming circuit outputs a pulse signal whose pulse width and pulse period change according to the contents of the middle K bit digital data, and whose pulse width is determined by the sum of the pulse widths in 2 ^K clock periods. A D/A converter according to claim 1, characterized in that: