JPH084224B2 - D / A converter - Google Patents

Description

The present invention relates to a high-precision, high-bit D / A converter, which is equipped with various D / A converters, such as a CD (compact compact). It is used for a disc) player and a voice synthesizer.

(B) Conventional technology D / A conversion is required for devices that require D / A converters in the recent fields of digital audio, etc., because of low cost, low power consumption, and miniaturization. The container must meet the demand.

Therefore, by combining the strengths of the amplitude modulation (AM) type and pulse width modulation (PWM) type D / A converters, a compact D / A converter that does not require high-precision resistors and has a high conversion speed can be used. In order to achieve cost reduction and cost reduction, it is necessary to reduce the chip size of the semiconductor element in which the D / A converter is integrated. To this end, it is effective to reduce the voltage dividing circuit that occupies most of the D / A converter. That is, the number of bits processed by the AM type D / A conversion unit may be reduced. However, if the number of bits processed by the AM type D / A conversion unit is reduced, the number of bits processed by the PWM type D / A conversion unit will increase, so the clock pulse in the PWM type D / A conversion unit will be reduced. The number of steps of the counting circuit for counting increases, and the conversion speed decreases accordingly. To avoid this, the frequency of the clock pulse may be increased, but this increases power consumption and is not preferable for battery drive. Further, when the frequency of the clock pulse is high, switching noise increases and unnecessary radiation occurs during mounting, which deteriorates the performance as a D / A converter.

Therefore, Japanese Patent Application No. 61-23624 proposes a D / A converter that can reduce the number of bits processed by the AM type D / A conversion unit and reduce the size of the voltage dividing circuit without degrading the performance. ing. The block diagram is shown in FIG.

In FIG. 4, (1) is the first D / A conversion circuit, and the input N (= M
A decoder (11) for decoding higher-order digital data of + K + J) bits of digital data, and a voltage divider circuit (12) composed of 2 ^M resistors R for dividing the potential difference between both ends thereof. It is composed of a switching circuit (13) for selecting and extracting the adjacent two potentials V ₁ and V ₂ from the voltage dividing circuit (12) according to the output of the decoder (11).
(2) is a second D / A conversion circuit, which is a clock pulse generator (21) for generating a clock pulse, and a 2 ^K- ary counter circuit ( ^C ) for counting clock pulses from the clock pulse generator (21) ( 22), and a pulse forming circuit (23) which outputs a pulse signal having a pulse width corresponding to the K-bit data, by inputting the middle K-bit data of N bits and the output from the counting circuit (22). And two switching transistors (24b) (2
4c) and is configured to correspond to the pulse signal
The low-pass filter (25) includes a selective combination circuit (24) for selecting and combining one of the _two adjacent potentials V ₁ and V ₂ output from the D / A conversion circuit (1). (3) is a level shift circuit as a third D / A conversion circuit, which has a first reference potential
It is provided between Vref1 and one end of the voltage dividing circuit (12), and between the second reference potential Vref2 and the other end of the voltage dividing circuit (12). The lower J-bit data of N bits is input to the level shift circuit (3), and the potential applied to both ends of the voltage dividing circuit (12) is changed according to the data.
It changes while maintaining the potential difference.

In the following, N = 16, and among the input data a ₁₅ , a ₁₄ ..., A ₀ , ₈ of the higher order a ₁₅ , a ₁₄ , ... A ₈ to the first D / A conversion circuit (1)
Bit (M = 8) the second D / A conversion circuit (2) to the medium a _7,
4 bits of a ₆ , a ₅ and a ₄ (K = 4), 4 bits of lower a ₃ , a ₂ , a ₁ and a ₀ to the third D / A conversion circuit (3) (J = 4) The case where it is configured to give

In the first D / A conversion circuit (1), the voltage between the one end A and the other end B is divided into 1/256 by the resistor R by the voltage dividing circuit (12), and the input M = 8-bit data a the ₁₅ ~a ₈ based on the result of decoding by the decoder (11), and outputs a proximity second potential of the divided output as V ₁ and V ₂ are selected by the switching circuit (13).

Further, the level shift circuit (3), which is the third D / A conversion circuit, includes the voltage dividing circuit (12) of the first D / A conversion circuit (1).
The voltage divided by is further divided into 1/256, that is, the voltage e _M corresponding to the minimum bit is created, and the lower order J = 4 bits of data a _{3 to} a ₀ are input. The voltage across the voltage divider circuit (12) is shifted in the same direction in steps of voltage e _M. Therefore, the voltages V ₁ and V ₂ selected and output by the switching circuit (13) of the first D / A conversion circuit (1)
The voltage difference of does not change, and the voltage level changes in steps of the voltage e _M corresponding to the smallest bit.

On the other hand, the second D / A conversion circuit (2), a clock pulse outputted from the clock generator (21) between (1 conversion period) of 2 ^K number counted by 2 ^K-ary counting circuit (22) , A pulse signal corresponding to the inputted K = 4 bit data a _{7 to} a ₄ is output from the pulse forming circuit (23). That is, a pulse with a pulse width obtained by dividing 1 conversion period into 1/16 is input data
outputs for the number represented by a ₇ ~a _4.

The pulse signal C ₀ output in this manner is input to the selection synthesis circuit (24). The selective combining circuit (24) includes a switching transistor (24b) to which a pulse signal is directly applied to its gate, an inverter (24a) to which a pulse signal is applied, and a pulse signal to its gate via this inverter (24a). Switching transistor (24c) that is connected to both transistors (24b), (24c)
The connection mode of is connected to the low pass filter (25) to obtain the analog signal Vout. While the output pulse signal of the pulse forming circuit (23) is "1", the transistor (24b) is turned on and the first potential V ₁ output from the first D / A conversion circuit (1) is selected. Then, while the pulse signal is "0", the transistor (24c) is turned on and the second potential V ₂ is selected. These potentials are combined in time series, the harmonic components are removed by the low-pass filter (25), and the result is output.

(C) Problems to be solved by the invention However, in the above-mentioned D / A conversion circuit, if the number of bits is further increased, if the number of bits of the voltage dividing circuit is increased, the AM type D / A conversion circuit section Of the PWM type D / A converter has a problem in that the conversion speed is delayed or the current consumption is increased due to the higher frequency. Furthermore, when the number of bits of the level shift circuit is increased, the number of weighted voltages created in the level shift circuit increases, which causes a problem that the characteristics of the D / A conversion circuit deteriorate.

(D) Means for Solving the Problems The present invention was created in view of the above-mentioned points, and includes a decoder for decoding upper M bits of N-bit digital data, a first reference potential and a first reference potential. A first voltage divider circuit that divides between the reference potential shown in FIG. 2 and a reference potential by 2 ^M resistors, and means for selectively taking out two adjacent potentials according to the output of the decoder from the voltage divider circuit. A conversion circuit, clock generating means for generating clock pulses, 2 ^K- ary counting circuit for counting clock pulses from the clock generating means, middle K bits of the N bits of digital data and counting by the counting circuit A pulse forming circuit that receives an output as an input and outputs a pulse signal according to the content of the middle K-bit digital data, and a proximity output from the first D / A conversion circuit according to the pulse signal of the pulse forming circuit. Two A second D / A conversion circuit having means for selecting and synthesizing positions, inputting the count output from the counting circuit and the lower Q bits of the lower J bits of the N-bit digital data, A pulse forming circuit for outputting a pulse signal according to the content of the Q bit, provided between the first reference potential and one end of the voltage dividing circuit and between the second reference potential and the other end of the voltage dividing circuit. 1 / of the potential unit divided by the voltage dividing circuit based on the data content of the upper P bits of the lower J bits.
In a period of 2 ^{(K + P)} steps, the voltage at one end and the other end of the voltage dividing circuit is shifted, and during the period controlled by the pulse output of the pulse forming circuit, 1/2 ^{(K + P )}
Third with a level shift circuit for shifting steps
With the D / A converter circuit of D / A
A converter is provided.

(E) Action According to the above-mentioned means, the upper P-bit data in the lower J-bits of the N-bit digital data is the third data.
Of the voltage applied to the D / A conversion circuit of the first D / A conversion circuit according to the P-bit data in the J-bit and the potential difference thereof is kept constant. The voltage divided by the voltage circuit is changed in steps of 1/2 ^{(K + P)} . Further, the third D / A conversion circuit divides a pulse, which is obtained by dividing the period having an integral fraction of the conversion cycle of the second D / A conversion circuit into 1/2 ^Q , into the input J-bit. Output as many as the lower Q-bit data in the output, and while the pulse is output, shift the voltage across the level-shifted voltage divider circuit by a voltage of 1/2 ^{(K + P).} By doing so, weighting of the least significant bit is added to the output voltage of the first D / A conversion circuit by pulse width modulation. As a result, the level shift circuit of the third D / A conversion circuit can increase the number of bits by the amount of pulse width modulation.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
The same parts as those of the conventional circuit shown in FIG. 4 are designated by the same reference numerals and the description thereof is omitted.

The third D / A conversion circuit (4), which is a feature of the present invention, is provided between the first reference potential Vref1 and one end A of the voltage dividing circuit (12) of the first D / A conversion circuit (1). , And the second reference potential Vref2
A second D / A and a level shift circuit (41) which is respectively provided between the voltage dividing circuit (12) and the other end B of the voltage dividing circuit (12), to which the upper P bits of the lower J bits of the N bits are applied. A count output of the counting circuit (22) of the conversion circuit (2) and the lower Q bits of the J bits are applied, and a pulse having a pulse width corresponding to the content of the Q bits is applied to the level shift circuit (41). Two
Pulse forming circuit (42).

In the following, N = 18, and the input data a ₁₇ , a ₁₆ , a ₁₅ ..., A ₀
Of the higher order to the first D / A conversion circuit (1) a ₁₇ , a ₁₆ , ..., a
₁₀ 8-bit (M = 8), a second D / A conversion circuit (2) to the medium _{a 9, a 8, a 7} , 4 bits of a ₆ (K = 4), a third D / a converter subordinate a ₅ to (4), 6 bits of _{a 4 ... a 0 (J =} 6)
The case where it is configured to give

FIG. 2 shows a specific circuit configuration of the third D / A conversion circuit (4). Voltage dividing circuit (12) of the first D / A conversion circuit (1)
In the level shift circuit (41) provided at one end A of the first reference potential Vref1, resistors R ₁ , R ₂ , R ₃ , R ₄ and R ₅ are connected in series, and further, each resistor R ₁ , R ₂ , R ₃ , R ₄ , R ₅ have resistors R ₁₁ , R respectively
_{12, R 13, R 14,} R 15 and the switching transistor _{T 1, T 2, T 3} , T
₄ and T ₅ series circuits are connected in parallel. Similarly, the other end B and a level shift circuit provided in the second reference potential Vref2 of the voltage divider circuit (12) (41), resistor _{R 6, R 7, R 8} , R 9, R 10 are connected in series Further, the resistors R ₆ , R ₇ , R ₈ , R ₉ , R ₁₀ are respectively connected to the resistors R ₁₆ , R ₁₇ , R ₁₈ , R ₁₉ , R ₂₀ and the switching transistor T.
A series circuit of ₆ , T ₇ , T ₈ , T ₉ , T ₁₀ is connected in parallel. The upper 4 bits (P = 4) of J = 6 bits
a ₅ , a ₄ , a ₃ and a ₂ are switching transistors T ₁ and
It is directly applied to the gates of T ₂ , T ₃ , and T ₄ , and is applied to the gates of the switching transistors T ₆ , T ₇ , T ₈ , and T ₉ via an inverter (43). On the other hand, the pulse output C ₁ of the second pulse forming circuit (42) is applied to the gate of the switching transistor T ₅ , and
_The pulse output C ₁ is applied to the gate of ₁₀ through an inverter (44).

Here, assuming that the resistance values of the resistors R _{1 to} R ₂₀ and the resistance R of the voltage dividing circuit are as indicated by the symbols, the respective resistance values are determined so as to satisfy the following relational expression.

R _{1 to} R ₁₀ = R R ₁₁ = R ₁₅ = R ₁₆ = R ₂₀ = 255 x R (2 ^{K + J} -1) x RR ₁₂ = R ₁₇ = 127 x R (2 ^{K + J-1} -1) × RR ₁₃ = R ₁₈ = 63 × R (2 ^{K + J-2} -1) × RR ₁₄ = R ₁₉ = 31 × R (2 ^{K + J-3} -1) × R One end of voltage divider circuit (12) The resistance between A and Vref1
Assuming that the resistance value between R _A and the other end B and Vref2 is R _B , when the switching transistor T ₁ or T ₆ is turned on, R _A
Or R _B is reduced by R / 256.

Similarly, when T ₂ or T ₇ is turned on, R _A or R _B is turned on by R / 128 T ₃ or T ₈ , R _A or R _B is turned on by R / 64 T ₄ or T ₉ . In this case, R _{A and} R _B are each reduced by R / 32.

Further, the switching transistors T _{1 to} T ₄ and T _{6 to} T ₉ are
Since the inverter (43) turns on and off complementarily, if the resistance value R _A increases, the resistance value R _B decreases by the same value, and conversely, if the resistance value R _A decreases, the resistance value R _A decreases by the same value. _B
Will increase. In terms of voltage, the voltage difference between points A and B does not change, only the voltage level changes. Further, the resistance values R _A and R _B are 0, R / 256, 2R / 256 depending on the values of a ₅ , a ₄ , a ₃ and a _2.
… Changes to 15R / 256. That is, in terms of voltage, the voltage at points A and B is shifted to 16 gradations (4 bits) with a voltage width that is 1/256 of the voltage divided by the resistor R of the voltage dividing circuit (12). it can. Therefore, the voltage changes at points A and B are a ₅ , a
_The voltage corresponds to the weight of ₄ , a ₃ and a ₂ .

On the other hand, when the switching transistor T ₅ or T ₁₀ is turned on, the resistance values R _A and R _B decrease by R / 256 as in the case of the switching transistor T ₁ or T ₆ described above. The switching transistors T ₅ and T ₁₀ are also connected to the inverter (4
4) turn on and off complementarily, so point A and point B
The voltage difference between the voltage divider (1
It changes in 1/256 of the voltage divided in 2). That is, this corresponds to the weighted voltage of the data a ₂ . Therefore, by controlling the switching transistors T ₅ and T ₁₀ with the pulse width modulated pulse output C ₁ , the data a ₂
Lower order data will be D / A converted.

The second pulse forming circuit (42) counts the first and second stages of the counting circuit (22) of the second D / A conversion circuit (2).
Input Q ₁ and Q ₂ and a ₁ and a ₀ of the lower 2 bits (Q = 2) of the lower J = 6 bits of the data, and generate the number of pulses corresponding to the values of a ₁ and a _0. AND is output at fixed intervals.
It is composed of gates (45) (46) (47) and OR gates (48) (49).

FIG. 3 is a timing chart showing the operation of the second pulse forming circuit (42), in which the value represented by a ₁ and a ₀ is “0”,
The pulse output C ₁ in each of “1”, “2”, and “3” is shown. As shown in FIG. 3, within the fixed period t, pulses having a pulse width of t / 4 are output by the number represented by a ₁ and a ₀ . Further, since the outputs Q ₁ and Q ₂ of the counting circuit (22) are used, the period t is an integral fraction of one conversion cycle of the second D / A conversion circuit (2). In the present embodiment, since the first pulse forming circuit (23) of the second D / A conversion circuit (2) performs 4-bit PWM, the counting circuit (2
Since the outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ of 2) are used, the period t of the second pulse forming circuit (42) is the conversion cycle of the second D / A conversion circuit (2). It is 1/4 of that. Of course, the second
It is clear that if the pulse forming circuit (42) of (2) uses the count outputs Q ₃ and Q ₄ , the conversion period of the second D / A conversion circuit (2) and the period t become equal.

Therefore, the pulse output C _{1 of} the second pulse forming circuit (42)
By controlling the switching transistors T ₅ and T ₁₀ with the voltage level of the point A and the point B of the voltage dividing circuit (12) at a cycle corresponding to the conversion cycle of the second D / A conversion circuit (2). , A period of time based on the data of bits a ₁ and a ₀ is shifted upward by a voltage width 1/256 of the voltage divided by the voltage dividing circuit (12). As a result, in the first D / A conversion circuit (1), the adjacent 2 voltages V ₁ and V ₂ that are selectively output based on the 8-bit voltages a _{17 to} a ₁₀ are higher than the lower 6 bits. The voltage shift corresponding to the data of 4 bits a _{5 to} a ₂ and the lower 2
A pulse width modulated voltage is generated corresponding to the data of bits a ₁ and a ₂ .

In this way, when the number of bits is increased, the voltage shift circuit (12) of the first D / A conversion circuit (1) is obtained by performing pulse width modulation on the level shift circuit (41) with the increased number of bits.
By increasing the output of the counting circuit (22) of the second D / A conversion circuit (2) without increasing the resistance R of
The configuration of the second pulse forming circuit (42) is simplified, and it is not necessary to increase the frequency of clock pulses. In particular, by making the conversion cycle of the level shift circuit (41) equal to the conversion cycle of the second D / A conversion circuit (2), low power consumption and prevention of switching noise and unnecessary radiation can be achieved.

(G) Effect of the Invention As described above, according to the present invention, the characteristics of each of the conventional D / A conversion circuits in which the AM-type D / A conversion circuit and the PWM-type D / A conversion circuit are combined are impaired. It is possible to increase the number of bits of data to be converted, and to obtain a D / A conversion circuit with higher accuracy and higher performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of the third D / A conversion circuit shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a timing diagram of the pulse forming circuit, and FIG. 4 is a block diagram showing a conventional example. (1) …… First D / A conversion circuit, (2) …… D / A in Fig. 2
Conversion circuit, (4) …… Third D / A conversion circuit, (41) ……
Level shift circuit, (42) ... Second pulse forming circuit.

Continuation of the front page (56) References JP-A-62-181529 (JP, A) JP-A-57-23321 (JP, A) Actually developed JP-A-62-135237 (JP, U)

Claims (1)

[Claims] 1. A D / A converter for outputting an analog signal corresponding to N (= M + K + J) bits of digital data, wherein a decoder for decoding upper M bits of N bits of digital data, and a first reference potential The first D / having a voltage dividing circuit for dividing the voltage between the second reference potential and the second reference potential by 2 ^M resistors, and means for selectively extracting the adjacent two potentials according to the output of the decoder from the voltage dividing circuit. A conversion circuit, clock generating means for generating clock pulses, 2 ^K- ary counting circuit for counting clock pulses from the clock generating means, middle K bits of the N bits of digital data and counting by the counting circuit A first pulse forming circuit which receives an output as an input and outputs a pulse signal corresponding to the contents of the intermediate K-bit digital data, and the first D / D according to the pulse signal of the first pulse forming circuit. A second D / A conversion circuit having means for selecting and synthesizing adjacent two potentials output from the A conversion circuit; count output from the counting circuit and the lower J bits of the N-bit digital data Input the lower Q bits of and output a pulse signal according to the contents of the Q bits.
Pulse forming circuit, provided between the first reference potential and one end of the voltage dividing circuit and between the second reference potential and the other end of the voltage dividing circuit, and the upper P bits of the lower J bits The voltage at one end and the other end of the voltage dividing circuit is shifted in half ^{(K + Q)} steps of the voltage unit divided by the voltage dividing circuit based on the content of the data of the second pulse formation. A third D / A conversion circuit having a level shift circuit that shifts by 1/2 ^{(K + Q)} steps further than the shifted voltage during a period controlled by the pulse output of the circuit. Characterized D / A converter.