JP3233209B2 - Crystal oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a crystal oscillation circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 6 is well known as a crystal oscillation circuit. In the crystal oscillation circuit shown in FIG. 6, the control signals S1 to Sn
This is a circuit that changes the oscillation frequency by changing the capacitance value of the weighted capacitances Cval1 to Cvaln, which are given to the gates 1 to Mn and viewed from the crystal unit XTAL. The capacitance value of the capacitance Cvaln is 2 ⁿ times the capacitance value of the capacitance Cval1.

A crystal unit XTAL can be represented by a series-parallel circuit of LCR, and its equivalent circuit is a capacitance C and a coil L
And the resistor R are connected in series, and the capacitance C ₀ is connected in parallel. Generally, the oscillation frequency f ₀ is expressed by the following equation (1), where CL is the load capacitance. The oscillation frequency changes.

[0004]

(Equation 1) The operation of the conventional crystal oscillation circuit will be described with reference to FIG. At the point A in the figure, an oscillation waveform represented by the above-described equation 1 is generated, and the waveform is output to the output terminal OUT.
Output to When changing the oscillation frequency, the signals S1 to S
When n is changed from low level to high level, the capacitance Cval1
The waveform at the point A is distorted in order to charge the electric charges to Cvaln, and the duty of the output terminal OUT (Duty). When the ratio of the high level and the ratio of the high level to the low level is 1: 1, Duty = (Referred to as 50%).

At this time, the on-resistance value and the flowing current value of the N-channel MOS transistor are Ron and i, the switching capacitance value is ΔCL, the voltage value at point A is V, and the resistance values of resistors 3 and 4 are R3 and R4. When the voltage value of the power supply 6 is VDD and the time is t, the voltage V at the point A is expressed by the following equation (2). The i in the mathematical formula shown in the above-mentioned formula 2 is the following formula 3
It is calculated by the mathematical formula shown in FIG.

[0006]

(Equation 2)

[0007]

(Equation 3) The voltage drop at the point A due to the switching of the N-channel MOS transistors M1 to Mn is expressed by the equation shown in the above equation (2), and the second term on the right side corresponds to the fluctuation due to the transient response. From this result, it is clear that the fluctuation at the point A increases as the switching capacitance value ΔCL increases.

The relationship between the capacitance value and the duty at this time is obtained by simulation, as shown in FIG. 4. The greater the capacitance value, the greater the fluctuation of the duty. As an example, in the case of a crystal oscillation circuit in which a capacitance value is weighted, when switching from 1C to 16C (in the case of 5 bits), a maximum duty change of 51% to 61% occurs.

[0009]

In the above-described conventional crystal oscillation circuit, when the oscillation frequency is varied, the duty fluctuates due to the transient response of the N-channel MOS transistors M1 to Mn and the capacitor for varying the frequency.
Since the output of the oscillation circuit is mainly treated as the main clock of the digital circuit, when a change in the duty occurs, a timing shift occurs, which causes a problem that an operation failure occurs.

An object of the present invention is to provide a crystal oscillation circuit that can reduce a duty fluctuation by using a bit conversion circuit, a delay circuit, and a minute unit capacitance.

[0011]

According to the present invention, a source follower circuit, a first capacitor connected between an input and an output of the source follower circuit, and a capacitor connected between an output of the source follower circuit and ground. A second capacitor, and means for applying a bias voltage to an input of the source follower circuit;
In a Colpitts-type crystal oscillation circuit in which a crystal oscillator is connected between the input of the source follower circuit and the ground, the first and second n (n is an integer) minute unit capacitors each having one end connected to the ground, To the second ⁿ (n is an integer) N-channel MOS transistors,
And each drain is connected in common, the common connection point is connected to the input of the source follower circuit,
The gates of the second ^n- channel N-channel MOS transistors are respectively connected to the output of a bit conversion control unit. The bit conversion control unit converts an n-bit input signal into a 2 ^n- bit signal; A crystal oscillation circuit comprising a delay circuit for converting a change in an ^n- bit signal into a signal change for each unit bit is obtained.

[0012]

Furthermore, according to the present invention, the bit conversion circuit, the switch of the switches, second of the (1,1) to the first input signal in the input signal of the n-bit (2 ^{n, 1)} From the first-stage switch group to the (1, n) -th switch to the (2 ⁿ , n) ^-th switch for the n-th input signal of the n-bit input signal. and, the resistance of the first resistor, second 2 ⁿ respectively the 2 ⁿ columns switches located in the first column switch group-th first 2 ⁿ columns located in the first row viewed from the input signal side A crystal oscillation circuit characterized by being provided and obtained is obtained.

Furthermore, according to the present invention, the delay circuit is constituted by OR circuit of the first OR circuit, second 2 ^n, wherein one end of the resistor-first resistance of the 2 ⁿ each second ⁿ OR gates connected to the inputs of the first OR gate and the second OR gate.
The output of the OR circuit of ⁿ is connected to an input of the OR circuit of the (2 n ^-1), the first OR circuit, second 2 ⁿ logical sum times the
The output of the path is connected to the gates of the first to the second ^n- channel MOS transistors, respectively, to obtain a crystal oscillation circuit.

Furthermore, according to the present invention, the bit conversion circuit, the switch of the switches, second of the (1,1) to the first input signal in the input signal of the n-bit (2 ^{n, 1)} From the first-stage switch group to the (1, n) -th switch to the (2 ⁿ , n) ^-th switch for the n-th input signal of the n-bit input signal. and, wherein the input signal side viewed from the first row each first current source, second 2 ⁿ of the current to the first 2 ⁿ columns switch unit located switches ~ th the 2 ⁿ row positioned in the first column A crystal oscillation circuit characterized by being provided with a source is obtained.

Furthermore, according to the present invention, the delay circuit is constituted by OR circuit of the first OR circuit, second 2 ^n, one end of a current source - a first current source of the first 2 ^n, respectively Second
ⁿ OR circuits to the inputs of the first OR circuit;
The output of the OR circuit of the 2 ⁿ is connected to an input of the OR circuit of the (2 n ^-1), the logic of the first OR circuit, second 2 ⁿ
The output of the sum circuit is connected to the gates of the first to ^n-th N-channel MOS transistors, respectively, to obtain a crystal oscillation circuit.

[0017]

The circuit of the present invention uses a bit conversion circuit, a delay circuit, and a unit capacitor to reduce the transient response when the frequency is changed, and to reduce the duty fluctuation.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. First, the operation of the crystal oscillation circuit according to the first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a diagram showing a first embodiment of the crystal oscillation circuit of the present invention. FIG. 2 is a diagram showing a first embodiment of a bit conversion circuit and a delay circuit used in the present invention. FIG. 3 is a time chart of the crystal oscillation circuit of the present invention.

This circuit also generates an oscillation waveform at the point A, which is represented by the above-mentioned equation (1), and outputs the oscillation waveform to the output terminal OUT. By using the bit conversion circuit 1 and the delay circuit 2 as shown, the n-bit signals of the control signals S1 to Sn are converted into the 2 ⁿ -bit signals of the outputs D1 to D2 ⁿ and the output D
1 to D2 ⁿ are sequentially delayed so that an N-channel type M
A point input to the OS transistors M1 and M2 ^n, is that doing variable frequency using infinitesimal unit capacity Cval1~Cval2 ^n. Other points are the same as the conventional one.
The capacitance values of the minute unit capacitances Cval1 to Cval2 ⁿ are equal.

As shown in FIG. 2, the bit conversion circuit 1
Switch SW (1, 1) for input signal S1 in the first stage
From the first stage to the switch SW (2 ⁿ , 1), and the switch S for the input signal S2 at the second stage.
The second from W (1,2) to switch SW (2 ⁿ , 2)
A stage switch group is arranged, and the switch SW (1, n) for the input signal Sn is switched to the switch SW (2 ⁿ ,
the first n-stage switch group to n) are arranged, respectively the 2 ⁿ columns switches located in the first column switch group-th first 2 ⁿ columns located in the first row viewed from the input signal side first One
It is constituted by providing an anti-R (1) ~ a ^{2 n} resistor R ⁽² n). Switch SW (1,1) to Switch SW (1,1)
n), the path of the resistor R (1), and the switch SW (2, 1).
~ The path of the switch SW (2, n) and the resistor R (2),
..Switch SW (2 ⁿ , 1) to switch SW (2 ⁿ , 1)
n) and the path of the resistor R (2 ⁿ ) are connected in parallel.
Logical sum of the first resistor R (1) to the ^{2 n} resistor R ⁽² n) of the one end a first OR circuit OR, respectively (1) to the ^{2 n}
It is connected to the input of the circuit OR (2 ⁿ ) . The output of the OR circuit OR of the ^{2 n (2 n)} is connected to an input of the OR circuit OR of ^{(2 n -1) (2 n} -1). Delay circuit 2 first OR circuit OR (1) ~ the ^{2 n} logical sum times the
The path OR (2 ⁿ ) . First OR circuit O
Output der of R (1) ~ the ^{2 n} of the OR circuit OR ^{(2 n)}
Outputs D (1) to D (2 ⁿ ) are N-channel type M
It is connected to the gate of the OS transistor M1~M2 ^n.

Now, if n = 2, the time chart of the bit conversion circuit and the delay circuit is as shown in FIG.
In the case where D1 to D4 are changed one bit at a time, the previous state is maintained and the state is changed one bit at a time, and when several bits are changed, D1 is changed according to the change of the input signals S2 and S1. The signals D4 to D4 are sequentially switched with a slight delay difference from D4 to D3 to D2. By performing such an operation, simultaneous operation of the capacitors is eliminated, and the circuit is stabilized. Further, by using 2 ⁿ minute unit capacitors as shown in FIG. 1, the time for charging each capacitor can be shortened, and the influence of the transient response can be minimized.

That is, if the frequency is further varied by using the bit conversion circuit 1 and the delay circuit 2 and by the minute unit capacitance, ΔCL = 0 can be considered. Therefore, the voltage drop at the point A of this circuit is expressed by the above equation (2). It is obvious that only the first term on the right side of the mathematical expression shown in FIG. 4A does not cause distortion due to the transient response, and that the variation in the Tuty is unlikely to occur. That is, if the capacitance value 1C in FIG. 4 is set as the unit capacitance, it can be regarded as a continuous change of 1C, and the fluctuation of the duty becomes 51%.
Compared to a 5-bit weighted crystal oscillator, 1
About 0% improvement is expected. Further, if 2C is set as the unit capacitance value, it can be regarded as a continuous change of 2C, so that the fluctuation of the duty becomes 52%, and an improvement of about 9% can be expected.

Since the outputs D1 to D4 are switched with a slight delay difference, the time from when the input signals S2 and S1 are switched to when the frequency is determined is hardly impaired as compared with the conventional case.

FIG. 5 is a circuit diagram showing a second embodiment of the bit conversion circuit 1 and the delay circuit 2 in the crystal oscillation circuit of FIG. 1 of the present invention. The bit conversion circuit and the delay circuit according to the second embodiment differ from the bit conversion circuit and the delay circuit according to the first embodiment only in the configuration of the bit conversion circuit. The bit conversion circuit according to the second embodiment includes a first resistance R (1) to a second ⁿ resistance R (2 ) that constitute the bit conversion circuit according to the first embodiment.
ⁿ ) instead of the first current source ID (1) to the second ⁿ current
The source ID (2 ⁿ ) is provided. The bit conversion circuit and the delay circuit according to the first embodiment can be applied to the crystal oscillation circuit shown in FIG. 1 instead of the bit conversion circuit and the delay circuit shown in FIG. An operation similar to that of the circuit is performed, and a similar effect is obtained.

[0026]

As described above, according to the crystal oscillation circuit of the present invention, simultaneous operation of a large capacity is eliminated by using a bit conversion circuit, a delay circuit, and a minute unit capacity, thereby alleviating a transient response. Therefore, the effect of reducing the fluctuation of the duty can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a crystal oscillation circuit according to the present invention.

FIG. 2 is a diagram showing a first embodiment of a bit conversion circuit and a delay circuit used in the present invention.

FIG. 3 is a time chart of the crystal oscillation circuit of the present invention.

FIG. 4 is a graph showing a relationship between a duty and a capacitance value.

FIG. 5 is a diagram showing a second embodiment of a bit conversion circuit and a delay circuit used in the present invention.

FIG. 6 is a diagram showing an embodiment of a conventional crystal oscillation circuit.

[Explanation of symbols]

1 bit conversion circuit 2 delay circuit 3, 4, R (1) to R (2 ⁿ ) resistor 6 voltage source XTAL crystal oscillator M1 to M2 ⁿ , TR N channel type MOS transistor ID (1) to ID (2 ⁿ ) Current source SW (1, 1) to SW (2 ⁿ , n) Switch OR (1) to OR (2 ⁿ ) OR circuit IN input terminal OUT output terminal S1 to Sn input signal C1, C2 capacitance Cval1 to Cval2 ⁿ minute Unit capacity

Claims (5)

(57) [Claims] 1. A source follower circuit, a first capacitor connected between an input and an output of the source follower circuit, a second capacitor connected between an output of the source follower circuit and ground, and a source follower circuit. Means for applying a bias voltage to an input, and a Colpitts-type crystal oscillation circuit in which a crystal oscillator is connected between the input of the source follower circuit and the ground;
(N is an integer) at the other end of the minute unit capacity
The sources of the 2 ⁿ (n is an integer) N-channel MOS transistors are connected, their drains are connected in common, the common connection point is connected to the input of the source follower circuit, and the first to second ⁿ are connected. the gate of the n-channel type MOS transistor are respectively connected to the output of the bit conversion control unit, 2 ⁿ bit input signal of the bit conversion control unit n bits
A bit conversion circuit for converting the ²ⁿ bits
A delay circuit that converts a signal change into a signal change for each unit bit.
Crystal oscillator circuit, characterized in that it is constituted by the road. Wherein said bit conversion circuit, the first stage switch to the switches of the switch, second (2 ^{n, 1)} of the (1,1) to the first input signal in the input signal of the n bits A (1, n) -th to (2 ⁿ , n) -th switch group for the n-th input signal of the n-bit input signal from the group; From the first row switch group to the second ⁿ
2. The crystal oscillation circuit according to claim 1, wherein first to second ⁿ resistors are provided for each of the second ^n-th row switch groups located in the column. 3. The delay circuit comprises a first OR circuit and a second OR circuit.
is constituted by OR circuit of ^n, the one end of the resistor-first resistance of the 2 ⁿ is connected to an input of the OR circuit-first OR circuit of the 2 ^n, respectively, the logical sum of the 2 ⁿ The output of the circuit is connected to the input of the (2 ⁿ -1) ^-th OR circuit and the first
3. The crystal according to claim 1, wherein the outputs of the OR circuit to the ( ^{2n) -th} OR circuit are respectively connected to the gates of the first to ( ^{2n) -th} N-channel MOS transistors. Oscillator circuit. 4. A first-stage switch from a (1,1) th switch to a (2 ⁿ , 1) ^th switch for a first input signal of the n-bit input signals. A (1, n) -th to (2 ⁿ , n) -th switch group for the n-th input signal of the n-bit input signal from the group; From the first row switch group to the second ⁿ
2. The crystal oscillation circuit according to claim 1, wherein first to second ⁿ current sources are provided for each of the second ^n-th column switch groups located in the column. 5. The delay circuit comprises a first OR circuit and a second OR circuit.
ⁿ OR circuits, wherein the second ^n-th current source to the first
One end of the current source is connected to an input of the OR circuit-first OR circuit of the 2 ⁿ respectively, the output of the OR circuit of the 2 ⁿ input OR circuit of the (2 n ^-1) Connected to the
5. The output of each of the first to second ^n-th OR circuits is connected to the gate of each of the first to second ^n- channel MOS transistors.
Crystal oscillator circuit as described.